X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32x.c;h=0edadfd2ae82e90b98eedcd24d8d2f5265b41120;hp=75dcf3b57c67cf147942dcaef6fd32d5d3e56979;hb=7bbd6c76838ffc639226897328d8ec7069b1769d;hpb=1c5c57ec8e3f285cc81d4ad101edccb82b721beb diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c index 75dcf3b57c..0edadfd2ae 100644 --- a/src/flash/nor/stm32x.c +++ b/src/flash/nor/stm32x.c @@ -25,12 +25,85 @@ #endif #include "imp.h" -#include "stm32x.h" #include #include #include +/* stm32x register locations */ + +#define STM32_FLASH_ACR 0x40022000 +#define STM32_FLASH_KEYR 0x40022004 +#define STM32_FLASH_OPTKEYR 0x40022008 +#define STM32_FLASH_SR 0x4002200C +#define STM32_FLASH_CR 0x40022010 +#define STM32_FLASH_AR 0x40022014 +#define STM32_FLASH_OBR 0x4002201C +#define STM32_FLASH_WRPR 0x40022020 + +/* option byte location */ + +#define STM32_OB_RDP 0x1FFFF800 +#define STM32_OB_USER 0x1FFFF802 +#define STM32_OB_DATA0 0x1FFFF804 +#define STM32_OB_DATA1 0x1FFFF806 +#define STM32_OB_WRP0 0x1FFFF808 +#define STM32_OB_WRP1 0x1FFFF80A +#define STM32_OB_WRP2 0x1FFFF80C +#define STM32_OB_WRP3 0x1FFFF80E + +/* FLASH_CR register bits */ + +#define FLASH_PG (1 << 0) +#define FLASH_PER (1 << 1) +#define FLASH_MER (1 << 2) +#define FLASH_OPTPG (1 << 4) +#define FLASH_OPTER (1 << 5) +#define FLASH_STRT (1 << 6) +#define FLASH_LOCK (1 << 7) +#define FLASH_OPTWRE (1 << 9) + +/* FLASH_SR register bits */ + +#define FLASH_BSY (1 << 0) +#define FLASH_PGERR (1 << 2) +#define FLASH_WRPRTERR (1 << 4) +#define FLASH_EOP (1 << 5) + +/* STM32_FLASH_OBR bit definitions (reading) */ + +#define OPT_ERROR 0 +#define OPT_READOUT 1 +#define OPT_RDWDGSW 2 +#define OPT_RDRSTSTOP 3 +#define OPT_RDRSTSTDBY 4 + +/* register unlock keys */ + +#define KEY1 0x45670123 +#define KEY2 0xCDEF89AB + + +struct stm32x_options +{ + uint16_t RDP; + uint16_t user_options; + uint16_t protection[4]; +}; + +struct stm32x_flash_bank +{ + struct stm32x_options option_bytes; + struct working_area *write_algorithm; + int ppage_size; + int probed; +}; + +struct stm32x_mem_layout { + uint32_t sector_start; + uint32_t sector_size; +}; + static int stm32x_mass_erase(struct flash_bank *bank); /* flash bank stm32x 0 0 @@ -54,33 +127,56 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command) return ERROR_OK; } -static uint32_t stm32x_get_flash_status(struct flash_bank *bank) +static int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status) { struct target *target = bank->target; - uint32_t status; - - target_read_u32(target, STM32_FLASH_SR, &status); - - return status; + return target_read_u32(target, STM32_FLASH_SR, status); } -static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout) +static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout) { struct target *target = bank->target; uint32_t status; + int retval = ERROR_OK; /* wait for busy to clear */ - while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0)) + for (;;) { + retval = stm32x_get_flash_status(bank, &status); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("status: 0x%" PRIx32 "", status); + if ((status & FLASH_BSY) == 0) + break; + if (timeout-- <= 0) + { + LOG_ERROR("timed out waiting for flash"); + return ERROR_FAIL; + } alive_sleep(1); } + + if (status & FLASH_WRPRTERR) + { + LOG_ERROR("stm32x device protected"); + retval = ERROR_FAIL; + } + + if (status & FLASH_PGERR) + { + LOG_ERROR("stm32x device programming failed"); + retval = ERROR_FAIL; + } + /* Clear but report errors */ if (status & (FLASH_WRPRTERR | FLASH_PGERR)) { + /* If this operation fails, we ignore it and report the original + * retval + */ target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR); } - return status; + return retval; } static int stm32x_read_options(struct flash_bank *bank) @@ -92,7 +188,9 @@ static int stm32x_read_options(struct flash_bank *bank) stm32x_info = bank->driver_priv; /* read current option bytes */ - target_read_u32(target, STM32_FLASH_OBR, &optiondata); + int retval = target_read_u32(target, STM32_FLASH_OBR, &optiondata); + if (retval != ERROR_OK) + return retval; stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07); stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5; @@ -101,7 +199,9 @@ static int stm32x_read_options(struct flash_bank *bank) LOG_INFO("Device Security Bit Set"); /* each bit refers to a 4bank protection */ - target_read_u32(target, STM32_FLASH_WRPR, &optiondata); + retval = target_read_u32(target, STM32_FLASH_WRPR, &optiondata); + if (retval != ERROR_OK) + return retval; stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata; stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8); @@ -115,7 +215,6 @@ static int stm32x_erase_options(struct flash_bank *bank) { struct stm32x_flash_bank *stm32x_info = NULL; struct target *target = bank->target; - uint32_t status; stm32x_info = bank->driver_priv; @@ -123,23 +222,33 @@ static int stm32x_erase_options(struct flash_bank *bank) stm32x_read_options(bank); /* unlock flash registers */ - target_write_u32(target, STM32_FLASH_KEYR, KEY1); - target_write_u32(target, STM32_FLASH_KEYR, KEY2); + int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2); + if (retval != ERROR_OK) + return retval; /* unlock option flash registers */ - target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1); - target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2); + retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2); + if (retval != ERROR_OK) + return retval; /* erase option bytes */ - target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE); - target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; /* clear readout protection and complementary option bytes * this will also force a device unlock if set */ @@ -152,82 +261,87 @@ static int stm32x_write_options(struct flash_bank *bank) { struct stm32x_flash_bank *stm32x_info = NULL; struct target *target = bank->target; - uint32_t status; stm32x_info = bank->driver_priv; /* unlock flash registers */ - target_write_u32(target, STM32_FLASH_KEYR, KEY1); - target_write_u32(target, STM32_FLASH_KEYR, KEY2); + int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2); + if (retval != ERROR_OK) + return retval; /* unlock option flash registers */ - target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1); - target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2); + retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2); + if (retval != ERROR_OK) + return retval; /* program option bytes */ - target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE); + if (retval != ERROR_OK) + return retval; /* write user option byte */ - target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; /* write protection byte 1 */ - target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; /* write protection byte 2 */ - target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; /* write protection byte 3 */ - target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; /* write protection byte 4 */ - target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; /* write readout protection bit */ - target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP); - - status = stm32x_wait_status_busy(bank, 10); + retval = target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; + retval = stm32x_wait_status_busy(bank, 10); + if (retval != ERROR_OK) + return retval; - target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } @@ -250,7 +364,9 @@ static int stm32x_protect_check(struct flash_bank *bank) /* medium density - each bit refers to a 4bank protection * high density - each bit refers to a 2bank protection */ - target_read_u32(target, STM32_FLASH_WRPR, &protection); + int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection); + if (retval != ERROR_OK) + return retval; /* medium density - each protection bit is for 4 * 1K pages * high density - each protection bit is for 2 * 2K pages */ @@ -308,7 +424,6 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last) { struct target *target = bank->target; int i; - uint32_t status; if (bank->target->state != TARGET_HALTED) { @@ -322,25 +437,35 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last) } /* unlock flash registers */ - target_write_u32(target, STM32_FLASH_KEYR, KEY1); - target_write_u32(target, STM32_FLASH_KEYR, KEY2); + int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2); + if (retval != ERROR_OK) + return retval; for (i = first; i <= last; i++) { - target_write_u32(target, STM32_FLASH_CR, FLASH_PER); - target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset); - target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT); + if (retval != ERROR_OK) + return retval; - status = stm32x_wait_status_busy(bank, 10); + retval = stm32x_wait_status_busy(bank, 100); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - return ERROR_FLASH_OPERATION_FAILED; - if (status & FLASH_PGERR) - return ERROR_FLASH_OPERATION_FAILED; bank->sectors[i].is_erased = 1; } - target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } @@ -362,15 +487,19 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last) return ERROR_TARGET_NOT_HALTED; } - if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size)) + if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && + (last + 1) % stm32x_info->ppage_size)) { - LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size); + LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", + stm32x_info->ppage_size); return ERROR_FLASH_SECTOR_INVALID; } /* medium density - each bit refers to a 4bank protection * high density - each bit refers to a 2bank protection */ - target_read_u32(target, STM32_FLASH_WRPR, &protection); + int retval = target_read_u32(target, STM32_FLASH_WRPR, &protection); + if (retval != ERROR_OK) + return retval; prot_reg[0] = (uint16_t)protection; prot_reg[1] = (uint16_t)(protection >> 8); @@ -432,7 +561,8 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last) return stm32x_write_options(bank); } -static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count) +static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, + uint32_t offset, uint32_t count) { struct stm32x_flash_bank *stm32x_info = bank->driver_priv; struct target *target = bank->target; @@ -443,45 +573,52 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t struct armv7m_algorithm armv7m_info; int retval = ERROR_OK; - uint8_t stm32x_flash_write_code[] = { + /* see contib/loaders/flash/stm32x.s for src */ + + static const uint8_t stm32x_flash_write_code[] = { + /* #define STM32_FLASH_CR_OFFSET 0x10 */ + /* #define STM32_FLASH_SR_OFFSET 0x0C */ /* write: */ - 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */ - 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */ - 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */ - 0x23, 0x60, /* str r3, [r4, #0] */ - 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */ - 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */ + 0xdf, 0xf8, 0x20, 0x40, /* ldr r4, STM32_FLASH_BASE */ + /* write_half_word: */ + 0x01, 0x23, /* movs r3, #0x01 */ + 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */ + 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */ + 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */ /* busy: */ - 0x2B, 0x68, /* ldr r3, [r5, #0] */ - 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */ - 0xFB, 0xD0, /* beq busy */ - 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */ - 0x01, 0xD1, /* bne exit */ - 0x01, 0x3A, /* subs r2, r2, #1 */ - 0xED, 0xD1, /* bne write */ + 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */ + 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */ + 0xfb, 0xd0, /* beq busy */ + 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */ + 0x01, 0xd1, /* bne exit */ + 0x01, 0x3a, /* subs r2, r2, #0x01 */ + 0xf0, 0xd1, /* bne write_half_word */ /* exit: */ - 0xFE, 0xE7, /* b exit */ - 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */ - 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */ + 0x00, 0xbe, /* bkpt #0x00 */ + 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ }; /* flash write code */ - if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK) + if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), + &stm32x_info->write_algorithm) != ERROR_OK) { LOG_WARNING("no working area available, can't do block memory writes"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; }; - if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK) + if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, + sizeof(stm32x_flash_write_code), + (uint8_t*)stm32x_flash_write_code)) != ERROR_OK) return retval; /* memory buffer */ - while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) + while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { buffer_size /= 2; if (buffer_size <= 256) { - /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */ + /* if we already allocated the writing code, but failed to get a + * buffer, free the algorithm */ if (stm32x_info->write_algorithm) target_free_working_area(target, stm32x_info->write_algorithm); @@ -500,20 +637,23 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t while (count > 0) { - uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count; + uint32_t thisrun_count = (count > (buffer_size / 2)) ? + (buffer_size / 2) : count; - if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK) + if ((retval = target_write_buffer(target, source->address, + thisrun_count * 2, buffer)) != ERROR_OK) break; buf_set_u32(reg_params[0].value, 0, 32, source->address); buf_set_u32(reg_params[1].value, 0, 32, address); buf_set_u32(reg_params[2].value, 0, 32, thisrun_count); - if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \ - stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK) + if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, + stm32x_info->write_algorithm->address, + 0, + 10000, &armv7m_info)) != ERROR_OK) { LOG_ERROR("error executing stm32x flash write algorithm"); - retval = ERROR_FLASH_OPERATION_FAILED; break; } @@ -522,7 +662,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t LOG_ERROR("flash memory not erased before writing"); /* Clear but report errors */ target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR); - retval = ERROR_FLASH_OPERATION_FAILED; + retval = ERROR_FAIL; break; } @@ -531,7 +671,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t LOG_ERROR("flash memory write protected"); /* Clear but report errors */ target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR); - retval = ERROR_FLASH_OPERATION_FAILED; + retval = ERROR_FAIL; break; } @@ -551,14 +691,14 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t return retval; } -static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count) +static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, + uint32_t offset, uint32_t count) { struct target *target = bank->target; uint32_t words_remaining = (count / 2); uint32_t bytes_remaining = (count & 0x00000001); uint32_t address = bank->base + offset; uint32_t bytes_written = 0; - uint8_t status; int retval; if (bank->target->state != TARGET_HALTED) @@ -574,8 +714,12 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offse } /* unlock flash registers */ - target_write_u32(target, STM32_FLASH_KEYR, KEY1); - target_write_u32(target, STM32_FLASH_KEYR, KEY2); + retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2); + if (retval != ERROR_OK) + return retval; /* multiple half words (2-byte) to be programmed? */ if (words_remaining > 0) @@ -589,11 +733,6 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offse * we use normal (slow) single dword accesses */ LOG_WARNING("couldn't use block writes, falling back to single memory accesses"); } - else if (retval == ERROR_FLASH_OPERATION_FAILED) - { - LOG_ERROR("flash writing failed with error code: 0x%x", retval); - return ERROR_FLASH_OPERATION_FAILED; - } } else { @@ -603,26 +742,24 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offse } } + if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)) + return retval; + while (words_remaining > 0) { uint16_t value; memcpy(&value, buffer + bytes_written, sizeof(uint16_t)); - target_write_u32(target, STM32_FLASH_CR, FLASH_PG); - target_write_u16(target, address, value); - - status = stm32x_wait_status_busy(bank, 5); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG); + if (retval != ERROR_OK) + return retval; + retval = target_write_u16(target, address, value); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - { - LOG_ERROR("flash memory not erased before writing"); - return ERROR_FLASH_OPERATION_FAILED; - } - if (status & FLASH_PGERR) - { - LOG_ERROR("flash memory write protected"); - return ERROR_FLASH_OPERATION_FAILED; - } + retval = stm32x_wait_status_busy(bank, 5); + if (retval != ERROR_OK) + return retval; bytes_written += 2; words_remaining--; @@ -634,26 +771,19 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offse uint16_t value = 0xffff; memcpy(&value, buffer + bytes_written, bytes_remaining); - target_write_u32(target, STM32_FLASH_CR, FLASH_PG); - target_write_u16(target, address, value); - - status = stm32x_wait_status_busy(bank, 5); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_PG); + if (retval != ERROR_OK) + return retval; + retval = target_write_u16(target, address, value); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - { - LOG_ERROR("flash memory not erased before writing"); - return ERROR_FLASH_OPERATION_FAILED; - } - if (status & FLASH_PGERR) - { - LOG_ERROR("flash memory write protected"); - return ERROR_FLASH_OPERATION_FAILED; - } + retval = stm32x_wait_status_busy(bank, 5); + if (retval != ERROR_OK) + return retval; } - target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); - - return ERROR_OK; + return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); } static int stm32x_probe(struct flash_bank *bank) @@ -665,21 +795,19 @@ static int stm32x_probe(struct flash_bank *bank) uint32_t device_id; int page_size; - if (bank->target->state != TARGET_HALTED) - { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - stm32x_info->probed = 0; /* read stm32 device id register */ - target_read_u32(target, 0xE0042000, &device_id); + int retval = target_read_u32(target, 0xE0042000, &device_id); + if (retval != ERROR_OK) + return retval; LOG_INFO("device id = 0x%08" PRIx32 "", device_id); - /* get flash size from target */ - if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK) + /* get flash size from target. */ + retval = target_read_u16(target, 0x1FFFF7E0, &num_pages); + if (retval != ERROR_OK) { + LOG_WARNING("failed reading flash size, default to max target family"); /* failed reading flash size, default to max target family */ num_pages = 0xffff; } @@ -744,10 +872,25 @@ static int stm32x_probe(struct flash_bank *bank) num_pages = 256; } } + else if ((device_id & 0x7ff) == 0x420) + { + /* value line density - we have 1k pages + * 4 pages for a protection area */ + page_size = 1024; + stm32x_info->ppage_size = 4; + + /* check for early silicon */ + if (num_pages == 0xffff) + { + /* number of sectors may be incorrrect on early silicon */ + LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash"); + num_pages = 128; + } + } else { LOG_WARNING("Cannot identify target as a STM32 family."); - return ERROR_FLASH_OPERATION_FAILED; + return ERROR_FAIL; } LOG_INFO("flash size = %dkbytes", num_pages); @@ -755,6 +898,12 @@ static int stm32x_probe(struct flash_bank *bank) /* calculate numbers of pages */ num_pages /= (page_size / 1024); + if (bank->sectors) + { + free(bank->sectors); + bank->sectors = NULL; + } + bank->base = 0x08000000; bank->size = (num_pages * page_size); bank->num_sectors = num_pages; @@ -788,14 +937,16 @@ COMMAND_HANDLER(stm32x_handle_part_id_command) } #endif -static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size) +static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size) { struct target *target = bank->target; uint32_t device_id; int printed; /* read stm32 device id register */ - target_read_u32(target, 0xE0042000, &device_id); + int retval = target_read_u32(target, 0xE0042000, &device_id); + if (retval != ERROR_OK) + return retval; if ((device_id & 0x7ff) == 0x410) { @@ -885,10 +1036,31 @@ static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size) break; } } + else if ((device_id & 0x7ff) == 0x420) + { + printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: "); + buf += printed; + buf_size -= printed; + + switch (device_id >> 16) + { + case 0x1000: + snprintf(buf, buf_size, "A"); + break; + + case 0x1001: + snprintf(buf, buf_size, "Z"); + break; + + default: + snprintf(buf, buf_size, "unknown"); + break; + } + } else { snprintf(buf, buf_size, "Cannot identify target as a stm32x\n"); - return ERROR_FLASH_OPERATION_FAILED; + return ERROR_FAIL; } return ERROR_OK; @@ -978,7 +1150,9 @@ COMMAND_HANDLER(stm32x_handle_unlock_command) return ERROR_OK; } - command_print(CMD_CTX, "stm32x unlocked"); + command_print(CMD_CTX, "stm32x unlocked.\n" + "INFO: a reset or power cycle is required " + "for the new settings to take effect."); return ERROR_OK; } @@ -1010,7 +1184,9 @@ COMMAND_HANDLER(stm32x_handle_options_read_command) return ERROR_TARGET_NOT_HALTED; } - target_read_u32(target, STM32_FLASH_OBR, &optionbyte); + retval = target_read_u32(target, STM32_FLASH_OBR, &optionbyte); + if (retval != ERROR_OK) + return retval; command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte); if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1)) @@ -1114,7 +1290,9 @@ COMMAND_HANDLER(stm32x_handle_options_write_command) return ERROR_OK; } - command_print(CMD_CTX, "stm32x write options complete"); + command_print(CMD_CTX, "stm32x write options complete.\n" + "INFO: a reset or power cycle is required " + "for the new settings to take effect."); return ERROR_OK; } @@ -1122,7 +1300,6 @@ COMMAND_HANDLER(stm32x_handle_options_write_command) static int stm32x_mass_erase(struct flash_bank *bank) { struct target *target = bank->target; - uint32_t status; if (target->state != TARGET_HALTED) { @@ -1131,28 +1308,28 @@ static int stm32x_mass_erase(struct flash_bank *bank) } /* unlock option flash registers */ - target_write_u32(target, STM32_FLASH_KEYR, KEY1); - target_write_u32(target, STM32_FLASH_KEYR, KEY2); + int retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2); + if (retval != ERROR_OK) + return retval; /* mass erase flash memory */ - target_write_u32(target, STM32_FLASH_CR, FLASH_MER); - target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT); - - status = stm32x_wait_status_busy(bank, 10); - - target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER); + if (retval != ERROR_OK) + return retval; + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_WRPRTERR) - { - LOG_ERROR("stm32x device protected"); - return ERROR_OK; - } + retval = stm32x_wait_status_busy(bank, 100); + if (retval != ERROR_OK) + return retval; - if (status & FLASH_PGERR) - { - LOG_ERROR("stm32x device programming failed"); - return ERROR_OK; - } + retval = target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } @@ -1172,7 +1349,8 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) if (ERROR_OK != retval) return retval; - if (stm32x_mass_erase(bank) == ERROR_OK) + retval = stm32x_mass_erase(bank); + if (retval == ERROR_OK) { /* set all sectors as erased */ for (i = 0; i < bank->num_sectors; i++) @@ -1187,41 +1365,41 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command) command_print(CMD_CTX, "stm32x mass erase failed"); } - return ERROR_OK; + return retval; } static const struct command_registration stm32x_exec_command_handlers[] = { { .name = "lock", - .handler = &stm32x_handle_lock_command, + .handler = stm32x_handle_lock_command, .mode = COMMAND_EXEC, .usage = "bank_id", .help = "Lock entire flash device.", }, { .name = "unlock", - .handler = &stm32x_handle_unlock_command, + .handler = stm32x_handle_unlock_command, .mode = COMMAND_EXEC, .usage = "bank_id", .help = "Unlock entire protected flash device.", }, { .name = "mass_erase", - .handler = &stm32x_handle_mass_erase_command, + .handler = stm32x_handle_mass_erase_command, .mode = COMMAND_EXEC, .usage = "bank_id", .help = "Erase entire flash device.", }, { .name = "options_read", - .handler = &stm32x_handle_options_read_command, + .handler = stm32x_handle_options_read_command, .mode = COMMAND_EXEC, .usage = "bank_id", .help = "Read and display device option byte.", }, { .name = "options_write", - .handler = &stm32x_handle_options_write_command, + .handler = stm32x_handle_options_write_command, .mode = COMMAND_EXEC, .usage = "bank_id ('SWWDG'|'HWWDG') " "('RSTSTNDBY'|'NORSTSTNDBY') " @@ -1230,6 +1408,7 @@ static const struct command_registration stm32x_exec_command_handlers[] = { }, COMMAND_REGISTRATION_DONE }; + static const struct command_registration stm32x_command_handlers[] = { { .name = "stm32x", @@ -1241,15 +1420,16 @@ static const struct command_registration stm32x_command_handlers[] = { }; struct flash_driver stm32x_flash = { - .name = "stm32x", - .commands = stm32x_command_handlers, - .flash_bank_command = &stm32x_flash_bank_command, - .erase = &stm32x_erase, - .protect = &stm32x_protect, - .write = &stm32x_write, - .probe = &stm32x_probe, - .auto_probe = &stm32x_auto_probe, - .erase_check = &default_flash_mem_blank_check, - .protect_check = &stm32x_protect_check, - .info = &stm32x_info, - }; + .name = "stm32x", + .commands = stm32x_command_handlers, + .flash_bank_command = stm32x_flash_bank_command, + .erase = stm32x_erase, + .protect = stm32x_protect, + .write = stm32x_write, + .read = default_flash_read, + .probe = stm32x_probe, + .auto_probe = stm32x_auto_probe, + .erase_check = default_flash_mem_blank_check, + .protect_check = stm32x_protect_check, + .info = get_stm32x_info, +};