X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fs3c2440_nand.c;h=44ac3c2abe2a11b94a9cb57d0d258cf35933fdc2;hp=fd1971950137a75416bca72f009a15654d82832d;hb=0f1163e823c6ca3c2a81fa296157f5dde0635fea;hpb=ee340df8417772b8c29a54ddf7b36556ec20d609 diff --git a/src/flash/s3c2440_nand.c b/src/flash/s3c2440_nand.c index fd19719501..44ac3c2abe 100644 --- a/src/flash/s3c2440_nand.c +++ b/src/flash/s3c2440_nand.c @@ -1,14 +1,26 @@ -/* src/flash/s3c2440_nand.c - * +/*************************************************************************** + * Copyright (C) 2007, 2008 by Ben Dooks * + * ben@fluff.org * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ + +/* * S3C2440 OpenOCD NAND Flash controller support. * - * Copyright 2007,2008 Ben Dooks - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * * Many thanks to Simtec Electronics for sponsoring this work. */ @@ -16,64 +28,27 @@ #include "config.h" #endif -#include "replacements.h" -#include "log.h" - -#include -#include - -#include "nand.h" #include "s3c24xx_nand.h" -#include "target.h" -int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device); -int s3c2440_init(struct nand_device_s *device); -int s3c2440_nand_ready(struct nand_device_s *device, int timeout); -nand_flash_controller_t s3c2440_nand_controller = -{ - .name = "s3c2440", - .nand_device_command = s3c2440_nand_device_command, - .register_commands = s3c24xx_register_commands, - .init = s3c2440_init, - .reset = s3c24xx_reset, - .command = s3c24xx_command, - .address = s3c24xx_address, - .write_data = s3c24xx_write_data, - .read_data = s3c24xx_read_data, - .write_page = s3c24xx_write_page, - .read_page = s3c24xx_read_page, - .write_block_data = s3c2440_write_block_data, - .read_block_data = s3c2440_read_block_data, - .controller_ready = s3c24xx_controller_ready, - .nand_ready = s3c2440_nand_ready, -}; - -int s3c2440_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, - char **args, int argc, - struct nand_device_s *device) +NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command) { - s3c24xx_nand_controller_t *info; - - info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device); - if (info == NULL) { - return ERROR_NAND_DEVICE_INVALID; - } + struct s3c24xx_nand_controller *info; + CALL_S3C24XX_DEVICE_COMMAND(nand, &info); /* fill in the address fields for the core device */ info->cmd = S3C2440_NFCMD; info->addr = S3C2440_NFADDR; info->data = S3C2440_NFDATA; info->nfstat = S3C2440_NFSTAT; - + return ERROR_OK; } -int s3c2440_init(struct nand_device_s *device) +static int s3c2440_init(struct nand_device_s *nand) { - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u32 version; + struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv; + struct target *target = s3c24xx_info->target; target_write_u32(target, S3C2410_NFCONF, S3C2440_NFCONF_TACLS(3) | @@ -86,24 +61,24 @@ int s3c2440_init(struct nand_device_s *device) return ERROR_OK; } -int s3c2440_nand_ready(struct nand_device_s *device, int timeout) +int s3c2440_nand_ready(struct nand_device_s *nand, int timeout) { - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u8 status; + struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv; + struct target *target = s3c24xx_info->target; + uint8_t status; if (target->state != TARGET_HALTED) { - ERROR("target must be halted to use S3C24XX NAND flash controller"); + LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - - do { + + do { target_read_u8(target, s3c24xx_info->nfstat, &status); - + if (status & S3C2440_NFSTAT_READY) return 1; - usleep(1000); + alive_sleep(1); } while (timeout-- > 0); @@ -112,21 +87,21 @@ int s3c2440_nand_ready(struct nand_device_s *device, int timeout) /* use the fact we can read/write 4 bytes in one go via a single 32bit op */ -int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_size) +int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size) { - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u32 nfdata = s3c24xx_info->data; - u32 tmp; + struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv; + struct target *target = s3c24xx_info->target; + uint32_t nfdata = s3c24xx_info->data; + uint32_t tmp; - printf("%s: reading data: %p, %p, %d\n", __func__, device, data, data_size); + LOG_INFO("%s: reading data: %p, %p, %d\n", __func__, nand, data, data_size); if (target->state != TARGET_HALTED) { - ERROR("target must be halted to use S3C24XX NAND flash controller"); + LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - while (data_size >= 4) { + while (data_size >= 4) { target_read_u32(target, nfdata, &tmp); data[0] = tmp; @@ -148,19 +123,19 @@ int s3c2440_read_block_data(struct nand_device_s *device, u8 *data, int data_siz return ERROR_OK; } -int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_size) +int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size) { - s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv; - target_t *target = s3c24xx_info->target; - u32 nfdata = s3c24xx_info->data; - u32 tmp; + struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv; + struct target *target = s3c24xx_info->target; + uint32_t nfdata = s3c24xx_info->data; + uint32_t tmp; if (target->state != TARGET_HALTED) { - ERROR("target must be halted to use S3C24XX NAND flash controller"); + LOG_ERROR("target must be halted to use S3C24XX NAND flash controller"); return ERROR_NAND_OPERATION_FAILED; } - while (data_size >= 4) { + while (data_size >= 4) { tmp = le_to_h_u32(data); target_write_u32(target, nfdata, tmp); @@ -177,3 +152,21 @@ int s3c2440_write_block_data(struct nand_device_s *device, u8 *data, int data_si return ERROR_OK; } + +struct nand_flash_controller s3c2440_nand_controller = { + .name = "s3c2440", + .nand_device_command = &s3c2440_nand_device_command, + .register_commands = &s3c24xx_register_commands, + .init = &s3c2440_init, + .reset = &s3c24xx_reset, + .command = &s3c24xx_command, + .address = &s3c24xx_address, + .write_data = &s3c24xx_write_data, + .read_data = &s3c24xx_read_data, + .write_page = s3c24xx_write_page, + .read_page = s3c24xx_read_page, + .write_block_data = &s3c2440_write_block_data, + .read_block_data = &s3c2440_read_block_data, + .controller_ready = &s3c24xx_controller_ready, + .nand_ready = &s3c2440_nand_ready, + };