X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fstm32x.c;h=5b16f57aefc4cffe3266010b7a8586e903948edb;hp=a09fa40d79f0acad7c0b943957d3d67c9fdbaad6;hb=53bbd36c7d5adfe86aef071e2effbbfa804d0054;hpb=eba4e394d834c5088f95412a6d3bdba622a691fc

diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c
index a09fa40d79..5b16f57aef 100644
--- a/src/flash/stm32x.c
+++ b/src/flash/stm32x.c
@@ -40,6 +40,7 @@ int stm32x_erase(struct flash_bank_s *bank, int first, int last);
 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
 int stm32x_probe(struct flash_bank_s *bank);
+int stm32x_auto_probe(struct flash_bank_s *bank);
 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int stm32x_protect_check(struct flash_bank_s *bank);
 int stm32x_erase_check(struct flash_bank_s *bank);
@@ -60,6 +61,7 @@ flash_driver_t stm32x_flash =
 	.protect = stm32x_protect,
 	.write = stm32x_write,
 	.probe = stm32x_probe,
+	.auto_probe = stm32x_auto_probe,
 	.erase_check = stm32x_erase_check,
 	.protect_check = stm32x_protect_check,
 	.info = stm32x_info
@@ -82,41 +84,6 @@ int stm32x_register_commands(struct command_context_s *cmd_ctx)
 	return ERROR_OK;
 }
 
-int stm32x_build_block_list(struct flash_bank_s *bank)
-{
-	int i;
-	int num_sectors = 0;
-		
-	switch (bank->size)
-	{
-		case 32 * 1024:
-			num_sectors = 32;
-			break;
-		case 64 * 1024:
-			num_sectors = 64;
-			break;
-		case 128 * 1024:
-			num_sectors = 128;
-			break;
-		default:
-			ERROR("BUG: unknown bank->size encountered");
-			exit(-1);
-	}
-	
-	bank->num_sectors = num_sectors;
-	bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
-	
-	for (i = 0; i < num_sectors; i++)
-	{
-		bank->sectors[i].offset = i * 1024;
-		bank->sectors[i].size = 1024;
-		bank->sectors[i].is_erased = -1;
-		bank->sectors[i].is_protected = 1;
-	}
-	
-	return ERROR_OK;
-}
-
 /* flash bank stm32x <base> <size> 0 0 <target#>
  */
 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
@@ -132,30 +99,15 @@ int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
 	stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
 	bank->driver_priv = stm32x_info;
 	
-	if (bank->base != 0x08000000)
-	{
-		WARNING("overriding flash base address for STM32x device with 0x08000000");
-		bank->base = 0x08000000;
-	}
-	
-	stm32x_info->target = get_target_by_num(strtoul(args[5], NULL, 0));
-	if (!stm32x_info->target)
-	{
-		ERROR("no target '%s' configured", args[5]);
-		exit(-1);
-	}
-
-	stm32x_build_block_list(bank);
-	
 	stm32x_info->write_algorithm = NULL;
+	stm32x_info->probed = 0;
 	
 	return ERROR_OK;
 }
 
 u32 stm32x_get_flash_status(flash_bank_t *bank)
 {
-	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	target_t *target = bank->target;
 	u32 status;
 	
 	target_read_u32(target, STM32_FLASH_SR, &status);
@@ -177,10 +129,158 @@ u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 	return status;
 }
 
+int stm32x_read_options(struct flash_bank_s *bank)
+{
+	u32 optiondata;
+	stm32x_flash_bank_t *stm32x_info = NULL;
+	target_t *target = bank->target;
+	
+	stm32x_info = bank->driver_priv;
+	
+	/* read current option bytes */
+	target_read_u32(target, STM32_FLASH_OBR, &optiondata);
+	
+	stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
+	stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
+	
+	if (optiondata & (1 << OPT_READOUT))
+		INFO("Device Security Bit Set");
+	
+	/* each bit refers to a 4bank protection */
+	target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
+	
+	stm32x_info->option_bytes.protection[0] = (u16)optiondata;
+	stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
+	stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
+	stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
+		
+	return ERROR_OK;
+}
+
+int stm32x_erase_options(struct flash_bank_s *bank)
+{
+	stm32x_flash_bank_t *stm32x_info = NULL;
+	target_t *target = bank->target;
+	u32 status;
+	
+	stm32x_info = bank->driver_priv;
+	
+	/* read current options */
+	stm32x_read_options(bank);
+	
+	/* unlock flash registers */
+	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+	
+	/* unlock option flash registers */
+	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
+	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
+	
+	/* erase option bytes */
+	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
+	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	/* clear readout protection and complementary option bytes
+	 * this will also force a device unlock if set */
+	stm32x_info->option_bytes.RDP = 0x5AA5;
+	
+	return ERROR_OK;
+}
+
+int stm32x_write_options(struct flash_bank_s *bank)
+{
+	stm32x_flash_bank_t *stm32x_info = NULL;
+	target_t *target = bank->target;
+	u32 status;
+	
+	stm32x_info = bank->driver_priv;
+	
+	/* unlock flash registers */
+	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+	
+	/* unlock option flash registers */
+	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
+	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
+	
+	/* program option bytes */
+	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
+		
+	/* write user option byte */
+	target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	/* write protection byte 1 */
+	target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	/* write protection byte 2 */
+	target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	/* write protection byte 3 */
+	target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	/* write protection byte 4 */
+	target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	/* write readout protection bit */
+	target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
+	
+	status = stm32x_wait_status_busy(bank, 10);
+	
+	if( status & FLASH_WRPRTERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	if( status & FLASH_PGERR )
+		return ERROR_FLASH_OPERATION_FAILED;
+	
+	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+	
+	return ERROR_OK;
+}
+
 int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
 {
-	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	target_t *target = bank->target;
 	u8 *buffer;
 	int i;
 	int nBytes;
@@ -218,11 +318,11 @@ int stm32x_blank_check(struct flash_bank_s *bank, int first, int last)
 
 int stm32x_protect_check(struct flash_bank_s *bank)
 {
-	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	target_t *target = bank->target;
 	
 	u32 protection;
 	int i, s;
+	int num_bits;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -232,7 +332,10 @@ int stm32x_protect_check(struct flash_bank_s *bank)
 	/* each bit refers to a 4bank protection */
 	target_read_u32(target, STM32_FLASH_WRPR, &protection);
 	
-	for (i = 0; i < 32; i++)
+	/* each protection bit is for 4 1K pages */
+	num_bits = (bank->num_sectors / 4);
+	
+	for (i = 0; i < num_bits; i++)
 	{
 		int set = 1;
 		
@@ -248,21 +351,20 @@ int stm32x_protect_check(struct flash_bank_s *bank)
 
 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 {
-	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	target_t *target = bank->target;
 	
 	int i;
 	u32 status;
 	
-	/* unlock flash registers */
-	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
-	
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	
+	/* unlock flash registers */
+	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
+	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
+	
 	for (i = first; i <= last; i++)
 	{	
 		target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
@@ -285,25 +387,64 @@ int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 
 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 {
-	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	stm32x_flash_bank_t *stm32x_info = NULL;
+	target_t *target = bank->target;
+	u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
+	int i, reg, bit;
+	int status;
+	u32 protection;
+	
+	stm32x_info = bank->driver_priv;
 	
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
-
-	return ERROR_OK;
+	
+	if ((first && (first % 4)) || ((last + 1) && (last + 1) % 4))
+	{
+		WARNING("sector start/end incorrect - stm32 has 4K sector protection");
+		return ERROR_FLASH_SECTOR_INVALID;
+	}
+	
+	/* each bit refers to a 4bank protection */
+	target_read_u32(target, STM32_FLASH_WRPR, &protection);
+	
+	prot_reg[0] = (u16)protection;
+	prot_reg[1] = (u16)(protection >> 8);
+	prot_reg[2] = (u16)(protection >> 16);
+	prot_reg[3] = (u16)(protection >> 24);
+	
+	for (i = first; i <= last; i++)
+	{
+		reg = (i / 4) / 8;
+		bit = (i / 4) - (reg * 8);
+		
+		if( set )
+			prot_reg[reg] &= ~(1 << bit);
+		else
+			prot_reg[reg] |= (1 << bit);
+	}
+	
+	if ((status = stm32x_erase_options(bank)) != ERROR_OK)
+		return status;
+	
+	stm32x_info->option_bytes.protection[0] = prot_reg[0];
+	stm32x_info->option_bytes.protection[1] = prot_reg[1];
+	stm32x_info->option_bytes.protection[2] = prot_reg[2];
+	stm32x_info->option_bytes.protection[3] = prot_reg[3];
+	
+	return stm32x_write_options(bank);
 }
 
 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 {
 	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	target_t *target = bank->target;
 	u32 buffer_size = 8192;
 	working_area_t *source;
 	u32 address = bank->base + offset;
-	reg_param_t reg_params[6];
+	reg_param_t reg_params[4];
 	armv7m_algorithm_t armv7m_info;
 	int retval = ERROR_OK;
 	
@@ -330,16 +471,13 @@ int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
 	};
 	
 	/* flash write code */
-	if (!stm32x_info->write_algorithm)
+	if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 	{
-		if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
-		{
-			WARNING("no working area available, can't do block memory writes");
-			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-		};
-		
-		target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
-	}
+		WARNING("no working area available, can't do block memory writes");
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	};
+	
+	target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
 
 	/* memory buffer */
 	while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
@@ -364,8 +502,6 @@ int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 	init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
-	init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
-	init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
 	
 	while (count > 0)
 	{
@@ -377,7 +513,7 @@ int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
 		buf_set_u32(reg_params[1].value, 0, 32, address);
 		buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 		
-		if ((retval = target->type->run_algorithm(target, 0, NULL, 6, reg_params, stm32x_info->write_algorithm->address, \
+		if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 				stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 		{
 			ERROR("error executing str7x flash write algorithm");
@@ -396,21 +532,19 @@ int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 co
 	}
 	
 	target_free_working_area(target, source);
+	target_free_working_area(target, stm32x_info->write_algorithm);
 	
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
 	destroy_reg_param(&reg_params[2]);
 	destroy_reg_param(&reg_params[3]);
-	destroy_reg_param(&reg_params[4]);
-	destroy_reg_param(&reg_params[5]);
 	
 	return retval;
 }
 
 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 {
-	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
-	target_t *target = stm32x_info->target;
+	target_t *target = bank->target;
 	u32 words_remaining = (count / 2);
 	u32 bytes_remaining = (count & 0x00000001);
 	u32 address = bank->base + offset;
@@ -506,9 +640,43 @@ int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 
 int stm32x_probe(struct flash_bank_s *bank)
 {
+	target_t *target = bank->target;
+	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
+	int i;
+	u16 num_sectors;
+	
+	stm32x_info->probed = 0;
+	
+	/* get flash size from target */
+	target_read_u16(target, 0x1FFFF7E0, &num_sectors);
+	INFO( "flash size = %dkbytes", num_sectors );
+	
+	bank->base = 0x08000000;
+	bank->size = num_sectors * 1024;
+	bank->num_sectors = num_sectors;
+	bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
+	
+	for (i = 0; i < num_sectors; i++)
+	{
+		bank->sectors[i].offset = i * 1024;
+		bank->sectors[i].size = 1024;
+		bank->sectors[i].is_erased = -1;
+		bank->sectors[i].is_protected = 1;
+	}
+	
+	stm32x_info->probed = 1;
+	
 	return ERROR_OK;
 }
 
+int stm32x_auto_probe(struct flash_bank_s *bank)
+{
+	stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
+	if (stm32x_info->probed)
+		return ERROR_OK;
+	return stm32x_probe(bank);
+}
+
 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	return ERROR_OK;
@@ -528,7 +696,6 @@ int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	flash_bank_t *bank;
-	u32 status;
 	target_t *target = NULL;
 	stm32x_flash_bank_t *stm32x_info = NULL;
 	
@@ -547,46 +714,28 @@ int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, cha
 	
 	stm32x_info = bank->driver_priv;
 	
-	target = stm32x_info->target;
+	target = bank->target;
 	
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	
-	/* unlock flash registers */
-	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
-	
-	/* unlock option flash registers */
-	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
-	
-	/* erase option bytes */
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
-	
-	status = stm32x_wait_status_busy(bank, 10);
-	
-	if( status & FLASH_WRPRTERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	if( status & FLASH_PGERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	
-	/* program option bytes */
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
-	
-	/* set readout protection */
-	target_write_u16(target, STM32_OB_ADR, 0);
-	
-	status = stm32x_wait_status_busy(bank, 10);
+	if (stm32x_erase_options(bank) != ERROR_OK)
+	{
+		command_print(cmd_ctx, "stm32x failed to erase options");
+		return ERROR_OK;
+	}
+		
+	/* set readout protection */	
+	stm32x_info->option_bytes.RDP = 0;
 	
-	if( status & FLASH_WRPRTERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	if( status & FLASH_PGERR )
-		return ERROR_FLASH_OPERATION_FAILED;
+	if (stm32x_write_options(bank) != ERROR_OK)
+	{
+		command_print(cmd_ctx, "stm32x failed to lock device");
+		return ERROR_OK;
+	}
 	
-	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 	command_print(cmd_ctx, "stm32x locked");
 	
 	return ERROR_OK;
@@ -595,7 +744,6 @@ int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, cha
 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	flash_bank_t *bank;
-	u32 status;
 	target_t *target = NULL;
 	stm32x_flash_bank_t *stm32x_info = NULL;
 	
@@ -614,46 +762,25 @@ int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, c
 	
 	stm32x_info = bank->driver_priv;
 	
-	target = stm32x_info->target;
+	target = bank->target;
 	
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
+		
+	if (stm32x_erase_options(bank) != ERROR_OK)
+	{
+		command_print(cmd_ctx, "stm32x failed to unlock device");
+		return ERROR_OK;
+	}
 	
-	/* unlock flash registers */
-	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
-	
-	/* unlock option flash registers */
-	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
-	
-	/* erase option bytes */
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
-	
-	status = stm32x_wait_status_busy(bank, 10);
-	
-	if( status & FLASH_WRPRTERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	if( status & FLASH_PGERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	
-	/* program option bytes */
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
-	
-	/* clear readout protection and complementary option bytes */
-	target_write_u16(target, STM32_OB_ADR, 0x5AA5);
-	
-	status = stm32x_wait_status_busy(bank, 10);
-	
-	if( status & FLASH_WRPRTERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	if( status & FLASH_PGERR )
-		return ERROR_FLASH_OPERATION_FAILED;
+	if (stm32x_write_options(bank) != ERROR_OK)
+	{
+		command_print(cmd_ctx, "stm32x failed to lock device");
+		return ERROR_OK;
+	}
 	
-	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 	command_print(cmd_ctx, "stm32x unlocked");
 	
 	return ERROR_OK;
@@ -681,22 +808,13 @@ int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *
 	
 	stm32x_info = bank->driver_priv;
 	
-	target = stm32x_info->target;
+	target = bank->target;
 	
 	if (target->state != TARGET_HALTED)
 	{
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	
-	//target_read_u32(target, STM32_OB_ADR, &optionbyte);
-	//command_print(cmd_ctx, "Option Byte 0: 0x%x", optionbyte);
-	//target_read_u32(target, STM32_OB_ADR+4, &optionbyte);
-	//command_print(cmd_ctx, "Option Byte 1: 0x%x", optionbyte);
-	//target_read_u32(target, STM32_OB_ADR+8, &optionbyte);
-	//command_print(cmd_ctx, "Option Byte 2: 0x%x", optionbyte);
-	//target_read_u32(target, STM32_OB_ADR+12, &optionbyte);
-	//command_print(cmd_ctx, "Option Byte 3: 0x%x", optionbyte);
-	
 	target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
 	command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
 	
@@ -732,7 +850,6 @@ int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char
 	target_t *target = NULL;
 	stm32x_flash_bank_t *stm32x_info = NULL;
 	u16 optionbyte = 0xF8;
-	u32 status;
 	
 	if (argc < 4)
 	{
@@ -749,7 +866,7 @@ int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char
 	
 	stm32x_info = bank->driver_priv;
 	
-	target = stm32x_info->target;
+	target = bank->target;
 	
 	if (target->state != TARGET_HALTED)
 	{
@@ -783,38 +900,31 @@ int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char
 		optionbyte &= ~(1<<2);
 	}
 	
-	/* unlock flash registers */
-	target_write_u32(target, STM32_FLASH_KEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_KEYR, KEY2);
-	
-	/* unlock option flash registers */
-	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
-	target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
-	
-	/* program option bytes */
-	target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
-	
-	/* write option byte */
-	target_write_u16(target, STM32_OB_ADR + 2, optionbyte);
+	if (stm32x_erase_options(bank) != ERROR_OK)
+	{
+		command_print(cmd_ctx, "stm32x failed to erase options");
+		return ERROR_OK;
+	}
 	
-	status = stm32x_wait_status_busy(bank, 10);
+	stm32x_info->option_bytes.user_options = optionbyte;
 	
-	if( status & FLASH_WRPRTERR )
-		return ERROR_FLASH_OPERATION_FAILED;
-	if( status & FLASH_PGERR )
-		return ERROR_FLASH_OPERATION_FAILED;
+	if (stm32x_write_options(bank) != ERROR_OK)
+	{
+		command_print(cmd_ctx, "stm32x failed to write options");
+		return ERROR_OK;
+	}
 	
-	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+	command_print(cmd_ctx, "stm32x write options complete");
 	
 	return ERROR_OK;
 }
 
 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
-	flash_bank_t *bank;
-	u32 status;
 	target_t *target = NULL;
 	stm32x_flash_bank_t *stm32x_info = NULL;
+	flash_bank_t *bank;
+	u32 status;
 	
 	if (argc < 1)
 	{
@@ -831,7 +941,7 @@ int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cm
 	
 	stm32x_info = bank->driver_priv;
 	
-	target = stm32x_info->target;
+	target = bank->target;
 	
 	if (target->state != TARGET_HALTED)
 	{
@@ -848,12 +958,21 @@ int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cm
 	
 	status = stm32x_wait_status_busy(bank, 10);
 	
+	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+	
 	if( status & FLASH_WRPRTERR )
-		return ERROR_FLASH_OPERATION_FAILED;
+	{
+		command_print(cmd_ctx, "stm32x device protected");
+		return ERROR_OK;
+	}
+	
 	if( status & FLASH_PGERR )
-		return ERROR_FLASH_OPERATION_FAILED;
+	{
+		command_print(cmd_ctx, "stm32x device programming failed");
+		return ERROR_OK;
+	}
 	
-	target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
+	command_print(cmd_ctx, "stm32x mass erase complete");
 	
 	return ERROR_OK;
 }