X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Frtos%2Frtos_standard_stackings.c;fp=src%2Frtos%2Frtos_standard_stackings.c;h=fe890413fa1f5eec48cb52f2cb6de8cae62e12d5;hp=c3eef5c068e11ed19fdfc08316655c78f027bfb3;hb=5148a1324aeef62d85aaeaa1c061df8e874e4c12;hpb=da434d7d5975c1c7ebae8e35eb71b6d2d6ad062e

diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
index c3eef5c068..fe890413fa 100644
--- a/src/rtos/rtos_standard_stackings.c
+++ b/src/rtos/rtos_standard_stackings.c
@@ -249,41 +249,41 @@ static target_addr_t rtos_standard_cortex_m4f_fpu_stack_align(struct target *tar
 
 
 const struct rtos_register_stacking rtos_standard_cortex_m3_stacking = {
-	0x40,					/* stack_registers_size */
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_standard_cortex_m3_stack_align,	/* stack_alignment */
-	rtos_standard_cortex_m3_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x40,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_standard_cortex_m3_stack_align,
+	.register_offsets = rtos_standard_cortex_m3_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking = {
-	0x44,					/* stack_registers_size 4 more for LR*/
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_standard_cortex_m4f_stack_align,	/* stack_alignment */
-	rtos_standard_cortex_m4f_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x44,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_standard_cortex_m4f_stack_align,
+	.register_offsets = rtos_standard_cortex_m4f_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking = {
-	0xcc,					/* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
-	-1,						/* stack_growth_direction */
-	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
-	rtos_standard_cortex_m4f_fpu_stack_align,	/* stack_alignment */
-	rtos_standard_cortex_m4f_fpu_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0xcc,
+	.stack_growth_direction = -1,
+	.num_output_registers = ARMV7M_NUM_CORE_REGS,
+	.calculate_process_stack = rtos_standard_cortex_m4f_fpu_stack_align,
+	.register_offsets = rtos_standard_cortex_m4f_fpu_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
-	0x48,				/* stack_registers_size */
-	-1,					/* stack_growth_direction */
-	26,					/* num_output_registers */
-	rtos_generic_stack_align8,	/* stack_alignment */
-	rtos_standard_cortex_r4_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x48,
+	.stack_growth_direction = -1,
+	.num_output_registers = 26,
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_standard_cortex_r4_stack_offsets
 };
 
 const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
-	0x90,				/* stack_registers_size */
-	-1,					/* stack_growth_direction */
-	32,					/* num_output_registers */
-	rtos_generic_stack_align8,	/* stack_alignment */
-	rtos_standard_nds32_n1068_stack_offsets	/* register_offsets */
+	.stack_registers_size = 0x90,
+	.stack_growth_direction = -1,
+	.num_output_registers = 32,
+	.calculate_process_stack = rtos_generic_stack_align8,
+	.register_offsets = rtos_standard_nds32_n1068_stack_offsets
 };