X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Faarch64.c;h=41bea2e93dca22531055a6d25004f86039e966cd;hp=3510db23503a31c52f6414e962db69063b625957;hb=a76e88daa645d7137c8415f48793525f2ba98545;hpb=675b0170f2752c285de359f235e50a208f7f138a

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3510db2350..41bea2e93d 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -698,6 +698,8 @@ static int aarch64_post_debug_entry(struct target *target)
 
 	switch (armv8->arm.core_mode) {
 		case ARMV8_64_EL0T:
+			dpmv8_modeswitch(&armv8->dpm, ARMV8_64_EL1T);
+			/* fall through */
 		case ARMV8_64_EL1T:
 		case ARMV8_64_EL1H:
 			retval = armv8->arm.mrs(target, 3, /*op 0*/
@@ -725,13 +727,20 @@ static int aarch64_post_debug_entry(struct target *target)
 			if (retval != ERROR_OK)
 				return retval;
 		break;
-		default:
+
+		case ARM_MODE_SVC:
 			retval = armv8->arm.mrc(target, 15, 0, 0, 1, 0, &aarch64->system_control_reg);
 			if (retval != ERROR_OK)
 				return retval;
 			break;
+
+		default:
+			LOG_INFO("cannot read system control register in this mode");
+			break;
 	}
 
+	dpmv8_modeswitch(&armv8->dpm, ARM_MODE_ANY);
+
 	LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
 	aarch64->system_control_reg_curr = aarch64->system_control_reg;