X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm.h;h=316ff9ab848e433ecb67da02b64ae47cb8d5c749;hp=00dbe2d6f4cd9abb305c8e764074cf402bd08041;hb=010b09121ca08f955921654c6a3d405be80afef1;hpb=0a1b7dcfc40385f09b5eb088cd97d6ff25a5816d diff --git a/src/target/arm.h b/src/target/arm.h index 00dbe2d6f4..316ff9ab84 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -8,6 +8,9 @@ * Copyright (C) 2009 by Øyvind Harboe * oyvind.harboe@zylin.com * + * Copyright (C) 2018 by Liviu Ionescu + * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -19,16 +22,14 @@ * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the - * Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * along with this program. If not, see . */ -#ifndef ARM_H -#define ARM_H -#include -#include +#ifndef OPENOCD_TARGET_ARM_H +#define OPENOCD_TARGET_ARM_H +#include +#include "target.h" /** * @file @@ -40,22 +41,81 @@ */ /** - * These numbers match the five low bits of the *PSR registers on + * Represent state of an ARM core. + * + * Most numbers match the five low bits of the *PSR registers on * "classic ARM" processors, which build on the ARMv4 processor * modes and register set. + * + * ARM_MODE_ANY is a magic value, often used as a wildcard. + * + * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD, + * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes + * they support. */ enum arm_mode { ARM_MODE_USR = 16, ARM_MODE_FIQ = 17, ARM_MODE_IRQ = 18, ARM_MODE_SVC = 19, + ARM_MODE_MON = 22, ARM_MODE_ABT = 23, - ARM_MODE_MON = 26, ARM_MODE_UND = 27, + ARM_MODE_1176_MON = 28, ARM_MODE_SYS = 31, + + ARM_MODE_THREAD = 0, + ARM_MODE_USER_THREAD = 1, + ARM_MODE_HANDLER = 2, + + ARMV8_64_EL0T = 0x0, + ARMV8_64_EL1T = 0x4, + ARMV8_64_EL1H = 0x5, + ARMV8_64_EL2T = 0x8, + ARMV8_64_EL2H = 0x9, + ARMV8_64_EL3T = 0xC, + ARMV8_64_EL3H = 0xD, + ARM_MODE_ANY = -1 }; +/* VFPv3 internal register numbers mapping to d0:31 */ +enum { + ARM_VFP_V3_D0 = 51, + ARM_VFP_V3_D1, + ARM_VFP_V3_D2, + ARM_VFP_V3_D3, + ARM_VFP_V3_D4, + ARM_VFP_V3_D5, + ARM_VFP_V3_D6, + ARM_VFP_V3_D7, + ARM_VFP_V3_D8, + ARM_VFP_V3_D9, + ARM_VFP_V3_D10, + ARM_VFP_V3_D11, + ARM_VFP_V3_D12, + ARM_VFP_V3_D13, + ARM_VFP_V3_D14, + ARM_VFP_V3_D15, + ARM_VFP_V3_D16, + ARM_VFP_V3_D17, + ARM_VFP_V3_D18, + ARM_VFP_V3_D19, + ARM_VFP_V3_D20, + ARM_VFP_V3_D21, + ARM_VFP_V3_D22, + ARM_VFP_V3_D23, + ARM_VFP_V3_D24, + ARM_VFP_V3_D25, + ARM_VFP_V3_D26, + ARM_VFP_V3_D27, + ARM_VFP_V3_D28, + ARM_VFP_V3_D29, + ARM_VFP_V3_D30, + ARM_VFP_V3_D31, + ARM_VFP_V3_FPSCR, +}; + const char *arm_mode_name(unsigned psr_mode); bool is_arm_mode(unsigned psr_mode); @@ -65,9 +125,16 @@ enum arm_state { ARM_STATE_THUMB, ARM_STATE_JAZELLE, ARM_STATE_THUMB_EE, + ARM_STATE_AARCH64, }; -extern const char *arm_state_strings[]; +/** ARM vector floating point enabled, if yes which version. */ +enum arm_vfp_version { + ARM_VFP_DISABLED, + ARM_VFP_V1, + ARM_VFP_V2, + ARM_VFP_V3, +}; #define ARM_COMMON_MAGIC 0x0A450A45 @@ -82,7 +149,10 @@ struct arm { int common_magic; struct reg_cache *core_cache; - /** Handle to the CPSR; valid in all core modes. */ + /** Handle to the PC; valid in all core modes. */ + struct reg *pc; + + /** Handle to the CPSR/xPSR; valid in all core modes. */ struct reg *cpsr; /** Handle to the SPSR; valid only in core modes with an SPSR. */ @@ -96,6 +166,8 @@ struct arm { * ARM_MODE_ANY indicates the standard set of 37 registers, * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three * more registers are shadowed, for "Secure Monitor" mode. + * ARM_MODE_THREAD indicates a microcontroller profile core, + * which only shadows SP. */ enum arm_mode core_type; @@ -108,11 +180,13 @@ struct arm { /** Flag reporting unavailability of the BKPT instruction. */ bool is_armv4; - /** Flag reporting whether semihosting is active. */ - bool is_semihosting; + /** Flag reporting armv6m based core. */ + bool is_armv6m; - /** Value to be returned by semihosting SYS_ERRNO request. */ - int semihosting_errno; + /** Floating point or VFP version, 0 if disabled. */ + int arm_vfp_version; + + int (*setup_semihosting)(struct target *target, int enable); /** Backpointer to the target. */ struct target *target; @@ -132,7 +206,7 @@ struct arm { int (*read_core_reg)(struct target *target, struct reg *reg, int num, enum arm_mode mode); int (*write_core_reg)(struct target *target, struct reg *reg, - int num, enum arm_mode mode, uint32_t value); + int num, enum arm_mode mode, uint8_t *value); /** Read coprocessor register. */ int (*mrc)(struct target *target, int cpnum, @@ -147,17 +221,25 @@ struct arm { uint32_t value); void *arch_info; + + /** For targets conforming to ARM Debug Interface v5, + * this handle references the Debug Access Port (DAP) + * used to make requests to the target. + */ + struct adiv5_dap *dap; }; /** Convert target handle to generic ARM target state handle. */ static inline struct arm *target_to_arm(struct target *target) { + assert(target != NULL); return target->arch_info; } static inline bool is_arm(struct arm *arm) { - return arm && arm->common_magic == ARM_COMMON_MAGIC; + assert(arm != NULL); + return arm->common_magic == ARM_COMMON_MAGIC; } struct arm_algorithm { @@ -171,17 +253,22 @@ struct arm_reg { int num; enum arm_mode mode; struct target *target; - struct arm *armv4_5_common; - uint32_t value; + struct arm *arm; + uint8_t value[16]; }; struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm); +struct reg_cache *armv8_build_reg_cache(struct target *target); extern const struct command_registration arm_command_handlers[]; int arm_arch_state(struct target *target); int arm_get_gdb_reg_list(struct target *target, - struct reg **reg_list[], int *reg_list_size); + struct reg **reg_list[], int *reg_list_size, + enum target_register_class reg_class); +int armv8_get_gdb_reg_list(struct target *target, + struct reg **reg_list[], int *reg_list_size, + enum target_register_class reg_class); int arm_init_arch_info(struct target *target, struct arm *arm); @@ -189,18 +276,26 @@ int arm_init_arch_info(struct target *target, struct arm *arm); int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, - uint32_t entry_point, uint32_t exit_point, + target_addr_t entry_point, target_addr_t exit_point, int timeout_ms, void *arch_info); +int armv4_5_run_algorithm_inner(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info, + int (*run_it)(struct target *target, uint32_t exit_point, + int timeout_ms, void *arch_info)); int arm_checksum_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *checksum); + target_addr_t address, uint32_t count, uint32_t *checksum); int arm_blank_check_memory(struct target *target, - uint32_t address, uint32_t count, uint32_t *blank); + struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value); void arm_set_cpsr(struct arm *arm, uint32_t cpsr); struct reg *arm_reg_current(struct arm *arm, unsigned regnum); +struct reg *armv8_reg_current(struct arm *arm, unsigned regnum); extern struct reg arm_gdb_dummy_fp_reg; extern struct reg arm_gdb_dummy_fps_reg; -#endif /* ARM_H */ +#endif /* OPENOCD_TARGET_ARM_H */