X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=0b2fa2cf5e8c4d295a4fc0883a7e7c4d9ae27d35;hp=dc465973bb9acd8539a27cf1bf54b105d45a09ef;hb=2280ddeea5fd82554696f1caa97f7a485a035da4;hpb=8f09c5df854426179a84d93de45129a224842de6 diff --git a/src/target/arm11.c b/src/target/arm11.c index dc465973bb..0b2fa2cf5e 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -27,6 +27,7 @@ #endif #include "arm11.h" +#include "arm11_dbgtap.h" #include "armv4_5.h" #include "arm_simulator.h" #include "time_support.h" @@ -49,60 +50,13 @@ #define FNC_INFO_NOTIMPLEMENTED #endif -static int arm11_on_enter_debug_state(arm11_common_t * arm11); - -bool arm11_config_memwrite_burst = true; -bool arm11_config_memwrite_error_fatal = true; -uint32_t arm11_vcr = 0; -bool arm11_config_memrw_no_increment = false; -bool arm11_config_step_irq_enable = false; -bool arm11_config_hardware_step = false; - -#define ARM11_HANDLER(x) \ - .x = arm11_##x - -target_type_t arm11_target = -{ - .name = "arm11", - - ARM11_HANDLER(poll), - ARM11_HANDLER(arch_state), - - ARM11_HANDLER(target_request_data), - - ARM11_HANDLER(halt), - ARM11_HANDLER(resume), - ARM11_HANDLER(step), - - ARM11_HANDLER(assert_reset), - ARM11_HANDLER(deassert_reset), - ARM11_HANDLER(soft_reset_halt), - - ARM11_HANDLER(get_gdb_reg_list), - - ARM11_HANDLER(read_memory), - ARM11_HANDLER(write_memory), - - ARM11_HANDLER(bulk_write_memory), - - ARM11_HANDLER(checksum_memory), - - ARM11_HANDLER(add_breakpoint), - ARM11_HANDLER(remove_breakpoint), - ARM11_HANDLER(add_watchpoint), - ARM11_HANDLER(remove_watchpoint), - - ARM11_HANDLER(run_algorithm), - - ARM11_HANDLER(register_commands), - ARM11_HANDLER(target_create), - ARM11_HANDLER(init_target), - ARM11_HANDLER(examine), - ARM11_HANDLER(quit), -}; - -int arm11_regs_arch_type = -1; +static bool arm11_config_memwrite_burst = true; +static bool arm11_config_memwrite_error_fatal = true; +static uint32_t arm11_vcr = 0; +static bool arm11_config_step_irq_enable = false; +static bool arm11_config_hardware_step = false; +static int arm11_regs_arch_type = -1; enum arm11_regtype { @@ -133,16 +87,16 @@ enum arm11_regtype }; -typedef struct arm11_reg_defs_s +struct arm11_reg_defs { char * name; uint32_t num; int gdb_num; enum arm11_regtype type; -} arm11_reg_defs_t; +}; /* update arm11_regcache_ids when changing this */ -static const arm11_reg_defs_t arm11_reg_defs[] = +static const struct arm11_reg_defs arm11_reg_defs[] = { {"r0", 0, 0, ARM11_REGISTER_CORE}, {"r1", 1, 1, ARM11_REGISTER_CORE}, @@ -292,21 +246,49 @@ enum arm11_regcache_ids #define ARM11_GDB_REGISTER_COUNT 26 -uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* FIXME these are *identical* to the ARMv4_5 dummies ... except + * for their names, and being static vs global, and having different + * addresses. Ditto ARMv7a and ARMv7m dummies. + */ -reg_t arm11_gdb_dummy_fp_reg = +static uint8_t arm11_gdb_dummy_fp_value[12]; + +static struct reg arm11_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point register", + .value = arm11_gdb_dummy_fp_value, + .dirty = 0, + .valid = 1, + .size = 96, + .arch_info = NULL, + .arch_type = 0, }; -uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; +static uint8_t arm11_gdb_dummy_fps_value[4]; -reg_t arm11_gdb_dummy_fps_reg = +static struct reg arm11_gdb_dummy_fps_reg = { - "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point status register", + .value = arm11_gdb_dummy_fps_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, + .arch_type = 0, }; +static int arm11_on_enter_debug_state(struct arm11_common *arm11); +static int arm11_step(struct target *target, int current, + uint32_t address, int handle_breakpoints); +/* helpers */ +static int arm11_build_reg_cache(struct target *target); +static int arm11_set_reg(struct reg *reg, uint8_t *buf); +static int arm11_get_reg(struct reg *reg); + +static void arm11_record_register_history(struct arm11_common * arm11); +static void arm11_dump_reg_changes(struct arm11_common * arm11); + /** Check and if necessary take control of the system * @@ -315,7 +297,7 @@ reg_t arm11_gdb_dummy_fps_reg = * available a pointer to a word holding the * DSCR can be passed. Otherwise use NULL. */ -int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) +static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr) { FNC_INFO; @@ -373,7 +355,7 @@ int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) * or on other occasions that stop the processor. * */ -static int arm11_on_enter_debug_state(arm11_common_t * arm11) +static int arm11_on_enter_debug_state(struct arm11_common *arm11) { int retval; FNC_INFO; @@ -395,7 +377,7 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); @@ -537,7 +519,7 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11) return ERROR_OK; } -void arm11_dump_reg_changes(arm11_common_t * arm11) +void arm11_dump_reg_changes(struct arm11_common * arm11) { if (!(debug_level >= LOG_LVL_DEBUG)) @@ -572,7 +554,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11) * This is called in preparation for the RESTART function. * */ -int arm11_leave_debug_state(arm11_common_t * arm11) +static int arm11_leave_debug_state(struct arm11_common *arm11) { FNC_INFO; int retval; @@ -609,7 +591,15 @@ int arm11_leave_debug_state(arm11_common_t * arm11) if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) { + /* + The wDTR/rDTR two registers that are used to send/receive data to/from + the core in tandem with corresponding instruction codes that are + written into the core. The RDTR FULL/WDTR FULL flag indicates that the + registers hold data that was written by one side (CPU or JTAG) and not + read out by the other side. + */ LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR); + return ERROR_FAIL; } } @@ -664,7 +654,7 @@ int arm11_leave_debug_state(arm11_common_t * arm11) arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; uint8_t Ready = 0; /* ignored */ uint8_t Valid = 0; /* ignored */ @@ -681,7 +671,7 @@ int arm11_leave_debug_state(arm11_common_t * arm11) return ERROR_OK; } -void arm11_record_register_history(arm11_common_t * arm11) +static void arm11_record_register_history(struct arm11_common *arm11) { for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) { @@ -695,16 +685,11 @@ void arm11_record_register_history(arm11_common_t * arm11) /* poll current target status */ -int arm11_poll(struct target_s *target) +static int arm11_poll(struct target *target) { FNC_INFO; int retval; - - arm11_common_t * arm11 = target->arch_info; - - if (arm11->trst_active) - return ERROR_OK; - + struct arm11_common *arm11 = target_to_arm11(target); uint32_t dscr; CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr)); @@ -743,9 +728,9 @@ int arm11_poll(struct target_s *target) return ERROR_OK; } /* architecture specific status reply */ -int arm11_arch_state(struct target_s *target) +static int arm11_arch_state(struct target *target) { - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, @@ -756,7 +741,8 @@ int arm11_arch_state(struct target_s *target) } /* target request support */ -int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer) +static int arm11_target_request_data(struct target *target, + uint32_t size, uint8_t *buffer) { FNC_INFO_NOTIMPLEMENTED; @@ -764,11 +750,10 @@ int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *b } /* target execution control */ -int arm11_halt(struct target_s *target) +static int arm11_halt(struct target *target) { FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -784,12 +769,6 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } - if (arm11->trst_active) - { - arm11->halt_requested = true; - return ERROR_OK; - } - arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE); CHECK_RETVAL(jtag_execute_queue()); @@ -835,14 +814,15 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } -int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static int arm11_resume(struct target *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) { FNC_INFO; // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", // current, address, handle_breakpoints, debug_execution); - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -867,7 +847,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han { /* check if one matches PC and step over it if necessary */ - breakpoint_t * bp; + struct breakpoint * bp; for (bp = target->breakpoints; bp; bp = bp->next) { @@ -885,7 +865,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han for (bp = target->breakpoints; bp; bp = bp->next) { - arm11_sc7_action_t brp[2]; + struct arm11_sc7_action brp[2]; brp[0].write = 1; brp[0].address = ARM11_SC7_BVR0 + brp_num; @@ -978,40 +958,43 @@ static int armv4_5_to_arm11(int reg) static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg) { - arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; reg=armv4_5_to_arm11(reg); return buf_get_u32(arm11->reg_list[reg].value, 0, 32); } -static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value) +static void arm11_sim_set_reg(struct arm_sim_interface *sim, + int reg, uint32_t value) { - arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; reg=armv4_5_to_arm11(reg); buf_set_u32(arm11->reg_list[reg].value, 0, 32, value); } -static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) +static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, + int pos, int bits) { - arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits); } static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim) { -// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; +// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; /* FIX!!!! we should implement thumb for arm11 */ return ARMV4_5_STATE_ARM; } -static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) +static void arm11_sim_set_state(struct arm_sim_interface *sim, + enum armv4_5_state mode) { -// arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; +// struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; /* FIX!!!! we should implement thumb for arm11 */ LOG_ERROR("Not implemetned!"); @@ -1020,13 +1003,13 @@ static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_stat static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim) { - //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; + //struct arm11_common * arm11 = (struct arm11_common *)sim->user_data; /* FIX!!!! we should implement something that returns the current mode here!!! */ return ARMV4_5_MODE_USR; } -static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc) +static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc) { struct arm_sim_interface sim; @@ -1044,7 +1027,8 @@ static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc) } -int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int arm11_step(struct target *target, int current, + uint32_t address, int handle_breakpoints) { FNC_INFO; @@ -1057,7 +1041,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl return ERROR_TARGET_NOT_HALTED; } - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); if (!current) R(PC) = address; @@ -1104,7 +1088,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl /* Set up breakpoint for stepping */ - arm11_sc7_action_t brp[2]; + struct arm11_sc7_action brp[2]; brp[0].write = 1; brp[0].address = ARM11_SC7_BVR0; @@ -1199,53 +1183,74 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl return ERROR_OK; } -/* target reset control */ -int arm11_assert_reset(struct target_s *target) +static int arm11_assert_reset(struct target *target) { FNC_INFO; + int retval; + struct arm11_common *arm11 = target_to_arm11(target); -#if 0 - /* assert reset lines */ - /* resets only the DBGTAP, not the ARM */ + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; - jtag_add_reset(1, 0); - jtag_add_sleep(5000); - - arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = true; -#endif + target->state = TARGET_UNKNOWN; + /* we would very much like to reset into the halted, state, + * but resetting and halting is second best... */ if (target->reset_halt) { CHECK_RETVAL(target_halt(target)); } - return ERROR_OK; -} -int arm11_deassert_reset(struct target_s *target) -{ - FNC_INFO; + /* srst is funny. We can not do *anything* else while it's asserted + * and it has unkonwn side effects. Make sure no other code runs + * meanwhile. + * + * Code below assumes srst: + * + * - Causes power-on-reset (but of what parts of the system?). Bug + * in arm11? + * + * - Messes us TAP state without asserting trst. + * + * - There is another bug in the arm11 core. When you generate an access to + * external logic (for example ddr controller via AHB bus) and that block + * is not configured (perhaps it is still held in reset), that transaction + * will never complete. This will hang arm11 core but it will also hang + * JTAG controller. Nothing, short of srst assertion will bring it out of + * this. + * + * Mysteries: + * + * - What should the PC be after an srst reset when starting in the halted + * state? + */ -#if 0 - LOG_DEBUG("target->state: %s", - target_state_name(target)); + jtag_add_reset(0, 1); + jtag_add_reset(0, 0); + /* How long do we have to wait? */ + jtag_add_sleep(5000); - /* deassert reset lines */ - jtag_add_reset(0, 0); + /* un-mess up TAP state */ + jtag_add_tlr(); - arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = false; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + { + return retval; + } - if (arm11->halt_requested) - return arm11_halt(target); -#endif + return ERROR_OK; +} +static int arm11_deassert_reset(struct target *target) +{ return ERROR_OK; } -int arm11_soft_reset_halt(struct target_s *target) +static int arm11_soft_reset_halt(struct target *target) { FNC_INFO_NOTIMPLEMENTED; @@ -1253,14 +1258,14 @@ int arm11_soft_reset_halt(struct target_s *target) } /* target register access for gdb */ -int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size) +static int arm11_get_gdb_reg_list(struct target *target, + struct reg **reg_list[], int *reg_list_size) { FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); *reg_list_size = ARM11_GDB_REGISTER_COUNT; - *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT); + *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT); for (size_t i = 16; i < 24; i++) { @@ -1283,8 +1288,14 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i /* target memory access * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit) * count: number of items of + * + * arm11_config_memrw_no_increment - in the future we may want to be able + * to read/write a range of data to a "port". a "port" is an action on + * read memory address for some peripheral. */ -int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm11_read_memory_inner(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, + bool arm11_config_memrw_no_increment) { /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ int retval; @@ -1299,7 +1310,7 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); retval = arm11_run_instr_data_prepare(arm11); if (retval != ERROR_OK) @@ -1370,7 +1381,19 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, return arm11_run_instr_data_finish(arm11); } -int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +{ + return arm11_read_memory_inner(target, address, size, count, buffer, false); +} + +/* +* arm11_config_memrw_no_increment - in the future we may want to be able +* to read/write a range of data to a "port". a "port" is an action on +* read memory address for some peripheral. +*/ +static int arm11_write_memory_inner(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, + bool arm11_config_memrw_no_increment) { int retval; FNC_INFO; @@ -1383,15 +1406,26 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count); - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); - arm11_run_instr_data_prepare(arm11); + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; /* MRC p14,0,r0,c0,c5,0 */ retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); if (retval != ERROR_OK) return retval; + /* burst writes are not used for single words as those may well be + * reset init script writes. + * + * The other advantage is that as burst writes are default, we'll + * now exercise both burst and non-burst code paths with the + * default settings, increasing code coverage. + */ + bool burst = arm11_config_memwrite_burst && (count > 1); + switch (size) { case 1: @@ -1447,7 +1481,7 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ uint32_t *words = (uint32_t*)buffer; - if (!arm11_config_memwrite_burst) + if (!burst) { /* STC p14,c5,[R0],#4 */ /* STC p14,c5,[R0]*/ @@ -1480,10 +1514,12 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, if (address + size * count != r0) { - LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x", - address + size * count, r0); + LOG_ERROR("Data transfer failed. Expected end " + "address 0x%08x, got 0x%08x", + (unsigned) (address + size * count), + (unsigned) r0); - if (arm11_config_memwrite_burst) + if (burst) LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); if (arm11_config_memwrite_error_fatal) @@ -1494,9 +1530,15 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, return arm11_run_instr_data_finish(arm11); } +static int arm11_write_memory(struct target *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +{ + return arm11_write_memory_inner(target, address, size, count, buffer, false); +} /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ -int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int arm11_bulk_write_memory(struct target *target, + uint32_t address, uint32_t count, uint8_t *buffer) { FNC_INFO; @@ -1513,7 +1555,8 @@ int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t * fallback code will read data from the target and calculate the CRC on the * host. */ -int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) +static int arm11_checksum_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t* checksum) { return ERROR_FAIL; } @@ -1521,11 +1564,11 @@ int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t co /* target break-/watchpoint control * rw: 0 = write, 1 = read, 2 = access */ -int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_add_breakpoint(struct target *target, + struct breakpoint *breakpoint) { FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); #if 0 if (breakpoint->type == BKPT_SOFT) @@ -1552,25 +1595,27 @@ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_remove_breakpoint(struct target *target, + struct breakpoint *breakpoint) { FNC_INFO; - - arm11_common_t * arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); arm11->free_brps++; return ERROR_OK; } -int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_add_watchpoint(struct target *target, + struct watchpoint *watchpoint) { FNC_INFO_NOTIMPLEMENTED; return ERROR_OK; } -int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_remove_watchpoint(struct target *target, + struct watchpoint *watchpoint) { FNC_INFO_NOTIMPLEMENTED; @@ -1579,11 +1624,13 @@ int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) // HACKHACKHACK - FIXME mode/state /* target algorithm support */ -int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, - int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info) +static int arm11_run_algorithm(struct target *target, + int num_mem_params, struct mem_param *mem_params, + int num_reg_params, struct reg_param *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { - arm11_common_t *arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); // enum armv4_5_state core_state = arm11->core_state; // enum armv4_5_mode core_mode = arm11->core_mode; uint32_t context[16]; @@ -1604,10 +1651,10 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t // return ERROR_FAIL; // Save regs - for (size_t i = 0; i < 16; i++) + for (unsigned i = 0; i < 16; i++) { context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32); - LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]); + LOG_DEBUG("Save %u: 0x%" PRIx32 "", i, context[i]); } cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32); @@ -1621,7 +1668,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t // Set register parameters for (int i = 0; i < num_reg_params; i++) { - reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -1706,7 +1753,7 @@ int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t { if (reg_params[i].direction != PARAM_OUT) { - reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -1743,11 +1790,11 @@ restore: return retval; } -int arm11_target_create(struct target_s *target, Jim_Interp *interp) +static int arm11_target_create(struct target *target, Jim_Interp *interp) { FNC_INFO; - NEW(arm11_common_t, arm11, 1); + NEW(struct arm11_common, arm11, 1); arm11->target = target; @@ -1760,29 +1807,37 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_COMMAND_SYNTAX_ERROR; } - target->arch_info = arm11; + armv4_5_init_arch_info(target, &arm11->arm); + + arm11->jtag_info.tap = target->tap; + arm11->jtag_info.scann_size = 5; + arm11->jtag_info.scann_instr = ARM11_SCAN_N; + /* cur_scan_chain == 0 */ + arm11->jtag_info.intest_instr = ARM11_INTEST; return ERROR_OK; } -int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm11_init_target(struct command_context *cmd_ctx, + struct target *target) { /* Initialize anything we can set up without talking to the target */ return arm11_build_reg_cache(target); } /* talk to the target and set things up */ -int arm11_examine(struct target_s *target) +static int arm11_examine(struct target *target) { - FNC_INFO; + int retval; - arm11_common_t * arm11 = target->arch_info; + FNC_INFO; + struct arm11_common *arm11 = target_to_arm11(target); /* check IDCODE */ arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT); - scan_field_t idcode_field; + struct scan_field idcode_field; arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field); @@ -1794,7 +1849,7 @@ int arm11_examine(struct target_s *target) arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain0_fields[2]; + struct scan_field chain0_fields[2]; arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); @@ -1809,11 +1864,9 @@ int arm11_examine(struct target_s *target) case 0x07B56000: LOG_INFO("found ARM1156"); break; case 0x07B76000: LOG_INFO("found ARM1176"); break; default: - { LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****"); return ERROR_FAIL; } - } arm11->debug_version = (arm11->didr >> 16) & 0x0F; @@ -1841,26 +1894,30 @@ int arm11_examine(struct target_s *target) * as suggested by the spec. */ - arm11_check_init(arm11, NULL); + retval = arm11_check_init(arm11, NULL); + if (retval != ERROR_OK) + return retval; + + /* ETM on ARM11 still uses original scanchain 6 access mode */ + if (arm11->arm.etm && !target_was_examined(target)) { + *register_get_last_cache_p(&target->reg_cache) = + etm_build_reg_cache(target, &arm11->jtag_info, + arm11->arm.etm); + retval = etm_setup(target); + } target_set_examined(target); return ERROR_OK; } -int arm11_quit(void) -{ - FNC_INFO_NOTIMPLEMENTED; - - return ERROR_OK; -} /** Load a register that is marked !valid in the register cache */ -int arm11_get_reg(reg_t *reg) +static int arm11_get_reg(struct reg *reg) { FNC_INFO; - target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target; + struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target; if (target->state != TARGET_HALTED) { @@ -1871,36 +1928,36 @@ int arm11_get_reg(reg_t *reg) /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */ #if 0 - arm11_common_t *arm11 = target->arch_info; - const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; + struct arm11_common *arm11 = target_to_arm11(target); + const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; #endif return ERROR_OK; } /** Change a value in the register cache */ -int arm11_set_reg(reg_t *reg, uint8_t *buf) +static int arm11_set_reg(struct reg *reg, uint8_t *buf) { FNC_INFO; - target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target; - arm11_common_t *arm11 = target->arch_info; -// const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index; + struct target *target = ((struct arm11_reg_state *)reg->arch_info)->target; + struct arm11_common *arm11 = target_to_arm11(target); +// const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index; - arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); + arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32); reg->valid = 1; reg->dirty = 1; return ERROR_OK; } -int arm11_build_reg_cache(target_t *target) +static int arm11_build_reg_cache(struct target *target) { - arm11_common_t *arm11 = target->arch_info; + struct arm11_common *arm11 = target_to_arm11(target); - NEW(reg_cache_t, cache, 1); - NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT); - NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT); + NEW(struct reg_cache, cache, 1); + NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT); + NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT); if (arm11_regs_arch_type == -1) arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg); @@ -1916,7 +1973,7 @@ int arm11_build_reg_cache(target_t *target) cache->reg_list = reg_list; cache->num_regs = ARM11_REGCACHE_COUNT; - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); (*cache_p) = cache; arm11->core_cache = cache; @@ -1935,17 +1992,15 @@ int arm11_build_reg_cache(target_t *target) for (i = 0; i < ARM11_REGCACHE_COUNT; i++) { - reg_t * r = reg_list + i; - const arm11_reg_defs_t * rd = arm11_reg_defs + i; - arm11_reg_state_t * rs = arm11_reg_states + i; + struct reg * r = reg_list + i; + const struct arm11_reg_defs * rd = arm11_reg_defs + i; + struct arm11_reg_state * rs = arm11_reg_states + i; r->name = rd->name; r->size = 32; r->value = (uint8_t *)(arm11->reg_values + i); r->dirty = 0; r->valid = 0; - r->bitfield_desc = NULL; - r->num_bitfields = 0; r->arch_type = arm11_regs_arch_type; r->arch_info = rs; @@ -1956,7 +2011,7 @@ int arm11_build_reg_cache(target_t *target) return ERROR_OK; } -int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name) +static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name) { if (argc == 0) { @@ -1992,25 +2047,26 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, } #define BOOL_WRAPPER(name, print_name) \ -int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \ +COMMAND_HANDLER(arm11_handle_bool_##name) \ { \ - return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \ + return CALL_COMMAND_HANDLER(arm11_handle_bool, \ + &arm11_config_##name, print_name); \ } BOOL_WRAPPER(memwrite_burst, "memory write burst mode") BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") -BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers") BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") BOOL_WRAPPER(hardware_step, "hardware single step") -int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm11_handle_vcr) { - if (argc == 1) - { - arm11_vcr = strtoul(args[0], NULL, 0); - } - else if (argc != 0) - { + switch (argc) { + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr); + break; + default: return ERROR_COMMAND_SYNTAX_ERROR; } @@ -2018,7 +2074,7 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, return ERROR_OK; } -const uint32_t arm11_coproc_instruction_limits[] = +static const uint32_t arm11_coproc_instruction_limits[] = { 15, /* coprocessor */ 7, /* opcode 1 */ @@ -2028,74 +2084,25 @@ const uint32_t arm11_coproc_instruction_limits[] = 0xFFFFFFFF, /* value */ }; -arm11_common_t * arm11_find_target(const char * arg) -{ - jtag_tap_t * tap; - target_t * t; - - tap = jtag_tap_by_string(arg); - - if (!tap) - return 0; - - for (t = all_targets; t; t = t->next) - { - if (t->tap != tap) - continue; - - /* if (t->type == arm11_target) */ - if (0 == strcmp(target_get_name(t), "arm11")) - return t->arch_info; - } - - return 0; -} - -int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read) +static int arm11_mrc_inner(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t *value, bool read) { int retval; + struct arm11_common *arm11 = target_to_arm11(target); - if (argc != (read ? 6 : 7)) - { - LOG_ERROR("Invalid number of arguments."); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - arm11_common_t * arm11 = arm11_find_target(args[0]); - - if (!arm11) - { - LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device."); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - if (arm11->target->state != TARGET_HALTED) - { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - uint32_t values[6]; - - for (size_t i = 0; i < (read ? 5 : 6); i++) + if (target->state != TARGET_HALTED) { - values[i] = strtoul(args[i + 1], NULL, 0); - - if (values[i] > arm11_coproc_instruction_limits[i]) - { - LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).", - (long)(i + 2), - arm11_coproc_instruction_limits[i]); - return ERROR_COMMAND_SYNTAX_ERROR; - } + LOG_ERROR("Target not halted"); + return ERROR_FAIL; } uint32_t instr = 0xEE000010 | - (values[0] << 8) | - (values[1] << 21) | - (values[2] << 16) | - (values[3] << 0) | - (values[4] << 5); + (cpnum << 8) | + (op1 << 21) | + (CRn << 16) | + (CRm << 0) | + (op2 << 5); if (read) instr |= 0x00100000; @@ -2106,48 +2113,37 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar if (read) { - uint32_t result; - retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); + retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value); if (retval != ERROR_OK) return retval; - - LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")", - (int)(values[0]), - (int)(values[1]), - (int)(values[2]), - (int)(values[3]), - (int)(values[4]), result, result); } else { - retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]); + retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value); if (retval != ERROR_OK) return retval; - - LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d", - (int)(values[0]), (int)(values[1]), - values[5], - (int)(values[2]), (int)(values[3]), (int)(values[4])); } return arm11_run_instr_data_finish(arm11); } -int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true); } -int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false); } -int arm11_register_commands(struct command_context_s *cmd_ctx) +static int arm11_register_commands(struct command_context *cmd_ctx) { FNC_INFO; - command_t *top_cmd, *mw_cmd; + struct command *top_cmd, *mw_cmd; top_cmd = register_command(cmd_ctx, NULL, "arm11", NULL, COMMAND_ANY, NULL); @@ -2161,10 +2157,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) "DEBUG ONLY - Hardware single stepping" " (default: disabled)"); - register_command(cmd_ctx, top_cmd, "mcr", - arm11_handle_mcr, COMMAND_ANY, - "Write Coprocessor register. mcr <32bit value to write>. All parameters are numbers only."); - mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite", NULL, COMMAND_ANY, NULL); register_command(cmd_ctx, mw_cmd, "burst", @@ -2176,13 +2168,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) "Terminate program if transfer error was found" " (default: enabled)"); - register_command(cmd_ctx, top_cmd, "mrc", - arm11_handle_mrc, COMMAND_ANY, - "Read Coprocessor register. mrc . All parameters are numbers only."); - register_command(cmd_ctx, top_cmd, "no_increment", - arm11_handle_bool_memrw_no_increment, COMMAND_ANY, - "Don't increment address on multi-read/-write" - " (default: disabled)"); register_command(cmd_ctx, top_cmd, "step_irq_enable", arm11_handle_bool_step_irq_enable, COMMAND_ANY, "Enable interrupts while stepping" @@ -2191,5 +2176,47 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) arm11_handle_vcr, COMMAND_ANY, "Control (Interrupt) Vector Catch Register"); - return ERROR_OK; + return etm_register_commands(cmd_ctx); } + +/** Holds methods for ARM11xx targets. */ +struct target_type arm11_target = { + .name = "arm11", + + .poll = arm11_poll, + .arch_state = arm11_arch_state, + + .target_request_data = arm11_target_request_data, + + .halt = arm11_halt, + .resume = arm11_resume, + .step = arm11_step, + + .assert_reset = arm11_assert_reset, + .deassert_reset = arm11_deassert_reset, + .soft_reset_halt = arm11_soft_reset_halt, + + .get_gdb_reg_list = arm11_get_gdb_reg_list, + + .read_memory = arm11_read_memory, + .write_memory = arm11_write_memory, + + .bulk_write_memory = arm11_bulk_write_memory, + + .checksum_memory = arm11_checksum_memory, + + .add_breakpoint = arm11_add_breakpoint, + .remove_breakpoint = arm11_remove_breakpoint, + .add_watchpoint = arm11_add_watchpoint, + .remove_watchpoint = arm11_remove_watchpoint, + + .run_algorithm = arm11_run_algorithm, + + .register_commands = arm11_register_commands, + .target_create = arm11_target_create, + .init_target = arm11_init_target, + .examine = arm11_examine, + + .mrc = arm11_mrc, + .mcr = arm11_mcr, +};