X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=0cb1d8c83fbd982f61270036330f31472af618b9;hp=61f1f64e16700b0ba91fa2b0063b37f5be94c86f;hb=ca0e237d39a8e50c702cec4d825c4b44d63e4d4a;hpb=d019080dfaa6c0c49228ecec2ad0c585ac65cb73

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 61f1f64e16..0cb1d8c83f 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1177,6 +1177,12 @@ static int arm11_examine(struct target *target)
 	LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
 		device_id, implementor, didr);
 
+	/* Build register cache "late", after target_init(), since we
+	 * want to know if this core supports Secure Monitor mode.
+	 */
+	if (!target_was_examined(target))
+		CHECK_RETVAL(arm11_dpm_init(arm11, didr));
+
 	/* as a side-effect this reads DSCR and thus
 	 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
 	 * as suggested by the spec.
@@ -1186,12 +1192,6 @@ static int arm11_examine(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* Build register cache "late", after target_init(), since we
-	 * want to know if this core supports Secure Monitor mode.
-	 */
-	if (!target_was_examined(target))
-		CHECK_RETVAL(arm11_dpm_init(arm11, didr));
-
 	/* ETM on ARM11 still uses original scanchain 6 access mode */
 	if (arm11->arm.etm && !target_was_examined(target)) {
 		*register_get_last_cache_p(&target->reg_cache) =