X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=2787eca9f074ae3065c8339d0d4f999e0c4c4987;hp=9d885de445ced3eaef1f194cb6fefab1b805f822;hb=b1de5eb9a074b362e953e857c42cac9a9b18b2a3;hpb=c202ba7d34bd7feba88d7c0ee1aa9ef7be18bca9

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 9d885de445..2787eca9f0 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -360,7 +360,7 @@ static int arm11_on_enter_debug_state(arm11_common_t *arm11)
 
 		arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-		scan_field_t	chain5_fields[3];
+		struct scan_field	chain5_fields[3];
 
 		arm11_setup_field(arm11, 32, NULL, &R(WDTR),	chain5_fields + 0);
 		arm11_setup_field(arm11,  1, NULL, NULL,		chain5_fields + 1);
@@ -637,7 +637,7 @@ static int arm11_leave_debug_state(arm11_common_t *arm11)
 
 		arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-		scan_field_t	chain5_fields[3];
+		struct scan_field	chain5_fields[3];
 
 		uint8_t			Ready		= 0;	/* ignored */
 		uint8_t			Valid		= 0;	/* ignored */
@@ -1614,8 +1614,8 @@ static int arm11_remove_watchpoint(struct target_s *target,
 // HACKHACKHACK - FIXME mode/state
 /* target algorithm support */
 static int arm11_run_algorithm(struct target_s *target,
-		int num_mem_params, mem_param_t *mem_params,
-		int num_reg_params, reg_param_t *reg_params,
+		int num_mem_params, struct mem_param *mem_params,
+		int num_reg_params, struct reg_param *reg_params,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info)
 {
@@ -1821,7 +1821,7 @@ static int arm11_examine(struct target_s *target)
 
 	arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
 
-	scan_field_t		idcode_field;
+	struct scan_field		idcode_field;
 
 	arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
 
@@ -1833,7 +1833,7 @@ static int arm11_examine(struct target_s *target)
 
 	arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-	scan_field_t		chain0_fields[2];
+	struct scan_field		chain0_fields[2];
 
 	arm11_setup_field(arm11, 32, NULL,	&arm11->didr,		chain0_fields + 0);
 	arm11_setup_field(arm11,  8, NULL,	&arm11->implementor,	chain0_fields + 1);
@@ -1991,8 +1991,7 @@ static int arm11_build_reg_cache(target_t *target)
 	return ERROR_OK;
 }
 
-static int arm11_handle_bool(struct command_context_s *cmd_ctx,
-		char *cmd, char **args, int argc, bool * var, char * name)
+static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name)
 {
 	if (argc == 0)
 	{
@@ -2028,9 +2027,10 @@ static int arm11_handle_bool(struct command_context_s *cmd_ctx,
 }
 
 #define BOOL_WRAPPER(name, print_name)	\
-static int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
+COMMAND_HANDLER(arm11_handle_bool_##name) \
 { \
-	return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
+	return CALL_COMMAND_HANDLER(arm11_handle_bool, \
+			&arm11_config_##name, print_name); \
 }
 
 BOOL_WRAPPER(memwrite_burst,			"memory write burst mode")
@@ -2038,7 +2038,7 @@ BOOL_WRAPPER(memwrite_error_fatal,		"fatal error mode for memory writes")
 BOOL_WRAPPER(step_irq_enable,			"IRQs while stepping")
 BOOL_WRAPPER(hardware_step,			"hardware single step")
 
-static int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+COMMAND_HANDLER(arm11_handle_vcr)
 {
 	switch (argc) {
 	case 0:
@@ -2066,7 +2066,7 @@ static const uint32_t arm11_coproc_instruction_limits[] =
 
 static arm11_common_t * arm11_find_target(const char * arg)
 {
-	jtag_tap_t *	tap;
+	struct jtag_tap *	tap;
 	target_t *		t;
 
 	tap = jtag_tap_by_string(arg);
@@ -2143,6 +2143,58 @@ static int arm11_mcr(target_t *target, int cpnum,
 	return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
 }
 
+static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
+{
+	if (argc != (read ? 2 : 3))
+	{
+		LOG_ERROR("Invalid number of arguments.");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	arm11_common_t * arm11 = arm11_find_target(args[0]);
+
+	if (!arm11)
+	{
+		LOG_ERROR("Parameter 1 is not the target name of an ARM11 device.");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	uint32_t address;
+	COMMAND_PARSE_NUMBER(u32, args[1], address);
+
+	if (!read)
+	{
+		uint32_t value;
+		COMMAND_PARSE_NUMBER(u32, args[2], value);
+
+		LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
+		  address, address, value, value);
+
+		CHECK_RETVAL(arm11_write_etm(arm11, address, value));
+	}
+	else
+	{
+		uint32_t value;
+
+		CHECK_RETVAL(arm11_read_etm(arm11, address, &value));
+
+	    LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")",
+		  address, address, value, value);
+	}
+
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(arm11_handle_etmr)
+{
+	return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, true);
+}
+
+COMMAND_HANDLER(arm11_handle_etmw)
+{
+	return CALL_COMMAND_HANDLER(arm11_handle_etm_read_write, false);
+}
+
 #define ARM11_HANDLER(x)	.x = arm11_##x
 
 target_type_t arm11_target = {
@@ -2196,6 +2248,14 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 	top_cmd = register_command(cmd_ctx, NULL, "arm11",
 			NULL, COMMAND_ANY, NULL);
 
+	register_command(cmd_ctx, top_cmd, "etmr",
+			arm11_handle_etmr, COMMAND_ANY,
+			"Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
+
+	register_command(cmd_ctx, top_cmd, "etmw",
+			arm11_handle_etmw, COMMAND_ANY,
+			"Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
+
 	/* "hardware_step" is only here to check if the default
 	 * simulate + breakpoint implementation is broken.
 	 * TEMPORARY! NOT DOCUMENTED!