X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=348dd8755f61c4e2a049a5605f98638a049a68ed;hp=b30e5181a87db7f820430aa47efb50e54e8ea918;hb=5d1a9033ab89b017c95e79590d76abbfa61f7512;hpb=817bf743023de7fea901e89157da57b90c7c326c

diff --git a/src/target/arm11.c b/src/target/arm11.c
index b30e5181a8..348dd8755f 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1551,16 +1551,6 @@ static int arm11_bulk_write_memory(struct target *target,
 	return arm11_write_memory(target, address, 4, count, buffer);
 }
 
-/* here we have nothing target specific to contribute, so we fail and then the
- * fallback code will read data from the target and calculate the CRC on the
- * host.
- */
-static int arm11_checksum_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t* checksum)
-{
-	return ERROR_FAIL;
-}
-
 /* target break-/watchpoint control
 * rw: 0 = write, 1 = read, 2 = access
 */
@@ -1898,6 +1888,14 @@ static int arm11_examine(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
+	/* ETM on ARM11 still uses original scanchain 6 access mode */
+	if (arm11->arm.etm && !target_was_examined(target)) {
+		*register_get_last_cache_p(&target->reg_cache) =
+			etm_build_reg_cache(target, &arm11->jtag_info,
+					arm11->arm.etm);
+		retval = etm_setup(target);
+	}
+
 	target_set_examined(target);
 
 	return ERROR_OK;
@@ -2131,51 +2129,7 @@ static int arm11_mcr(struct target *target, int cpnum,
 	return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
 }
 
-#define ARM11_HANDLER(x)	.x = arm11_##x
-
-struct target_type arm11_target = {
-		.name = "arm11",
-
-		ARM11_HANDLER(poll),
-		ARM11_HANDLER(arch_state),
-
-		ARM11_HANDLER(target_request_data),
-
-		ARM11_HANDLER(halt),
-		ARM11_HANDLER(resume),
-		ARM11_HANDLER(step),
-
-		ARM11_HANDLER(assert_reset),
-		ARM11_HANDLER(deassert_reset),
-		ARM11_HANDLER(soft_reset_halt),
-
-		ARM11_HANDLER(get_gdb_reg_list),
-
-		ARM11_HANDLER(read_memory),
-		ARM11_HANDLER(write_memory),
-
-		ARM11_HANDLER(bulk_write_memory),
-
-		ARM11_HANDLER(checksum_memory),
-
-		ARM11_HANDLER(add_breakpoint),
-		ARM11_HANDLER(remove_breakpoint),
-		ARM11_HANDLER(add_watchpoint),
-		ARM11_HANDLER(remove_watchpoint),
-
-		ARM11_HANDLER(run_algorithm),
-
-		ARM11_HANDLER(register_commands),
-		ARM11_HANDLER(target_create),
-		ARM11_HANDLER(init_target),
-		ARM11_HANDLER(examine),
-
-		ARM11_HANDLER(mrc),
-		ARM11_HANDLER(mcr),
-	};
-
-
-int arm11_register_commands(struct command_context *cmd_ctx)
+static int arm11_register_commands(struct command_context *cmd_ctx)
 {
 	FNC_INFO;
 
@@ -2212,5 +2166,48 @@ int arm11_register_commands(struct command_context *cmd_ctx)
 			arm11_handle_vcr, COMMAND_ANY,
 			"Control (Interrupt) Vector Catch Register");
 
-	return ERROR_OK;
+	return etm_register_commands(cmd_ctx);
 }
+
+/** Holds methods for ARM11xx targets. */
+struct target_type arm11_target = {
+	.name =			"arm11",
+
+	.poll =			arm11_poll,
+	.arch_state =		arm11_arch_state,
+
+	.target_request_data =	arm11_target_request_data,
+
+	.halt =			arm11_halt,
+	.resume =		arm11_resume,
+	.step =			arm11_step,
+
+	.assert_reset =		arm11_assert_reset,
+	.deassert_reset =	arm11_deassert_reset,
+	.soft_reset_halt =	arm11_soft_reset_halt,
+
+	.get_gdb_reg_list =	arm11_get_gdb_reg_list,
+
+	.read_memory =		arm11_read_memory,
+	.write_memory =		arm11_write_memory,
+
+	.bulk_write_memory =	arm11_bulk_write_memory,
+
+	.checksum_memory =	arm_checksum_memory,
+	.blank_check_memory =	arm_blank_check_memory,
+
+	.add_breakpoint =	arm11_add_breakpoint,
+	.remove_breakpoint =	arm11_remove_breakpoint,
+	.add_watchpoint =	arm11_add_watchpoint,
+	.remove_watchpoint =	arm11_remove_watchpoint,
+
+	.run_algorithm =	arm11_run_algorithm,
+
+	.register_commands =	arm11_register_commands,
+	.target_create =	arm11_target_create,
+	.init_target =		arm11_init_target,
+	.examine =		arm11_examine,
+
+	.mrc =			arm11_mrc,
+	.mcr =			arm11_mcr,
+};