X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=949c947596712c0ba839856112ec567746d2b75a;hp=289d64c05721ab33bcf6933f6dbb62af0f517d13;hb=63a26b421b1731df5826a157ea633b9d2c02aaee;hpb=510db585fd3996ff075539aac413eee955bf23b2 diff --git a/src/target/arm11.c b/src/target/arm11.c index 289d64c057..949c947596 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -27,6 +27,7 @@ #endif #include "arm11.h" +#include "arm11_dbgtap.h" #include "armv4_5.h" #include "arm_simulator.h" #include "time_support.h" @@ -49,59 +50,13 @@ #define FNC_INFO_NOTIMPLEMENTED #endif -static int arm11_on_enter_debug_state(arm11_common_t * arm11); - -bool arm11_config_memwrite_burst = true; -bool arm11_config_memwrite_error_fatal = true; -uint32_t arm11_vcr = 0; -bool arm11_config_step_irq_enable = false; -bool arm11_config_hardware_step = false; - -#define ARM11_HANDLER(x) \ - .x = arm11_##x - -target_type_t arm11_target = -{ - .name = "arm11", - - ARM11_HANDLER(poll), - ARM11_HANDLER(arch_state), - - ARM11_HANDLER(target_request_data), - - ARM11_HANDLER(halt), - ARM11_HANDLER(resume), - ARM11_HANDLER(step), - - ARM11_HANDLER(assert_reset), - ARM11_HANDLER(deassert_reset), - ARM11_HANDLER(soft_reset_halt), - - ARM11_HANDLER(get_gdb_reg_list), - - ARM11_HANDLER(read_memory), - ARM11_HANDLER(write_memory), - - ARM11_HANDLER(bulk_write_memory), - - ARM11_HANDLER(checksum_memory), - - ARM11_HANDLER(add_breakpoint), - ARM11_HANDLER(remove_breakpoint), - ARM11_HANDLER(add_watchpoint), - ARM11_HANDLER(remove_watchpoint), - - ARM11_HANDLER(run_algorithm), - - ARM11_HANDLER(register_commands), - ARM11_HANDLER(target_create), - ARM11_HANDLER(init_target), - ARM11_HANDLER(examine), - ARM11_HANDLER(quit), -}; - -int arm11_regs_arch_type = -1; +static bool arm11_config_memwrite_burst = true; +static bool arm11_config_memwrite_error_fatal = true; +static uint32_t arm11_vcr = 0; +static bool arm11_config_step_irq_enable = false; +static bool arm11_config_hardware_step = false; +static int arm11_regs_arch_type = -1; enum arm11_regtype { @@ -291,21 +246,32 @@ enum arm11_regcache_ids #define ARM11_GDB_REGISTER_COUNT 26 -uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -reg_t arm11_gdb_dummy_fp_reg = +static reg_t arm11_gdb_dummy_fp_reg = { "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 }; -uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; +static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0}; -reg_t arm11_gdb_dummy_fps_reg = +static reg_t arm11_gdb_dummy_fps_reg = { "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 }; +static int arm11_on_enter_debug_state(arm11_common_t *arm11); +static int arm11_step(struct target_s *target, int current, + uint32_t address, int handle_breakpoints); +/* helpers */ +static int arm11_build_reg_cache(target_t *target); +static int arm11_set_reg(reg_t *reg, uint8_t *buf); +static int arm11_get_reg(reg_t *reg); + +static void arm11_record_register_history(arm11_common_t * arm11); +static void arm11_dump_reg_changes(arm11_common_t * arm11); + /** Check and if necessary take control of the system * @@ -314,7 +280,7 @@ reg_t arm11_gdb_dummy_fps_reg = * available a pointer to a word holding the * DSCR can be passed. Otherwise use NULL. */ -int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) +static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr) { FNC_INFO; @@ -372,7 +338,7 @@ int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr) * or on other occasions that stop the processor. * */ -static int arm11_on_enter_debug_state(arm11_common_t * arm11) +static int arm11_on_enter_debug_state(arm11_common_t *arm11) { int retval; FNC_INFO; @@ -571,7 +537,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11) * This is called in preparation for the RESTART function. * */ -int arm11_leave_debug_state(arm11_common_t * arm11) +static int arm11_leave_debug_state(arm11_common_t *arm11) { FNC_INFO; int retval; @@ -688,7 +654,7 @@ int arm11_leave_debug_state(arm11_common_t * arm11) return ERROR_OK; } -void arm11_record_register_history(arm11_common_t * arm11) +static void arm11_record_register_history(arm11_common_t *arm11) { for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++) { @@ -702,7 +668,7 @@ void arm11_record_register_history(arm11_common_t * arm11) /* poll current target status */ -int arm11_poll(struct target_s *target) +static int arm11_poll(struct target_s *target) { FNC_INFO; int retval; @@ -747,7 +713,7 @@ int arm11_poll(struct target_s *target) return ERROR_OK; } /* architecture specific status reply */ -int arm11_arch_state(struct target_s *target) +static int arm11_arch_state(struct target_s *target) { arm11_common_t * arm11 = target->arch_info; @@ -760,7 +726,8 @@ int arm11_arch_state(struct target_s *target) } /* target request support */ -int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer) +static int arm11_target_request_data(struct target_s *target, + uint32_t size, uint8_t *buffer) { FNC_INFO_NOTIMPLEMENTED; @@ -768,7 +735,7 @@ int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *b } /* target execution control */ -int arm11_halt(struct target_s *target) +static int arm11_halt(struct target_s *target) { FNC_INFO; @@ -833,7 +800,8 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } -int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) +static int arm11_resume(struct target_s *target, int current, + uint32_t address, int handle_breakpoints, int debug_execution) { FNC_INFO; @@ -983,7 +951,8 @@ static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg) return buf_get_u32(arm11->reg_list[reg].value, 0, 32); } -static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value) +static void arm11_sim_set_reg(struct arm_sim_interface *sim, + int reg, uint32_t value) { arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; @@ -992,7 +961,8 @@ static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t v buf_set_u32(arm11->reg_list[reg].value, 0, 32, value); } -static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) +static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, + int pos, int bits) { arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; @@ -1007,7 +977,8 @@ static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim) return ARMV4_5_STATE_ARM; } -static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) +static void arm11_sim_set_state(struct arm_sim_interface *sim, + enum armv4_5_state mode) { // arm11_common_t * arm11 = (arm11_common_t *)sim->user_data; @@ -1042,7 +1013,8 @@ static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc) } -int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) +static int arm11_step(struct target_s *target, int current, + uint32_t address, int handle_breakpoints) { FNC_INFO; @@ -1197,7 +1169,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl return ERROR_OK; } -int arm11_assert_reset(target_t *target) +static int arm11_assert_reset(target_t *target) { FNC_INFO; int retval; @@ -1259,12 +1231,12 @@ int arm11_assert_reset(target_t *target) return ERROR_OK; } -int arm11_deassert_reset(target_t *target) +static int arm11_deassert_reset(target_t *target) { return ERROR_OK; } -int arm11_soft_reset_halt(struct target_s *target) +static int arm11_soft_reset_halt(struct target_s *target) { FNC_INFO_NOTIMPLEMENTED; @@ -1272,7 +1244,8 @@ int arm11_soft_reset_halt(struct target_s *target) } /* target register access for gdb */ -int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size) +static int arm11_get_gdb_reg_list(struct target_s *target, + struct reg_s **reg_list[], int *reg_list_size) { FNC_INFO; @@ -1307,7 +1280,8 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i * to read/write a range of data to a "port". a "port" is an action on * read memory address for some peripheral. */ -int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, +static int arm11_read_memory_inner(struct target_s *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, bool arm11_config_memrw_no_increment) { /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */ @@ -1394,7 +1368,7 @@ int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t return arm11_run_instr_data_finish(arm11); } -int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { return arm11_read_memory_inner(target, address, size, count, buffer, false); } @@ -1404,7 +1378,8 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, * to read/write a range of data to a "port". a "port" is an action on * read memory address for some peripheral. */ -int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, +static int arm11_write_memory_inner(struct target_s *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer, bool arm11_config_memrw_no_increment) { int retval; @@ -1542,13 +1517,15 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t return arm11_run_instr_data_finish(arm11); } -int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm11_write_memory(struct target_s *target, + uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { return arm11_write_memory_inner(target, address, size, count, buffer, false); } /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */ -int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer) +static int arm11_bulk_write_memory(struct target_s *target, + uint32_t address, uint32_t count, uint8_t *buffer) { FNC_INFO; @@ -1565,7 +1542,8 @@ int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t * fallback code will read data from the target and calculate the CRC on the * host. */ -int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) +static int arm11_checksum_memory(struct target_s *target, + uint32_t address, uint32_t count, uint32_t* checksum) { return ERROR_FAIL; } @@ -1573,7 +1551,8 @@ int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t co /* target break-/watchpoint control * rw: 0 = write, 1 = read, 2 = access */ -int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_add_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { FNC_INFO; @@ -1604,7 +1583,8 @@ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) +static int arm11_remove_breakpoint(struct target_s *target, + breakpoint_t *breakpoint) { FNC_INFO; @@ -1615,14 +1595,16 @@ int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } -int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_add_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { FNC_INFO_NOTIMPLEMENTED; return ERROR_OK; } -int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +static int arm11_remove_watchpoint(struct target_s *target, + watchpoint_t *watchpoint) { FNC_INFO_NOTIMPLEMENTED; @@ -1631,9 +1613,11 @@ int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) // HACKHACKHACK - FIXME mode/state /* target algorithm support */ -int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, - int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, - int timeout_ms, void *arch_info) +static int arm11_run_algorithm(struct target_s *target, + int num_mem_params, mem_param_t *mem_params, + int num_reg_params, reg_param_t *reg_params, + uint32_t entry_point, uint32_t exit_point, + int timeout_ms, void *arch_info) { arm11_common_t *arm11 = target->arch_info; // enum armv4_5_state core_state = arm11->core_state; @@ -1795,7 +1779,7 @@ restore: return retval; } -int arm11_target_create(struct target_s *target, Jim_Interp *interp) +static int arm11_target_create(struct target_s *target, Jim_Interp *interp) { FNC_INFO; @@ -1817,14 +1801,15 @@ int arm11_target_create(struct target_s *target, Jim_Interp *interp) return ERROR_OK; } -int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm11_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { /* Initialize anything we can set up without talking to the target */ return arm11_build_reg_cache(target); } /* talk to the target and set things up */ -int arm11_examine(struct target_s *target) +static int arm11_examine(struct target_s *target) { int retval; @@ -1904,15 +1889,9 @@ int arm11_examine(struct target_s *target) return ERROR_OK; } -int arm11_quit(void) -{ - FNC_INFO_NOTIMPLEMENTED; - - return ERROR_OK; -} /** Load a register that is marked !valid in the register cache */ -int arm11_get_reg(reg_t *reg) +static int arm11_get_reg(reg_t *reg) { FNC_INFO; @@ -1935,7 +1914,7 @@ int arm11_get_reg(reg_t *reg) } /** Change a value in the register cache */ -int arm11_set_reg(reg_t *reg, uint8_t *buf) +static int arm11_set_reg(reg_t *reg, uint8_t *buf) { FNC_INFO; @@ -1950,7 +1929,7 @@ int arm11_set_reg(reg_t *reg, uint8_t *buf) return ERROR_OK; } -int arm11_build_reg_cache(target_t *target) +static int arm11_build_reg_cache(target_t *target) { arm11_common_t *arm11 = target->arch_info; @@ -2012,7 +1991,7 @@ int arm11_build_reg_cache(target_t *target) return ERROR_OK; } -int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name) +static COMMAND_HELPER(arm11_handle_bool, bool *var, char *name) { if (argc == 0) { @@ -2048,7 +2027,7 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, } #define BOOL_WRAPPER(name, print_name) \ -int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \ +COMMAND_HANDLER(arm11_handle_bool_##name) \ { \ return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \ } @@ -2058,14 +2037,15 @@ BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes") BOOL_WRAPPER(step_irq_enable, "IRQs while stepping") BOOL_WRAPPER(hardware_step, "hardware single step") -int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm11_handle_vcr) { - if (argc == 1) - { - arm11_vcr = strtoul(args[0], NULL, 0); - } - else if (argc != 0) - { + switch (argc) { + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], arm11_vcr); + break; + default: return ERROR_COMMAND_SYNTAX_ERROR; } @@ -2073,7 +2053,7 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, return ERROR_OK; } -const uint32_t arm11_coproc_instruction_limits[] = +static const uint32_t arm11_coproc_instruction_limits[] = { 15, /* coprocessor */ 7, /* opcode 1 */ @@ -2083,7 +2063,7 @@ const uint32_t arm11_coproc_instruction_limits[] = 0xFFFFFFFF, /* value */ }; -arm11_common_t * arm11_find_target(const char * arg) +static arm11_common_t * arm11_find_target(const char * arg) { jtag_tap_t * tap; target_t * t; @@ -2106,51 +2086,26 @@ arm11_common_t * arm11_find_target(const char * arg) return 0; } -int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read) +static int arm11_mrc_inner(target_t *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, + uint32_t *value, bool read) { int retval; - - if (argc != (read ? 6 : 7)) - { - LOG_ERROR("Invalid number of arguments."); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - arm11_common_t * arm11 = arm11_find_target(args[0]); - - if (!arm11) - { - LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device."); - return ERROR_COMMAND_SYNTAX_ERROR; - } - - if (arm11->target->state != TARGET_HALTED) - { - LOG_WARNING("target was not halted"); - return ERROR_TARGET_NOT_HALTED; - } - - uint32_t values[6]; - - for (size_t i = 0; i < (read ? 5 : 6); i++) + + if (target->state != TARGET_HALTED) { - values[i] = strtoul(args[i + 1], NULL, 0); - - if (values[i] > arm11_coproc_instruction_limits[i]) - { - LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).", - (long)(i + 2), - arm11_coproc_instruction_limits[i]); - return ERROR_COMMAND_SYNTAX_ERROR; - } + LOG_ERROR("Target not halted"); + return ERROR_FAIL; } + + arm11_common_t * arm11 = target->arch_info; uint32_t instr = 0xEE000010 | - (values[0] << 8) | - (values[1] << 21) | - (values[2] << 16) | - (values[3] << 0) | - (values[4] << 5); + (cpnum << 8) | + (op1 << 21) | + (CRn << 16) | + (CRm << 0) | + (op2 << 5); if (read) instr |= 0x00100000; @@ -2161,43 +2116,128 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar if (read) { - uint32_t result; - retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); + retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, value); if (retval != ERROR_OK) return retval; - - LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")", - (int)(values[0]), - (int)(values[1]), - (int)(values[2]), - (int)(values[3]), - (int)(values[4]), result, result); } else { - retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]); + retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, *value); if (retval != ERROR_OK) return retval; - - LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d", - (int)(values[0]), (int)(values[1]), - values[5], - (int)(values[2]), (int)(values[3]), (int)(values[4])); } return arm11_run_instr_data_finish(arm11); } -int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mrc(target_t *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true); } -int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm11_mcr(target_t *target, int cpnum, + uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false); + return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false); } +static COMMAND_HELPER(arm11_handle_etm_read_write, bool read) +{ + if (argc != (read ? 2 : 3)) + { + LOG_ERROR("Invalid number of arguments."); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + arm11_common_t * arm11 = arm11_find_target(args[0]); + + if (!arm11) + { + LOG_ERROR("Parameter 1 is not the target name of an ARM11 device."); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + uint32_t address; + COMMAND_PARSE_NUMBER(u32, args[1], address); + + if (!read) + { + uint32_t value; + COMMAND_PARSE_NUMBER(u32, args[2], value); + + LOG_INFO("ETM write register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")", + address, address, value, value); + + CHECK_RETVAL(arm11_write_etm(arm11, address, value)); + } + else + { + uint32_t value; + + CHECK_RETVAL(arm11_read_etm(arm11, address, &value)); + + LOG_INFO("ETM read register 0x%02" PRIx32 " (%" PRId32 ") = 0x%08" PRIx32 " (%" PRId32 ")", + address, address, value, value); + } + + return ERROR_OK; +} + +COMMAND_HANDLER(arm11_handle_etmr) +{ + return arm11_handle_etm_read_write(cmd_ctx, cmd, args, argc, true); +} + +COMMAND_HANDLER(arm11_handle_etmw) +{ + return arm11_handle_etm_read_write(cmd_ctx, cmd, args, argc, false); +} + +#define ARM11_HANDLER(x) .x = arm11_##x + +target_type_t arm11_target = { + .name = "arm11", + + ARM11_HANDLER(poll), + ARM11_HANDLER(arch_state), + + ARM11_HANDLER(target_request_data), + + ARM11_HANDLER(halt), + ARM11_HANDLER(resume), + ARM11_HANDLER(step), + + ARM11_HANDLER(assert_reset), + ARM11_HANDLER(deassert_reset), + ARM11_HANDLER(soft_reset_halt), + + ARM11_HANDLER(get_gdb_reg_list), + + ARM11_HANDLER(read_memory), + ARM11_HANDLER(write_memory), + + ARM11_HANDLER(bulk_write_memory), + + ARM11_HANDLER(checksum_memory), + + ARM11_HANDLER(add_breakpoint), + ARM11_HANDLER(remove_breakpoint), + ARM11_HANDLER(add_watchpoint), + ARM11_HANDLER(remove_watchpoint), + + ARM11_HANDLER(run_algorithm), + + ARM11_HANDLER(register_commands), + ARM11_HANDLER(target_create), + ARM11_HANDLER(init_target), + ARM11_HANDLER(examine), + + ARM11_HANDLER(mrc), + ARM11_HANDLER(mcr), + }; + + int arm11_register_commands(struct command_context_s *cmd_ctx) { FNC_INFO; @@ -2207,6 +2247,14 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) top_cmd = register_command(cmd_ctx, NULL, "arm11", NULL, COMMAND_ANY, NULL); + register_command(cmd_ctx, top_cmd, "etmr", + arm11_handle_etmr, COMMAND_ANY, + "Read Embedded Trace Macrocell (ETM) register. etmr "); + + register_command(cmd_ctx, top_cmd, "etmw", + arm11_handle_etmw, COMMAND_ANY, + "Write Embedded Trace Macrocell (ETM) register. etmr "); + /* "hardware_step" is only here to check if the default * simulate + breakpoint implementation is broken. * TEMPORARY! NOT DOCUMENTED! @@ -2216,10 +2264,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) "DEBUG ONLY - Hardware single stepping" " (default: disabled)"); - register_command(cmd_ctx, top_cmd, "mcr", - arm11_handle_mcr, COMMAND_ANY, - "Write Coprocessor register. mcr <32bit value to write>. All parameters are numbers only."); - mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite", NULL, COMMAND_ANY, NULL); register_command(cmd_ctx, mw_cmd, "burst", @@ -2231,9 +2275,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) "Terminate program if transfer error was found" " (default: enabled)"); - register_command(cmd_ctx, top_cmd, "mrc", - arm11_handle_mrc, COMMAND_ANY, - "Read Coprocessor register. mrc . All parameters are numbers only."); register_command(cmd_ctx, top_cmd, "step_irq_enable", arm11_handle_bool_step_irq_enable, COMMAND_ANY, "Enable interrupts while stepping"