X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=a6f0d3cc7831feabd0a49a3b7a14dacdacfef764;hp=5b11f8e0f8b0851aacb7e9e2b62ab330def7befb;hb=04b514707f221ba00ae789e69f6f8047af96125d;hpb=5b6df55a1e5e4c0f531bc336691bc7c9a6a0df87

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 5b11f8e0f8..a6f0d3cc78 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -87,16 +87,16 @@ enum arm11_regtype
 };
 
 
-typedef struct arm11_reg_defs_s
+struct arm11_reg_defs
 {
 	char *					name;
 	uint32_t						num;
 	int						gdb_num;
 	enum arm11_regtype		type;
-} arm11_reg_defs_t;
+};
 
 /* update arm11_regcache_ids when changing this */
-static const arm11_reg_defs_t arm11_reg_defs[] =
+static const struct arm11_reg_defs arm11_reg_defs[] =
 {
 	{"r0",	0,	0,	ARM11_REGISTER_CORE},
 	{"r1",	1,	1,	ARM11_REGISTER_CORE},
@@ -246,31 +246,48 @@ enum arm11_regcache_ids
 
 #define ARM11_GDB_REGISTER_COUNT	26
 
-static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+/* FIXME these are *identical* to the ARMv4_5 dummies ...  except
+ * for their names, and being static vs global, and having different
+ * addresses.  Ditto ARMv7a and ARMv7m dummies.
+ */
+
+static uint8_t arm11_gdb_dummy_fp_value[12];
 
-static reg_t arm11_gdb_dummy_fp_reg =
+static struct reg arm11_gdb_dummy_fp_reg =
 {
-	"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
+	.name = "GDB dummy floating-point register",
+	.value = arm11_gdb_dummy_fp_value,
+	.dirty = 0,
+	.valid = 1,
+	.size = 96,
+	.arch_info = NULL,
+	.arch_type = 0,
 };
 
-static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+static uint8_t arm11_gdb_dummy_fps_value[4];
 
-static reg_t arm11_gdb_dummy_fps_reg =
+static struct reg arm11_gdb_dummy_fps_reg =
 {
-	"GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
+	.name = "GDB dummy floating-point status register",
+	.value = arm11_gdb_dummy_fps_value,
+	.dirty = 0,
+	.valid = 1,
+	.size = 32,
+	.arch_info = NULL,
+	.arch_type = 0,
 };
 
 
-static int arm11_on_enter_debug_state(arm11_common_t *arm11);
-static int arm11_step(struct target_s *target, int current,
+static int arm11_on_enter_debug_state(struct arm11_common *arm11);
+static int arm11_step(struct target *target, int current,
 		uint32_t address, int handle_breakpoints);
 /* helpers */
-static int arm11_build_reg_cache(target_t *target);
-static int arm11_set_reg(reg_t *reg, uint8_t *buf);
-static int arm11_get_reg(reg_t *reg);
+static int arm11_build_reg_cache(struct target *target);
+static int arm11_set_reg(struct reg *reg, uint8_t *buf);
+static int arm11_get_reg(struct reg *reg);
 
-static void arm11_record_register_history(arm11_common_t * arm11);
-static void arm11_dump_reg_changes(arm11_common_t * arm11);
+static void arm11_record_register_history(struct arm11_common * arm11);
+static void arm11_dump_reg_changes(struct arm11_common * arm11);
 
 
 /** Check and if necessary take control of the system
@@ -280,7 +297,7 @@ static void arm11_dump_reg_changes(arm11_common_t * arm11);
  *					available a pointer to a word holding the
  *					DSCR can be passed. Otherwise use NULL.
  */
-static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
+static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
 {
 	FNC_INFO;
 
@@ -338,7 +355,7 @@ static int arm11_check_init(arm11_common_t *arm11, uint32_t *dscr)
   * or on other occasions that stop the processor.
   *
   */
-static int arm11_on_enter_debug_state(arm11_common_t *arm11)
+static int arm11_on_enter_debug_state(struct arm11_common *arm11)
 {
 	int retval;
 	FNC_INFO;
@@ -360,7 +377,7 @@ static int arm11_on_enter_debug_state(arm11_common_t *arm11)
 
 		arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-		scan_field_t	chain5_fields[3];
+		struct scan_field	chain5_fields[3];
 
 		arm11_setup_field(arm11, 32, NULL, &R(WDTR),	chain5_fields + 0);
 		arm11_setup_field(arm11,  1, NULL, NULL,		chain5_fields + 1);
@@ -502,7 +519,7 @@ static int arm11_on_enter_debug_state(arm11_common_t *arm11)
 	return ERROR_OK;
 }
 
-void arm11_dump_reg_changes(arm11_common_t * arm11)
+void arm11_dump_reg_changes(struct arm11_common * arm11)
 {
 
 	if (!(debug_level >= LOG_LVL_DEBUG))
@@ -537,7 +554,7 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
   * This is called in preparation for the RESTART function.
   *
   */
-static int arm11_leave_debug_state(arm11_common_t *arm11)
+static int arm11_leave_debug_state(struct arm11_common *arm11)
 {
 	FNC_INFO;
 	int retval;
@@ -637,7 +654,7 @@ static int arm11_leave_debug_state(arm11_common_t *arm11)
 
 		arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-		scan_field_t	chain5_fields[3];
+		struct scan_field	chain5_fields[3];
 
 		uint8_t			Ready		= 0;	/* ignored */
 		uint8_t			Valid		= 0;	/* ignored */
@@ -654,7 +671,7 @@ static int arm11_leave_debug_state(arm11_common_t *arm11)
 	return ERROR_OK;
 }
 
-static void arm11_record_register_history(arm11_common_t *arm11)
+static void arm11_record_register_history(struct arm11_common *arm11)
 {
 	for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 	{
@@ -668,12 +685,12 @@ static void arm11_record_register_history(arm11_common_t *arm11)
 
 
 /* poll current target status */
-static int arm11_poll(struct target_s *target)
+static int arm11_poll(struct target *target)
 {
 	FNC_INFO;
 	int retval;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	uint32_t	dscr;
 
@@ -713,9 +730,9 @@ static int arm11_poll(struct target_s *target)
 	return ERROR_OK;
 }
 /* architecture specific status reply */
-static int arm11_arch_state(struct target_s *target)
+static int arm11_arch_state(struct target *target)
 {
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
@@ -726,7 +743,7 @@ static int arm11_arch_state(struct target_s *target)
 }
 
 /* target request support */
-static int arm11_target_request_data(struct target_s *target,
+static int arm11_target_request_data(struct target *target,
 		uint32_t size, uint8_t *buffer)
 {
 	FNC_INFO_NOTIMPLEMENTED;
@@ -735,11 +752,11 @@ static int arm11_target_request_data(struct target_s *target,
 }
 
 /* target execution control */
-static int arm11_halt(struct target_s *target)
+static int arm11_halt(struct target *target)
 {
 	FNC_INFO;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	LOG_DEBUG("target->state: %s",
 		target_state_name(target));
@@ -800,7 +817,7 @@ static int arm11_halt(struct target_s *target)
 	return ERROR_OK;
 }
 
-static int arm11_resume(struct target_s *target, int current,
+static int arm11_resume(struct target *target, int current,
 		uint32_t address, int handle_breakpoints, int debug_execution)
 {
 	FNC_INFO;
@@ -808,7 +825,7 @@ static int arm11_resume(struct target_s *target, int current,
 	//	  LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 	//	current, address, handle_breakpoints, debug_execution);
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	LOG_DEBUG("target->state: %s",
 		target_state_name(target));
@@ -833,7 +850,7 @@ static int arm11_resume(struct target_s *target, int current,
 	{
 		/* check if one matches PC and step over it if necessary */
 
-		breakpoint_t *	bp;
+		struct breakpoint *	bp;
 
 		for (bp = target->breakpoints; bp; bp = bp->next)
 		{
@@ -851,7 +868,7 @@ static int arm11_resume(struct target_s *target, int current,
 
 		for (bp = target->breakpoints; bp; bp = bp->next)
 		{
-			arm11_sc7_action_t	brp[2];
+			struct arm11_sc7_action	brp[2];
 
 			brp[0].write	= 1;
 			brp[0].address	= ARM11_SC7_BVR0 + brp_num;
@@ -944,7 +961,7 @@ static int armv4_5_to_arm11(int reg)
 
 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 {
-	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+	struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
 	reg=armv4_5_to_arm11(reg);
 
@@ -954,7 +971,7 @@ static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 static void arm11_sim_set_reg(struct arm_sim_interface *sim,
 		int reg, uint32_t value)
 {
-	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+	struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
 	reg=armv4_5_to_arm11(reg);
 
@@ -964,14 +981,14 @@ static void arm11_sim_set_reg(struct arm_sim_interface *sim,
 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim,
 		int pos, int bits)
 {
-	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+	struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
 	return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
 }
 
 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 {
-//	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+//	struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
 	/* FIX!!!! we should implement thumb for arm11 */
 	return ARMV4_5_STATE_ARM;
@@ -980,7 +997,7 @@ static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 static void arm11_sim_set_state(struct arm_sim_interface *sim,
 		enum armv4_5_state mode)
 {
-//	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+//	struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
 	/* FIX!!!! we should implement thumb for arm11 */
 	LOG_ERROR("Not implemetned!");
@@ -989,13 +1006,13 @@ static void arm11_sim_set_state(struct arm_sim_interface *sim,
 
 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
 {
-	//arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+	//struct arm11_common * arm11 = (struct arm11_common *)sim->user_data;
 
 	/* FIX!!!! we should implement something that returns the current mode here!!! */
 	return ARMV4_5_MODE_USR;
 }
 
-static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
+static int arm11_simulate_step(struct target *target, uint32_t *dry_run_pc)
 {
 	struct arm_sim_interface sim;
 
@@ -1013,7 +1030,7 @@ static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
 
 }
 
-static int arm11_step(struct target_s *target, int current,
+static int arm11_step(struct target *target, int current,
 		uint32_t address, int handle_breakpoints)
 {
 	FNC_INFO;
@@ -1027,7 +1044,7 @@ static int arm11_step(struct target_s *target, int current,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	if (!current)
 		R(PC) = address;
@@ -1074,7 +1091,7 @@ static int arm11_step(struct target_s *target, int current,
 
 		/* Set up breakpoint for stepping */
 
-		arm11_sc7_action_t	brp[2];
+		struct arm11_sc7_action	brp[2];
 
 		brp[0].write	= 1;
 		brp[0].address	= ARM11_SC7_BVR0;
@@ -1169,12 +1186,12 @@ static int arm11_step(struct target_s *target, int current,
 	return ERROR_OK;
 }
 
-static int arm11_assert_reset(target_t *target)
+static int arm11_assert_reset(struct target *target)
 {
 	FNC_INFO;
 	int retval;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 	retval = arm11_check_init(arm11, NULL);
 	if (retval != ERROR_OK)
 		return retval;
@@ -1231,12 +1248,12 @@ static int arm11_assert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-static int arm11_deassert_reset(target_t *target)
+static int arm11_deassert_reset(struct target *target)
 {
 	return ERROR_OK;
 }
 
-static int arm11_soft_reset_halt(struct target_s *target)
+static int arm11_soft_reset_halt(struct target *target)
 {
 	FNC_INFO_NOTIMPLEMENTED;
 
@@ -1244,15 +1261,15 @@ static int arm11_soft_reset_halt(struct target_s *target)
 }
 
 /* target register access for gdb */
-static int arm11_get_gdb_reg_list(struct target_s *target,
-		struct reg_s **reg_list[], int *reg_list_size)
+static int arm11_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size)
 {
 	FNC_INFO;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	*reg_list_size	= ARM11_GDB_REGISTER_COUNT;
-	*reg_list		= malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
+	*reg_list		= malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
 
 	for (size_t i = 16; i < 24; i++)
 	{
@@ -1280,7 +1297,7 @@ static int arm11_get_gdb_reg_list(struct target_s *target,
  * to read/write a range of data to a "port". a "port" is an action on
  * read memory address for some peripheral.
  */
-static int arm11_read_memory_inner(struct target_s *target,
+static int arm11_read_memory_inner(struct target *target,
 		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 		bool arm11_config_memrw_no_increment)
 {
@@ -1297,7 +1314,7 @@ static int arm11_read_memory_inner(struct target_s *target,
 
 	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	retval = arm11_run_instr_data_prepare(arm11);
 	if (retval != ERROR_OK)
@@ -1368,7 +1385,7 @@ static int arm11_read_memory_inner(struct target_s *target,
 	return arm11_run_instr_data_finish(arm11);
 }
 
-static int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	return arm11_read_memory_inner(target, address, size, count, buffer, false);
 }
@@ -1378,7 +1395,7 @@ static int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t
 * to read/write a range of data to a "port". a "port" is an action on
 * read memory address for some peripheral.
 */
-static int arm11_write_memory_inner(struct target_s *target,
+static int arm11_write_memory_inner(struct target *target,
 		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 		bool arm11_config_memrw_no_increment)
 {
@@ -1393,7 +1410,7 @@ static int arm11_write_memory_inner(struct target_s *target,
 
 	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	retval = arm11_run_instr_data_prepare(arm11);
 	if (retval != ERROR_OK)
@@ -1517,14 +1534,14 @@ static int arm11_write_memory_inner(struct target_s *target,
 	return arm11_run_instr_data_finish(arm11);
 }
 
-static int arm11_write_memory(struct target_s *target,
+static int arm11_write_memory(struct target *target,
 		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	return arm11_write_memory_inner(target, address, size, count, buffer, false);
 }
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
-static int arm11_bulk_write_memory(struct target_s *target,
+static int arm11_bulk_write_memory(struct target *target,
 		uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	FNC_INFO;
@@ -1542,7 +1559,7 @@ static int arm11_bulk_write_memory(struct target_s *target,
  * fallback code will read data from the target and calculate the CRC on the
  * host.
  */
-static int arm11_checksum_memory(struct target_s *target,
+static int arm11_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t* checksum)
 {
 	return ERROR_FAIL;
@@ -1551,12 +1568,12 @@ static int arm11_checksum_memory(struct target_s *target,
 /* target break-/watchpoint control
 * rw: 0 = write, 1 = read, 2 = access
 */
-static int arm11_add_breakpoint(struct target_s *target,
-		breakpoint_t *breakpoint)
+static int arm11_add_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
 {
 	FNC_INFO;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 #if 0
 	if (breakpoint->type == BKPT_SOFT)
@@ -1583,28 +1600,28 @@ static int arm11_add_breakpoint(struct target_s *target,
 	return ERROR_OK;
 }
 
-static int arm11_remove_breakpoint(struct target_s *target,
-		breakpoint_t *breakpoint)
+static int arm11_remove_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
 {
 	FNC_INFO;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	arm11->free_brps++;
 
 	return ERROR_OK;
 }
 
-static int arm11_add_watchpoint(struct target_s *target,
-		watchpoint_t *watchpoint)
+static int arm11_add_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
 {
 	FNC_INFO_NOTIMPLEMENTED;
 
 	return ERROR_OK;
 }
 
-static int arm11_remove_watchpoint(struct target_s *target,
-		watchpoint_t *watchpoint)
+static int arm11_remove_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
 {
 	FNC_INFO_NOTIMPLEMENTED;
 
@@ -1613,13 +1630,13 @@ static int arm11_remove_watchpoint(struct target_s *target,
 
 // HACKHACKHACK - FIXME mode/state
 /* target algorithm support */
-static int arm11_run_algorithm(struct target_s *target,
-		int num_mem_params, mem_param_t *mem_params,
-		int num_reg_params, reg_param_t *reg_params,
+static int arm11_run_algorithm(struct target *target,
+		int num_mem_params, struct mem_param *mem_params,
+		int num_reg_params, struct reg_param *reg_params,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info)
 {
-		arm11_common_t *arm11 = target->arch_info;
+		struct arm11_common *arm11 = target->arch_info;
 //	enum armv4_5_state core_state = arm11->core_state;
 //	enum armv4_5_mode core_mode = arm11->core_mode;
 	uint32_t context[16];
@@ -1657,7 +1674,7 @@ static int arm11_run_algorithm(struct target_s *target,
 	// Set register parameters
 	for (int i = 0; i < num_reg_params; i++)
 	{
-		reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+		struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
 		if (!reg)
 		{
 			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -1742,7 +1759,7 @@ static int arm11_run_algorithm(struct target_s *target,
 	{
 		if (reg_params[i].direction != PARAM_OUT)
 		{
-			reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+			struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
 			if (!reg)
 			{
 				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
@@ -1779,11 +1796,11 @@ restore:
 	return retval;
 }
 
-static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
+static int arm11_target_create(struct target *target, Jim_Interp *interp)
 {
 	FNC_INFO;
 
-	NEW(arm11_common_t, arm11, 1);
+	NEW(struct arm11_common, arm11, 1);
 
 	arm11->target = target;
 
@@ -1801,27 +1818,27 @@ static int arm11_target_create(struct target_s *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-static int arm11_init_target(struct command_context_s *cmd_ctx,
-		struct target_s *target)
+static int arm11_init_target(struct command_context *cmd_ctx,
+		struct target *target)
 {
 	/* Initialize anything we can set up without talking to the target */
 	return arm11_build_reg_cache(target);
 }
 
 /* talk to the target and set things up */
-static int arm11_examine(struct target_s *target)
+static int arm11_examine(struct target *target)
 {
 	int retval;
 
 	FNC_INFO;
 
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	/* check IDCODE */
 
 	arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
 
-	scan_field_t		idcode_field;
+	struct scan_field		idcode_field;
 
 	arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
 
@@ -1833,7 +1850,7 @@ static int arm11_examine(struct target_s *target)
 
 	arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-	scan_field_t		chain0_fields[2];
+	struct scan_field		chain0_fields[2];
 
 	arm11_setup_field(arm11, 32, NULL,	&arm11->didr,		chain0_fields + 0);
 	arm11_setup_field(arm11,  8, NULL,	&arm11->implementor,	chain0_fields + 1);
@@ -1891,11 +1908,11 @@ static int arm11_examine(struct target_s *target)
 
 
 /** Load a register that is marked !valid in the register cache */
-static int arm11_get_reg(reg_t *reg)
+static int arm11_get_reg(struct reg *reg)
 {
 	FNC_INFO;
 
-	target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
+	struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -1906,36 +1923,36 @@ static int arm11_get_reg(reg_t *reg)
 	/** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
 
 #if 0
-	arm11_common_t *arm11 = target->arch_info;
-	const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+	struct arm11_common *arm11 = target->arch_info;
+	const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
 #endif
 
 	return ERROR_OK;
 }
 
 /** Change a value in the register cache */
-static int arm11_set_reg(reg_t *reg, uint8_t *buf)
+static int arm11_set_reg(struct reg *reg, uint8_t *buf)
 {
 	FNC_INFO;
 
-	target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
-	arm11_common_t *arm11 = target->arch_info;
-//	  const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
+	struct target * target = ((struct arm11_reg_state *)reg->arch_info)->target;
+	struct arm11_common *arm11 = target->arch_info;
+//	  const struct arm11_reg_defs * arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
 
-	arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
+	arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
 	reg->valid	= 1;
 	reg->dirty	= 1;
 
 	return ERROR_OK;
 }
 
-static int arm11_build_reg_cache(target_t *target)
+static int arm11_build_reg_cache(struct target *target)
 {
-	arm11_common_t *arm11 = target->arch_info;
+	struct arm11_common *arm11 = target->arch_info;
 
-	NEW(reg_cache_t,		cache,				1);
-	NEW(reg_t,				reg_list,			ARM11_REGCACHE_COUNT);
-	NEW(arm11_reg_state_t,	arm11_reg_states,	ARM11_REGCACHE_COUNT);
+	NEW(struct reg_cache,		cache,				1);
+	NEW(struct reg,				reg_list,			ARM11_REGCACHE_COUNT);
+	NEW(struct arm11_reg_state,	arm11_reg_states,	ARM11_REGCACHE_COUNT);
 
 	if (arm11_regs_arch_type == -1)
 		arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
@@ -1951,7 +1968,7 @@ static int arm11_build_reg_cache(target_t *target)
 	cache->reg_list	= reg_list;
 	cache->num_regs	= ARM11_REGCACHE_COUNT;
 
-	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	(*cache_p) = cache;
 
 	arm11->core_cache = cache;
@@ -1970,17 +1987,15 @@ static int arm11_build_reg_cache(target_t *target)
 
 	for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
 	{
-		reg_t *						r	= reg_list			+ i;
-		const arm11_reg_defs_t *	rd	= arm11_reg_defs	+ i;
-		arm11_reg_state_t *			rs	= arm11_reg_states	+ i;
+		struct reg *						r	= reg_list			+ i;
+		const struct arm11_reg_defs *	rd	= arm11_reg_defs	+ i;
+		struct arm11_reg_state *			rs	= arm11_reg_states	+ i;
 
 		r->name				= rd->name;
 		r->size				= 32;
 		r->value			= (uint8_t *)(arm11->reg_values + i);
 		r->dirty			= 0;
 		r->valid			= 0;
-		r->bitfield_desc	= NULL;
-		r->num_bitfields	= 0;
 		r->arch_type		= arm11_regs_arch_type;
 		r->arch_info		= rs;
 
@@ -2064,10 +2079,10 @@ static const uint32_t arm11_coproc_instruction_limits[] =
 	0xFFFFFFFF,		/* value */
 };
 
-static arm11_common_t * arm11_find_target(const char * arg)
+static struct arm11_common * arm11_find_target(const char * arg)
 {
-	jtag_tap_t *	tap;
-	target_t *		t;
+	struct jtag_tap *	tap;
+	struct target *		t;
 
 	tap = jtag_tap_by_string(arg);
 
@@ -2087,7 +2102,7 @@ static arm11_common_t * arm11_find_target(const char * arg)
 	return 0;
 }
 
-static int arm11_mrc_inner(target_t *target, int cpnum,
+static int arm11_mrc_inner(struct target *target, int cpnum,
 		uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
 		uint32_t *value, bool read)
 {
@@ -2099,7 +2114,7 @@ static int arm11_mrc_inner(target_t *target, int cpnum,
 		return ERROR_FAIL;
 	}
 		
-	arm11_common_t * arm11 = target->arch_info;
+	struct arm11_common * arm11 = target->arch_info;
 
 	uint32_t instr = 0xEE000010	|
 		(cpnum <<  8) |
@@ -2131,13 +2146,13 @@ static int arm11_mrc_inner(target_t *target, int cpnum,
 	return arm11_run_instr_data_finish(arm11);
 }
 
-static int arm11_mrc(target_t *target, int cpnum,
+static int arm11_mrc(struct target *target, int cpnum,
 		uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
 {
 	return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, value, true);
 }
 
-static int arm11_mcr(target_t *target, int cpnum,
+static int arm11_mcr(struct target *target, int cpnum,
 		uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
 {
 	return arm11_mrc_inner(target, cpnum, op1, op2, CRn, CRm, &value, false);
@@ -2151,7 +2166,7 @@ static COMMAND_HELPER(arm11_handle_etm_read_write, bool read)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	arm11_common_t * arm11 = arm11_find_target(args[0]);
+	struct arm11_common * arm11 = arm11_find_target(args[0]);
 
 	if (!arm11)
 	{
@@ -2197,7 +2212,7 @@ COMMAND_HANDLER(arm11_handle_etmw)
 
 #define ARM11_HANDLER(x)	.x = arm11_##x
 
-target_type_t arm11_target = {
+struct target_type arm11_target = {
 		.name = "arm11",
 
 		ARM11_HANDLER(poll),
@@ -2239,11 +2254,11 @@ target_type_t arm11_target = {
 	};
 
 
-int arm11_register_commands(struct command_context_s *cmd_ctx)
+int arm11_register_commands(struct command_context *cmd_ctx)
 {
 	FNC_INFO;
 
-	command_t *top_cmd, *mw_cmd;
+	struct command *top_cmd, *mw_cmd;
 
 	top_cmd = register_command(cmd_ctx, NULL, "arm11",
 			NULL, COMMAND_ANY, NULL);