X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.c;h=da779b08e069f61abbdd7cf3bfe02d1b065668b6;hp=85068a11194023762b1985bedade9cf142a55dfd;hb=dfbb9f3e89ae;hpb=6d3bed69dc023f49b51b6504d977463e722e9e9d diff --git a/src/target/arm11.c b/src/target/arm11.c index 85068a1119..da779b08e0 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -16,6 +16,7 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -33,13 +34,13 @@ #if 0 -#define FNC_INFO DEBUG("-") +#define FNC_INFO LOG_DEBUG("-") #else #define FNC_INFO #endif #if 1 -#define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0) +#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0) #else #define FNC_INFO_NOTIMPLEMENTED #endif @@ -47,8 +48,8 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11); -int arm11_config_memwrite_burst = 1; -int arm11_config_memwrite_error_fatal = 1; +bool arm11_config_memwrite_burst = true; +bool arm11_config_memwrite_error_fatal = true; u32 arm11_vcr = 0; @@ -71,7 +72,6 @@ target_type_t arm11_target = ARM11_HANDLER(assert_reset), ARM11_HANDLER(deassert_reset), ARM11_HANDLER(soft_reset_halt), - ARM11_HANDLER(prepare_reset_halt), ARM11_HANDLER(get_gdb_reg_list), @@ -92,6 +92,7 @@ target_type_t arm11_target = ARM11_HANDLER(register_commands), ARM11_HANDLER(target_command), ARM11_HANDLER(init_target), + ARM11_HANDLER(examine), ARM11_HANDLER(quit), }; @@ -281,7 +282,6 @@ enum arm11_regcache_ids ARM11_RC_WDTR, ARM11_RC_RDTR, - ARM11_RC_MAX, }; @@ -324,15 +324,21 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr) if (!(*dscr & ARM11_DSCR_MODE_SELECT)) { - DEBUG("Bringing target into debug mode"); + LOG_DEBUG("Bringing target into debug mode"); *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */ arm11_write_DSCR(arm11, *dscr); /* add further reset initialization here */ + arm11->simulate_reset_on_next_halt = true; + if (*dscr & ARM11_DSCR_CORE_HALTED) { + /** \todo TODO: this needs further scrutiny because + * arm11_on_enter_debug_state() never gets properly called + */ + arm11->target->state = TARGET_HALTED; arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr); } @@ -404,15 +410,6 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11) arm11_write_DSCR(arm11, new_dscr); -// jtag_execute_queue(); - - - -// DEBUG("SAVE DSCR %08x", R(DSCR)); - -// if (R(DSCR) & ARM11_DSCR_WDTR_FULL) -// DEBUG("SAVE wDTR %08x", R(WDTR)); - /* From the spec: Before executing any instruction in debug state you have to drain the write buffer. @@ -431,7 +428,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11) u32 dscr = arm11_read_DSCR(arm11); - DEBUG("DRAIN, DSCR %08x", dscr); + LOG_DEBUG("DRAIN, DSCR %08x", dscr); if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) { @@ -439,7 +436,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11) dscr = arm11_read_DSCR(arm11); - DEBUG("DRAIN, DSCR %08x (DONE)", dscr); + LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr); break; } @@ -501,7 +498,18 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11) arm11->reg_values[ARM11_RC_PC] -= 8; } -// DEBUG("SAVE PC %08x", R(PC)); + if (arm11->simulate_reset_on_next_halt) + { + arm11->simulate_reset_on_next_halt = false; + + LOG_DEBUG("Reset c1 Control Register"); + + /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */ + + /* MCR p15,0,R0,c1,c0,0 */ + arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0); + + } arm11_run_instr_data_finish(arm11); @@ -516,18 +524,18 @@ void arm11_dump_reg_changes(arm11_common_t * arm11) if (!arm11->reg_list[i].valid) { if (arm11->reg_history[i].valid) - INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value); + LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value); } else { if (arm11->reg_history[i].valid) { if (arm11->reg_history[i].value != arm11->reg_values[i]) - INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); + LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value); } else { - INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); + LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]); } } }} @@ -557,7 +565,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11) /* MRC p14,0,r?,c0,c5,0 */ arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i)); -// DEBUG("RESTORE R%d %08x", i, R(RX + i)); +// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i)); }} arm11_run_instr_data_finish(arm11); @@ -571,7 +579,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11) if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL)) { - ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR); + LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR); } } @@ -659,7 +667,7 @@ int arm11_poll(struct target_s *target) u32 dscr = arm11_read_DSCR(arm11); - DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08x", dscr); arm11_check_init(arm11, &dscr); @@ -669,7 +677,7 @@ int arm11_poll(struct target_s *target) { enum target_state old_state = target->state; - DEBUG("enter TARGET_HALTED"); + LOG_DEBUG("enter TARGET_HALTED"); target->state = TARGET_HALTED; target->debug_reason = arm11_get_DSCR_debug_reason(dscr); arm11_on_enter_debug_state(arm11); @@ -682,7 +690,7 @@ int arm11_poll(struct target_s *target) { if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) { - DEBUG("enter TARGET_RUNNING"); + LOG_DEBUG("enter TARGET_RUNNING"); target->state = TARGET_RUNNING; target->debug_reason = DBG_REASON_NOTHALTED; } @@ -716,17 +724,22 @@ int arm11_halt(struct target_s *target) arm11_common_t * arm11 = target->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); + + if (target->state == TARGET_UNKNOWN) + { + arm11->simulate_reset_on_next_halt = true; + } if (target->state == TARGET_HALTED) { - WARNING("target was already halted"); - return ERROR_TARGET_ALREADY_HALTED; + LOG_DEBUG("target was already halted"); + return ERROR_OK; } if (arm11->trst_active) { - arm11->halt_requested = 1; + arm11->halt_requested = true; return ERROR_OK; } @@ -762,23 +775,23 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b { FNC_INFO; -// DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", +// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", // current, address, handle_breakpoints, debug_execution); arm11_common_t * arm11 = target->arch_info; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); if (target->state != TARGET_HALTED) { - WARNING("target was not halted"); + LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } if (!current) R(PC) = address; - INFO("RESUME PC %08x", R(PC)); + LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : ""); /* clear breakpoints/watchpoints and VCR*/ arm11_sc7_clear_vbw(arm11); @@ -794,7 +807,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b { if (bp->address == R(PC)) { - DEBUG("must step over %08x", bp->address); + LOG_DEBUG("must step over %08x", bp->address); arm11_step(target, 1, 0, 0); break; } @@ -817,7 +830,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b arm11_sc7_run(arm11, brp, asizeof(brp)); - DEBUG("Add BP %d at %08x", brp_num, bp->address); + LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address); brp_num++; } @@ -836,7 +849,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b { u32 dscr = arm11_read_DSCR(arm11); - DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08x", dscr); if (dscr & ARM11_DSCR_CORE_RESTARTED) break; @@ -862,11 +875,11 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre { FNC_INFO; - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); if (target->state != TARGET_HALTED) { - WARNING("target was not halted"); + LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -875,7 +888,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre if (!current) R(PC) = address; - INFO("STEP PC %08x", R(PC)); + LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : ""); /** \todo TODO: Thumb not supported here */ @@ -883,18 +896,27 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre arm11_read_memory_word(arm11, R(PC), &next_instruction); - /** skip over BKPT */ + /* skip over BKPT */ if ((next_instruction & 0xFFF00070) == 0xe1200070) { R(PC) += 4; arm11->reg_list[ARM11_RC_PC].valid = 1; arm11->reg_list[ARM11_RC_PC].dirty = 0; - INFO("Skipping BKPT"); + LOG_INFO("Skipping BKPT"); + } + /* skip over Wait for interrupt / Standby */ + /* mcr 15, 0, r?, cr7, cr0, {4} */ + else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) + { + R(PC) += 4; + arm11->reg_list[ARM11_RC_PC].valid = 1; + arm11->reg_list[ARM11_RC_PC].dirty = 0; + LOG_INFO("Skipping WFI"); } /* ignore B to self */ else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe) { - INFO("Not stepping jump to self"); + LOG_INFO("Not stepping jump to self"); } else { @@ -934,7 +956,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre { u32 dscr = arm11_read_DSCR(arm11); - DEBUG("DSCR %08x", dscr); + LOG_DEBUG("DSCR %08x", dscr); if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) == (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) @@ -970,7 +992,7 @@ int arm11_assert_reset(struct target_s *target) jtag_add_sleep(5000); arm11_common_t * arm11 = target->arch_info; - arm11->trst_active = 1; + arm11->trst_active = true; #endif return ERROR_OK; @@ -981,7 +1003,7 @@ int arm11_deassert_reset(struct target_s *target) FNC_INFO; #if 0 - DEBUG("target->state: %s", target_state_strings[target->state]); + LOG_DEBUG("target->state: %s", target_state_strings[target->state]); /* deassert reset lines */ jtag_add_reset(0, 0); @@ -1003,12 +1025,6 @@ int arm11_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int arm11_prepare_reset_halt(struct target_s *target) -{ - FNC_INFO_NOTIMPLEMENTED; - - return ERROR_OK; -} /* target register access for gdb */ @@ -1018,11 +1034,6 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i arm11_common_t * arm11 = target->arch_info; - if (target->state != TARGET_HALTED) - { - return ERROR_TARGET_NOT_HALTED; - } - *reg_list_size = ARM11_GDB_REGISTER_COUNT; *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT); @@ -1058,7 +1069,13 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, FNC_INFO; - DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); arm11_common_t * arm11 = target->arch_info; @@ -1073,7 +1090,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */ arm11->reg_list[ARM11_RC_R1].dirty = 1; - while (count--) + {size_t i; + for (i = 0; i < count; i++) { /* ldrb r1, [r0], #1 */ arm11_run_instr_no_data1(arm11, 0xe4d01001); @@ -1083,7 +1101,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); *buffer++ = res; - } + }} + break; case 2: @@ -1092,7 +1111,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u16 * buf16 = (u16*)buffer; - while (count--) + {size_t i; + for (i = 0; i < count; i++) { /* ldrh r1, [r0], #2 */ arm11_run_instr_no_data1(arm11, 0xe0d010b2); @@ -1103,7 +1123,8 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1); *buf16++ = res; - } + }} + break; } @@ -1123,7 +1144,13 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count { FNC_INFO; - DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count); arm11_common_t * arm11 = target->arch_info; @@ -1135,17 +1162,21 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count switch (size) { case 1: + { arm11->reg_list[ARM11_RC_R1].dirty = 1; - while (count--) + {size_t i; + for (i = 0; i < count; i++) { /* MRC p14,0,r1,c0,c5,0 */ arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); /* strb r1, [r0], #1 */ arm11_run_instr_no_data1(arm11, 0xe4c01001); - } + }} + break; + } case 2: { @@ -1153,14 +1184,16 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count u16 * buf16 = (u16*)buffer; - while (count--) + {size_t i; + for (i = 0; i < count; i++) { /* MRC p14,0,r1,c0,c5,0 */ arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++); /* strh r1, [r0], #2 */ arm11_run_instr_no_data1(arm11, 0xe0c010b2); - } + }} + break; } @@ -1191,10 +1224,10 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count if (address + size * count != r0) { - ERROR("Data transfer failed. (%d)", (r0 - address) - size * count); + LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count); if (arm11_config_memwrite_burst) - ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); + LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode"); if (arm11_config_memwrite_error_fatal) exit(-1); @@ -1217,6 +1250,12 @@ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 { FNC_INFO; + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } + return arm11_write_memory(target, address, 4, count, buffer); } @@ -1241,20 +1280,20 @@ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) #if 0 if (breakpoint->type == BKPT_SOFT) { - INFO("sw breakpoint requested, but software breakpoints not enabled"); + LOG_INFO("sw breakpoint requested, but software breakpoints not enabled"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } #endif if (!arm11->free_brps) { - INFO("no breakpoint unit available for hardware breakpoint"); + LOG_INFO("no breakpoint unit available for hardware breakpoint"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } if (breakpoint->length != 4) { - INFO("only breakpoints of four bytes length supported"); + LOG_INFO("only breakpoints of four bytes length supported"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } @@ -1303,7 +1342,7 @@ int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **ar if (argc < 4) { - ERROR("'target arm11' 4th argument "); + LOG_ERROR("'target arm11' 4th argument "); exit(-1); } @@ -1323,7 +1362,7 @@ int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **ar if (device->ir_length != 5) { - ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'"); + LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'"); exit(-1); } @@ -1333,6 +1372,13 @@ int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **ar } int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +{ + /* Initialize anything we can set up without talking to the target */ + return ERROR_OK; +} + +/* talk to the target and set things up */ +int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target) { FNC_INFO; @@ -1366,12 +1412,12 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target switch (arm11->device_id & 0x0FFFF000) { - case 0x07B36000: INFO("found ARM1136"); break; - case 0x07B56000: INFO("found ARM1156"); break; - case 0x07B76000: INFO("found ARM1176"); break; + case 0x07B36000: LOG_INFO("found ARM1136"); break; + case 0x07B56000: LOG_INFO("found ARM1156"); break; + case 0x07B76000: LOG_INFO("found ARM1176"); break; default: { - ERROR("'target arm11' expects IDCODE 0x*7B*7****"); + LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****"); exit(-1); } } @@ -1381,7 +1427,7 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target if (arm11->debug_version != ARM11_DEBUG_V6 && arm11->debug_version != ARM11_DEBUG_V61) { - ERROR("Only ARMv6 v6 and v6.1 architectures supported."); + LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported."); exit(-1); } @@ -1393,7 +1439,7 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target arm11->free_brps = arm11->brp; arm11->free_wrps = arm11->wrp; - DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x", + LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x", arm11->device_id, arm11->implementor, arm11->didr); @@ -1427,6 +1473,7 @@ int arm11_get_reg(reg_t *reg) if (target->state != TARGET_HALTED) { + LOG_WARNING("target was not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1489,7 +1536,7 @@ void arm11_build_reg_cache(target_t *target) ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) || ARM11_REGCACHE_COUNT != ARM11_RC_MAX) { - ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); + LOG_ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); exit(-1); } @@ -1516,11 +1563,11 @@ void arm11_build_reg_cache(target_t *target) -int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, int * var, char * name) +int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name) { if (argc == 0) { - INFO("%s is %s.", name, *var ? "enabled" : "disabled"); + LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled"); return ERROR_OK; } @@ -1534,7 +1581,7 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, case 'F': case 'd': /* disable */ case 'D': - *var = 0; + *var = false; break; case '1': /* 1 */ @@ -1542,11 +1589,11 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, case 'T': case 'e': /* enable */ case 'E': - *var = 1; + *var = true; break; } - INFO("%s %s.", *var ? "Enabled" : "Disabled", name); + LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name); return ERROR_OK; } @@ -1587,10 +1634,133 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, return ERROR_COMMAND_SYNTAX_ERROR; } - INFO("VCR 0x%08X", arm11_vcr); + LOG_INFO("VCR 0x%08X", arm11_vcr); return ERROR_OK; } +const u32 arm11_coproc_instruction_limits[] = +{ + 15, /* coprocessor */ + 7, /* opcode 1 */ + 15, /* CRn */ + 15, /* CRm */ + 7, /* opcode 2 */ + 0xFFFFFFFF, /* value */ +}; + +const char arm11_mrc_syntax[] = "Syntax: mrc . All parameters are numbers only."; +const char arm11_mcr_syntax[] = "Syntax: mcr <32bit value to write>. All parameters are numbers only."; + + +arm11_common_t * arm11_find_target(const char * arg) +{ + size_t jtag_target = strtoul(arg, NULL, 0); + + {target_t * t; + for (t = targets; t; t = t->next) + { + if (t->type != &arm11_target) + continue; + + arm11_common_t * arm11 = t->arch_info; + + if (arm11->jtag_info.chain_pos != jtag_target) + continue; + + return arm11; + }} + + return 0; +} + +int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read) +{ + if (argc != (read ? 6 : 7)) + { + LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax); + return -1; + } + + arm11_common_t * arm11 = arm11_find_target(args[0]); + + if (!arm11) + { + LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s", + read ? arm11_mrc_syntax : arm11_mcr_syntax); + + return -1; + + } + + if (arm11->target->state != TARGET_HALTED) + { + LOG_WARNING("target was not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + + u32 values[6]; + + {size_t i; + for (i = 0; i < (read ? 5 : 6); i++) + { + values[i] = strtoul(args[i + 1], NULL, 0); + + if (values[i] > arm11_coproc_instruction_limits[i]) + { + LOG_ERROR("Parameter %ld out of bounds (%d max). %s", + i + 2, arm11_coproc_instruction_limits[i], + read ? arm11_mrc_syntax : arm11_mcr_syntax); + return -1; + } + }} + + u32 instr = 0xEE000010 | + (values[0] << 8) | + (values[1] << 21) | + (values[2] << 16) | + (values[3] << 0) | + (values[4] << 5); + + if (read) + instr |= 0x00100000; + + + arm11_run_instr_data_prepare(arm11); + + if (read) + { + u32 result; + arm11_run_instr_data_from_core_via_r0(arm11, instr, &result); + + LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)", + values[0], values[1], values[2], values[3], values[4], result, result); + } + else + { + arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]); + + LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d", + values[0], values[1], + values[5], + values[2], values[3], values[4]); + } + + arm11_run_instr_data_finish(arm11); + + + return ERROR_OK; +} + +int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true); +} + +int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false); +} int arm11_register_commands(struct command_context_s *cmd_ctx) { @@ -1612,6 +1782,12 @@ int arm11_register_commands(struct command_context_s *cmd_ctx) RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register", arm11_handle_vcr) + + RC_FINAL( "mrc", "Read Coprocessor register", + arm11_handle_mrc) + + RC_FINAL( "mcr", "Write Coprocessor register", + arm11_handle_mcr) ) return ERROR_OK;