X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=77cc2236d7a6f815e3f965f98ca91570b934df91;hp=6bc1a25133c85cd7f3c8d8a69d2ebf5bb07514e7;hb=651998e33771bdad56873e3e70bd875104ca1d12;hpb=d0dee7ccafcf87259fadf6c5de43df8583b0e885 diff --git a/src/target/arm11.h b/src/target/arm11.h index 6bc1a25133..77cc2236d7 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -15,178 +15,100 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ -#ifndef ARM11_H -#define ARM11_H - -#include "target.h" -#include "register.h" -#include "jtag.h" - -#define asizeof(x) (sizeof(x) / sizeof((x)[0])) - -#define NEW(type, variable, items) \ - type * variable = calloc(1, sizeof(type) * items) - -/* For MinGW use 'I' prefix to print size_t (instead of 'z') */ -/* Except if __USE_MINGW_ANSI_STDIO is defined with MinGW */ - -#if (!defined(__MSVCRT__) || defined(__USE_MINGW_ANSI_STDIO)) -#define ZU "%zu" -#else -#define ZU "%Iu" -#endif - -#define ARM11_REGCACHE_MODEREGS 0 -#define ARM11_REGCACHE_FREGS 0 - -#define ARM11_REGCACHE_COUNT (20 + \ - 23 * ARM11_REGCACHE_MODEREGS + \ - 9 * ARM11_REGCACHE_FREGS) - -#define ARM11_TAP_DEFAULT TAP_INVALID - - -#define CHECK_RETVAL(action) \ -do { \ - int __retval = (action); \ - \ - if (__retval != ERROR_OK) \ - { \ - LOG_DEBUG("error while calling \"" # action "\""); \ - return __retval; \ - } \ - \ -} while (0) - - -struct arm11_register_history -{ - uint32_t value; - uint8_t valid; +#ifndef OPENOCD_TARGET_ARM11_H +#define OPENOCD_TARGET_ARM11_H + +#include "arm.h" +#include "arm_dpm.h" + +#define ARM11_TAP_DEFAULT TAP_INVALID + +#define CHECK_RETVAL(action) \ + do { \ + int __retval = (action); \ + if (__retval != ERROR_OK) { \ + LOG_DEBUG("error while calling \"%s\"", \ + # action); \ + return __retval; \ + } \ + } while (0) + +/* bits from ARMv7 DIDR */ +enum arm11_debug_version { + ARM11_DEBUG_V6 = 0x01, + ARM11_DEBUG_V61 = 0x02, + ARM11_DEBUG_V7 = 0x03, + ARM11_DEBUG_V7_CP14 = 0x04, }; -enum arm11_debug_version -{ - ARM11_DEBUG_V6 = 0x01, - ARM11_DEBUG_V61 = 0x02, - ARM11_DEBUG_V7 = 0x03, - ARM11_DEBUG_V7_CP14 = 0x04, -}; - -struct arm11_common -{ - target_t * target; /**< Reference back to the owner */ - - /** \name Processor type detection */ - /*@{*/ +struct arm11_common { + struct arm arm; - uint32_t device_id; /**< IDCODE readout */ - uint32_t didr; /**< DIDR readout (debug capabilities) */ - uint8_t implementor; /**< DIDR Implementor readout */ + /** Debug module state. */ + struct arm_dpm dpm; + struct arm11_sc7_action *bpwp_actions; + unsigned bpwp_n; - size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ - size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */ + size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */ + size_t free_brps; /**< Number of breakpoints allocated */ - enum arm11_debug_version - debug_version; /**< ARM debug architecture from DIDR */ - /*@}*/ + uint32_t dscr; /**< Last retrieved DSCR value. */ - uint32_t last_dscr; /**< Last retrieved DSCR value; - Use only for debug message generation */ + uint32_t saved_rdtr; + uint32_t saved_wdtr; - bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */ + bool is_rdtr_saved; + bool is_wdtr_saved; - /** \name Shadow registers to save processor state */ - /*@{*/ + bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt **/ - struct reg * reg_list; /**< target register list */ - uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */ + /* Per-core configurable options. + * NOTE that several of these boolean options should not exist + * once the relevant code is known to work correctly. + */ + bool memwrite_burst; + bool memwrite_error_fatal; + bool step_irq_enable; + bool hardware_step; - /*@}*/ + /** Configured Vector Catch Register settings. */ + uint32_t vcr; - struct arm11_register_history - reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */ - - size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */ - size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */ - - // GA - struct reg_cache *core_cache; + struct arm_jtag jtag_info; }; +static inline struct arm11_common *target_to_arm11(struct target *target) +{ + return container_of(target->arch_info, struct arm11_common, arm); +} /** * ARM11 DBGTAP instructions * * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html */ -enum arm11_instructions -{ +enum arm11_instructions { ARM11_EXTEST = 0x00, ARM11_SCAN_N = 0x02, ARM11_RESTART = 0x04, - ARM11_HALT = 0x08, + ARM11_HALT = 0x08, ARM11_INTEST = 0x0C, ARM11_ITRSEL = 0x1D, ARM11_IDCODE = 0x1E, ARM11_BYPASS = 0x1F, }; -enum arm11_dscr -{ - ARM11_DSCR_CORE_HALTED = 1 << 0, - ARM11_DSCR_CORE_RESTARTED = 1 << 1, - - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2, - ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2, - - ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6, - ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7, - ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11, - ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13, - ARM11_DSCR_MODE_SELECT = 1 << 14, - ARM11_DSCR_WDTR_FULL = 1 << 29, - ARM11_DSCR_RDTR_FULL = 1 << 30, -}; - -enum arm11_cpsr -{ - ARM11_CPSR_T = 1 << 5, - ARM11_CPSR_J = 1 << 24, -}; - -enum arm11_sc7 -{ - ARM11_SC7_NULL = 0, - ARM11_SC7_VCR = 7, - ARM11_SC7_PC = 8, - ARM11_SC7_BVR0 = 64, - ARM11_SC7_BCR0 = 80, - ARM11_SC7_WVR0 = 96, - ARM11_SC7_WCR0 = 112, -}; - -struct arm11_reg_state -{ - uint32_t def_index; - target_t * target; +enum arm11_sc7 { + ARM11_SC7_NULL = 0, + ARM11_SC7_VCR = 7, + ARM11_SC7_PC = 8, + ARM11_SC7_BVR0 = 64, + ARM11_SC7_BCR0 = 80, + ARM11_SC7_WVR0 = 96, + ARM11_SC7_WCR0 = 112, }; -int arm11_register_commands(struct command_context_s *cmd_ctx); - -int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t *value); -int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value); - - - -#endif /* ARM11_H */ +#endif /* OPENOCD_TARGET_ARM11_H */