X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11.h;h=d9e45357e1d091c576a73c2e84f166f1d7df19f8;hp=f3f0644b08b90af0569ea94f078baf0cdd99e3d8;hb=677b02b475870b7d9e5d86e9bf61dc28dae5a6e4;hpb=ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc

diff --git a/src/target/arm11.h b/src/target/arm11.h
index f3f0644b08..d9e45357e1 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -17,46 +17,45 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifndef ARM11_H
 #define ARM11_H
 
-#include <target/armv4_5.h>
-#include <target/arm_dpm.h>
+#include "arm.h"
+#include "arm_dpm.h"
 
-#define ARM11_TAP_DEFAULT			TAP_INVALID
+#define ARM11_TAP_DEFAULT                       TAP_INVALID
 
 #define CHECK_RETVAL(action)			\
 	do {					\
 		int __retval = (action);	\
 		if (__retval != ERROR_OK) {	\
 			LOG_DEBUG("error while calling \"%s\"",	\
-				# action );	\
+				# action);     \
 			return __retval;	\
 		}				\
 	} while (0)
 
 /* bits from ARMv7 DIDR */
-enum arm11_debug_version
-{
-	ARM11_DEBUG_V6			= 0x01,
-	ARM11_DEBUG_V61			= 0x02,
-	ARM11_DEBUG_V7			= 0x03,
-	ARM11_DEBUG_V7_CP14		= 0x04,
+enum arm11_debug_version {
+	ARM11_DEBUG_V6                  = 0x01,
+	ARM11_DEBUG_V61                 = 0x02,
+	ARM11_DEBUG_V7                  = 0x03,
+	ARM11_DEBUG_V7_CP14             = 0x04,
 };
 
-struct arm11_common
-{
-	struct arm	arm;
+struct arm11_common {
+	struct arm arm;
 
 	/** Debug module state. */
 	struct arm_dpm dpm;
+	struct arm11_sc7_action *bpwp_actions;
+	unsigned bpwp_n;
 
-	size_t	brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
-	size_t	wrp;			/**< Number of Watchpoint Register Pairs from DIDR	*/
-	size_t	free_brps;		/**< Number of breakpoints allocated */
+	size_t brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
+	size_t free_brps;		/**< Number of breakpoints allocated */
 
 	uint32_t dscr;			/**< Last retrieved DSCR value. */
 
@@ -66,15 +65,26 @@ struct arm11_common
 	bool is_rdtr_saved;
 	bool is_wdtr_saved;
 
-	bool	simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt */
+	bool simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt **/
+
+	/* Per-core configurable options.
+	 * NOTE that several of these boolean options should not exist
+	 * once the relevant code is known to work correctly.
+	 */
+	bool memwrite_burst;
+	bool memwrite_error_fatal;
+	bool step_irq_enable;
+	bool hardware_step;
+
+	/** Configured Vector Catch Register settings. */
+	uint32_t vcr;
 
 	struct arm_jtag jtag_info;
 };
 
 static inline struct arm11_common *target_to_arm11(struct target *target)
 {
-	return container_of(target->arch_info, struct arm11_common,
-			arm);
+	return container_of(target->arch_info, struct arm11_common, arm);
 }
 
 /**
@@ -82,27 +92,25 @@ static inline struct arm11_common *target_to_arm11(struct target *target)
  *
  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  */
-enum arm11_instructions
-{
+enum arm11_instructions {
 	ARM11_EXTEST    = 0x00,
 	ARM11_SCAN_N    = 0x02,
 	ARM11_RESTART   = 0x04,
-	ARM11_HALT	    = 0x08,
+	ARM11_HALT          = 0x08,
 	ARM11_INTEST    = 0x0C,
 	ARM11_ITRSEL    = 0x1D,
 	ARM11_IDCODE    = 0x1E,
 	ARM11_BYPASS    = 0x1F,
 };
 
-enum arm11_sc7
-{
-	ARM11_SC7_NULL				= 0,
-	ARM11_SC7_VCR				= 7,
-	ARM11_SC7_PC				= 8,
-	ARM11_SC7_BVR0				= 64,
-	ARM11_SC7_BCR0				= 80,
-	ARM11_SC7_WVR0				= 96,
-	ARM11_SC7_WCR0				= 112,
+enum arm11_sc7 {
+	ARM11_SC7_NULL                          = 0,
+	ARM11_SC7_VCR                           = 7,
+	ARM11_SC7_PC                            = 8,
+	ARM11_SC7_BVR0                          = 64,
+	ARM11_SC7_BCR0                          = 80,
+	ARM11_SC7_WVR0                          = 96,
+	ARM11_SC7_WCR0                          = 112,
 };
 
-#endif /* ARM11_H */
+#endif	/* ARM11_H */