X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=26de4ceb2f8bdd7da36d664f2cfb74667697a296;hp=9cc8ad03c8f0e6e830078ffc44f7884c037b38e2;hb=5985dee35da3ea24f1c9cb30b6cd50aa1bc63660;hpb=23de60e6bd44ae60bf0e0a2c2cad9f4721018fa6 diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 9cc8ad03c8..26de4ceb2f 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -1,7 +1,8 @@ /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * + * Michael Bruck * * * - * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -23,69 +24,68 @@ #include "config.h" #endif -#include "arm11.h" -#include "jtag.h" -#include "log.h" +#include "arm_jtag.h" +#include "arm11_dbgtap.h" -#include -#include +#include "time_support.h" #if 0 #define JTAG_DEBUG(expr ...) DEBUG(expr) #else -#define JTAG_DEBUG(expr ...) do {} while(0) +#define JTAG_DEBUG(expr ...) do {} while (0) #endif -tap_state_t arm11_move_pi_to_si_via_ci[] = +/* +This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The +behavior of the FTDI driver IIRC was to go via RTI. + +Conversely there may be other places in this code where the ARM11 code relies +on the driver to hit through RTI when coming from Update-?R. +*/ +static const tap_state_t arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; -int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state) +int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_IRPAUSE) - jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); jtag_add_ir_scan(num_fields, fields, state); return ERROR_OK; } -tap_state_t arm11_move_pd_to_sd_via_cd[] = +static const tap_state_t arm11_move_pd_to_sd_via_cd[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; -int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state) +int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_DRPAUSE) - jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); + jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); jtag_add_dr_scan(num_fields, fields, state); return ERROR_OK; } -/** Code de-clutter: Construct scan_field_t to write out a value +/** Code de-clutter: Construct struct scan_field to write out a value * * \param arm11 Target state variable. * \param num_bits Length of the data field * \param out_data pointer to the data that will be sent out - * (data is read when it is added to the JTAG queue) + * (data is read when it is added to the JTAG queue) * \param in_data pointer to the memory that will receive data that was clocked in - * (data is written when the JTAG queue is executed) + * (data is written when the JTAG queue is executed) * \param field target data structure that will be initialized */ -void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field) +void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field) { - field->tap = arm11->jtag_info.tap; + field->tap = arm11->target->tap; field->num_bits = num_bits; - field->out_mask = NULL; - field->in_check_mask = NULL; - field->in_check_value = NULL; - field->in_handler = NULL; - field->in_handler_priv = NULL; - field->out_value = out_data; field->in_value = in_data; } @@ -99,10 +99,10 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) +void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) { - jtag_tap_t *tap; - tap = arm11->jtag_info.tap; + struct jtag_tap *tap; + tap = arm11->target->tap; if (buf_get_u32(tap->cur_instr, 0, 5) == instr) { @@ -112,7 +112,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) JTAG_DEBUG("IR <= 0x%02x", instr); - scan_field_t field; + struct scan_field field; arm11_setup_field(arm11, 5, &instr, NULL, &field); @@ -120,23 +120,22 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state) } /** Verify shifted out data from Scan Chain Register (SCREG) - * Used as parameter to scan_field_t::in_handler in + * Used as parameter to struct scan_field::in_handler in * arm11_add_debug_SCAN_N(). * */ -static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field) +static void arm11_in_handler_SCAN_N(uint8_t *in_value) { - /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */ - u8 v = *in_value & 0x1F; + /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */ + uint8_t v = *in_value & 0x1F; if (v != 0x10) { LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - return ERROR_FAIL; + jtag_set_error(ERROR_FAIL); } JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); - return ERROR_OK; } /** Select and write to Scan Chain Register (SCREG) @@ -163,19 +162,26 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) +int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state) { JTAG_DEBUG("SCREG <= 0x%02x", chain); arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); - scan_field_t field; - - arm11_setup_field(arm11, 5, &chain, NULL, &field); + struct scan_field field; - field.in_handler = arm11_in_handler_SCAN_N; + uint8_t tmp[1]; + arm11_setup_field(arm11, 5, &chain, &tmp, &field); arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); + + jtag_execute_queue_noclear(); + + arm11_in_handler_SCAN_N(tmp); + + arm11->jtag_info.cur_scan_chain = chain; + + return jtag_execute_queue(); } /** Write an instruction into the ITR register @@ -195,16 +201,16 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state) * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state) +void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state) { JTAG_DEBUG("INST <= 0x%08x", inst); - scan_field_t itr[2]; + struct scan_field itr[2]; arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state); + arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state); } /** Read the Debug Status and Control Register (DSCR) @@ -212,31 +218,37 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state * same as CP14 c1 * * \param arm11 Target state variable. - * \return DSCR content + * \param value DSCR content + * \return Error status * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -u32 arm11_read_DSCR(arm11_common_t * arm11) +int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value) { - arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - u32 dscr; - scan_field_t chain1_field; + uint32_t dscr; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); if (arm11->last_dscr != dscr) JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); arm11->last_dscr = dscr; - return dscr; + *value = dscr; + + return ERROR_OK; } /** Write the Debug Status and Control Register (DSCR) @@ -248,23 +260,28 @@ u32 arm11_read_DSCR(arm11_common_t * arm11) * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) +int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) { - arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain1_field; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); arm11->last_dscr = dscr; + + return ERROR_OK; } @@ -275,7 +292,7 @@ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) * \return Debug reason * */ -enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) +enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr) { switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK) { @@ -325,9 +342,9 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) * \param arm11 Target state variable. * */ -void arm11_run_instr_data_prepare(arm11_common_t * arm11) +int arm11_run_instr_data_prepare(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); + return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); } /** Cleanup after ITR/DTR operations @@ -344,12 +361,13 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11) * \param arm11 Target state variable. * */ -void arm11_run_instr_data_finish(arm11_common_t * arm11) +int arm11_run_instr_data_finish(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); + return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); } + /** Execute one or multiple instructions via ITR * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block @@ -359,7 +377,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11) * \param count Number of opcodes to execute * */ -void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) +int arm11_run_instr_no_data(struct arm11_common * arm11, uint32_t * opcode, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -367,18 +385,38 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) { arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE); + int i = 0; while (1) { - u8 flag; + uint8_t flag; arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); if (flag) break; + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -389,9 +427,9 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) * \param opcode ARM opcode * */ -void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) +int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) { - arm11_run_instr_no_data(arm11, &opcode, 1); + return arm11_run_instr_no_data(arm11, &opcode, 1); } @@ -408,7 +446,7 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -416,11 +454,11 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u32 Data; - u8 Ready; - u8 nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); @@ -428,14 +466,33 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data while (count--) { + int i = 0; do { Data = *data; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } while (!Ready); @@ -444,16 +501,37 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + int i = 0; do { Data = 0; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } while (!Ready); + + return ERROR_OK; } /** JTAG path for arm11_run_instr_data_to_core_noack @@ -466,8 +544,14 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * + * To disable this code, try "memwrite burst false" + * + * FIX!!! should we use multiple TAP_IDLE here or not??? + * + * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html + * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = +static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -489,7 +573,7 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -497,14 +581,24 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - u8 Readies[count + 1]; - u8 * ReadyPos = Readies; + uint8_t *Readies; + unsigned readiesNum = count + 1; + unsigned bytes = sizeof(*Readies)*readiesNum; + + Readies = (uint8_t *) malloc(bytes); + if (Readies == NULL) + { + LOG_ERROR("Out of memory allocating %u bytes", bytes); + return ERROR_FAIL; + } + + uint8_t * ReadyPos = Readies; while (count--) { @@ -513,13 +607,13 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 if (count) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), + jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE)); + jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); } else { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE); + jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); } } @@ -528,23 +622,30 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 chain5_fields[0].out_value = 0; chain5_fields[1].in_value = ReadyPos++; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE); - size_t error_count = 0; - - {size_t i; - for (i = 0; i < asizeof(Readies); i++) + int retval = jtag_execute_queue(); + if (retval == ERROR_OK) { - if (Readies[i] != 1) + unsigned error_count = 0; + + for (size_t i = 0; i < readiesNum; i++) { - error_count++; + if (Readies[i] != 1) + { + error_count++; + } } - }} - if (error_count) - LOG_ERROR("Transfer errors " ZU, error_count); + if (error_count > 0 ) + LOG_ERROR("%u words out of %u not transferred", + error_count, readiesNum); + + } + + free(Readies); + + return retval; } @@ -559,9 +660,9 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * \param data Data word to be passed to the core via DTR * */ -void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { - arm11_run_instr_data_to_core(arm11, opcode, &data, 1); + return arm11_run_instr_data_to_core(arm11, opcode, &data, 1); } @@ -578,7 +679,7 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -586,11 +687,11 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u32 Data; - u8 Ready; - u8 nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); @@ -598,17 +699,38 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da while (count--) { + int i = 0; do { - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; } while (!Ready); *data++ = Data; } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -623,12 +745,17 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed. * */ -void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data) +int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data) { - arm11_run_instr_no_data1(arm11, opcode); + int retval; + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */ arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1); + + return ERROR_OK; } /** Load data into core via DTR then move it to r0 then @@ -643,44 +770,54 @@ void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u * \param data Data word that will be written to r0 before \p opcode is executed * */ -void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { + int retval; /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + if (retval != ERROR_OK) + return retval; + + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; - arm11_run_instr_no_data1(arm11, opcode); + return ERROR_OK; } /** Apply reads and writes to scan chain 7 * - * \see arm11_sc7_action_t + * \see struct arm11_sc7_action * * \param arm11 Target state variable. * \param actions A list of read and/or write instructions * \param count Number of instructions in the list. * */ -void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) +int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions, size_t count) { - arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + int retval; + + retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain7_fields[3]; + struct scan_field chain7_fields[3]; - u8 nRW; - u32 DataOut; - u8 AddressOut; - u8 Ready; - u32 DataIn; - u8 AddressIn; + uint8_t nRW; + uint32_t DataOut; + uint8_t AddressOut; + uint8_t Ready; + uint32_t DataIn; + uint8_t AddressIn; arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); - {size_t i; - for (i = 0; i < count + 1; i++) + for (size_t i = 0; i < count + 1; i++) { if (i < count) { @@ -699,8 +836,9 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t { JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); - arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); - jtag_execute_queue(); + arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields), chain7_fields, TAP_DRPAUSE); + + CHECK_RETVAL(jtag_execute_queue()); JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); } @@ -725,13 +863,14 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t } } } - }} + } - {size_t i; - for (i = 0; i < count; i++) + for (size_t i = 0; i < count; i++) { JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value); - }} + } + + return ERROR_OK; } /** Clear VCR and all breakpoints and watchpoints via scan chain 7 @@ -739,31 +878,31 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t * \param arm11 Target state variable. * */ -void arm11_sc7_clear_vbw(arm11_common_t * arm11) +void arm11_sc7_clear_vbw(struct arm11_common * arm11) { - arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; - arm11_sc7_action_t * pos = clear_bw; + size_t clear_bw_size = arm11->brp + arm11->wrp + 1; + struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size); + struct arm11_sc7_action * pos = clear_bw; - {size_t i; - for (i = 0; i < asizeof(clear_bw); i++) + for (size_t i = 0; i < clear_bw_size; i++) { clear_bw[i].write = true; clear_bw[i].value = 0; - }} + } - {size_t i; - for (i = 0; i < arm11->brp; i++) + for (size_t i = 0; i < arm11->brp; i++) (pos++)->address = ARM11_SC7_BCR0 + i; - } - {size_t i; - for (i = 0; i < arm11->wrp; i++) + + for (size_t i = 0; i < arm11->wrp; i++) (pos++)->address = ARM11_SC7_WCR0 + i; - } + (pos++)->address = ARM11_SC7_VCR; - arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw)); + arm11_sc7_run(arm11, clear_bw, clear_bw_size); + + free (clear_bw); } /** Write VCR register @@ -771,9 +910,9 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) * \param arm11 Target state variable. * \param value Value to be written */ -void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) +void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value) { - arm11_sc7_action_t set_vcr; + struct arm11_sc7_action set_vcr; set_vcr.write = true; set_vcr.address = ARM11_SC7_VCR; @@ -792,17 +931,19 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) * \param result Pointer where to store result * */ -void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) +int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result) { - arm11_run_instr_data_prepare(arm11); + int retval; + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ - arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1); + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); - arm11_run_instr_data_finish(arm11); + return arm11_run_instr_data_finish(arm11); } -