X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=f9582381f53ca0c5224276d869b96edae25f2f8c;hp=7e5bd847d18bf31d6329f2e06c3e1f44e5c331d0;hb=55926f576f99a0c67b2836fedf0dc1bfc1260428;hpb=69b8b5e0aa7f3d5fec39bd74d277546f290ed5cd diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 7e5bd847d1..f9582381f5 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -24,7 +24,7 @@ #include "config.h" #endif -#include "arm11.h" +#include "arm11_dbgtap.h" #include "time_support.h" @@ -41,13 +41,13 @@ behavior of the FTDI driver IIRC was to go via RTI. Conversely there may be other places in this code where the ARM11 code relies on the driver to hit through RTI when coming from Update-?R. */ -tap_state_t arm11_move_pi_to_si_via_ci[] = +static const tap_state_t arm11_move_pi_to_si_via_ci[] = { TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; -int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state) +int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_IRPAUSE) jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); @@ -56,12 +56,12 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state return ERROR_OK; } -tap_state_t arm11_move_pd_to_sd_via_cd[] = +static const tap_state_t arm11_move_pd_to_sd_via_cd[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; -int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state) +int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_DRPAUSE) jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); @@ -71,7 +71,7 @@ int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state } -/** Code de-clutter: Construct scan_field_t to write out a value +/** Code de-clutter: Construct struct scan_field to write out a value * * \param arm11 Target state variable. * \param num_bits Length of the data field @@ -81,7 +81,7 @@ int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state * (data is written when the JTAG queue is executed) * \param field target data structure that will be initialized */ -void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field) +void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field) { field->tap = arm11->target->tap; field->num_bits = num_bits; @@ -98,9 +98,9 @@ void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, vo * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state) +void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) { - jtag_tap_t *tap; + struct jtag_tap *tap; tap = arm11->target->tap; if (buf_get_u32(tap->cur_instr, 0, 5) == instr) @@ -111,7 +111,7 @@ void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state) JTAG_DEBUG("IR <= 0x%02x", instr); - scan_field_t field; + struct scan_field field; arm11_setup_field(arm11, 5, &instr, NULL, &field); @@ -119,7 +119,7 @@ void arm11_add_IR(arm11_common_t * arm11, uint8_t instr, tap_state_t state) } /** Verify shifted out data from Scan Chain Register (SCREG) - * Used as parameter to scan_field_t::in_handler in + * Used as parameter to struct scan_field::in_handler in * arm11_add_debug_SCAN_N(). * */ @@ -161,13 +161,13 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value) * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t state) +int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state) { JTAG_DEBUG("SCREG <= 0x%02x", chain); arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); - scan_field_t field; + struct scan_field field; uint8_t tmp[1]; arm11_setup_field(arm11, 5, &chain, &tmp, &field); @@ -177,6 +177,8 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t s jtag_execute_queue_noclear(); arm11_in_handler_SCAN_N(tmp); + + return jtag_execute_queue(); } /** Write an instruction into the ITR register @@ -196,11 +198,11 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, uint8_t chain, tap_state_t s * * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, tap_state_t state) +void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state) { JTAG_DEBUG("INST <= 0x%08x", inst); - scan_field_t itr[2]; + struct scan_field itr[2]; arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); @@ -218,14 +220,17 @@ void arm11_add_debug_INST(arm11_common_t * arm11, uint32_t inst, uint8_t * flag, * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value) +int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value) { - arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); uint32_t dscr; - scan_field_t chain1_field; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); @@ -252,13 +257,16 @@ int arm11_read_DSCR(arm11_common_t * arm11, uint32_t *value) * * \remarks This is a stand-alone function that executes the JTAG command queue. */ -int arm11_write_DSCR(arm11_common_t * arm11, uint32_t dscr) +int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) { - arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain1_field; + struct scan_field chain1_field; arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); @@ -331,9 +339,9 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr) * \param arm11 Target state variable. * */ -void arm11_run_instr_data_prepare(arm11_common_t * arm11) +int arm11_run_instr_data_prepare(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); + return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); } /** Cleanup after ITR/DTR operations @@ -350,9 +358,9 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11) * \param arm11 Target state variable. * */ -void arm11_run_instr_data_finish(arm11_common_t * arm11) +int arm11_run_instr_data_finish(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); + return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); } @@ -366,7 +374,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11) * \param count Number of opcodes to execute * */ -int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t count) +int arm11_run_instr_no_data(struct arm11_common * arm11, uint32_t * opcode, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -416,7 +424,7 @@ int arm11_run_instr_no_data(arm11_common_t * arm11, uint32_t * opcode, size_t co * \param opcode ARM opcode * */ -int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode) +int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) { return arm11_run_instr_no_data(arm11, &opcode, 1); } @@ -435,7 +443,7 @@ int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode) * \param count Number of data words and instruction repetitions * */ -int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -443,7 +451,7 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; uint32_t Data; uint8_t Ready; @@ -540,7 +548,7 @@ int arm11_run_instr_data_to_core(arm11_common_t * arm11, uint32_t opcode, uint32 * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = +static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -562,7 +570,7 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = * \param count Number of data words and instruction repetitions * */ -int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -570,13 +578,22 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0); arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - uint8_t Readies[count + 1]; + uint8_t *Readies; + size_t readiesNum = (count + 1); + size_t bytes = sizeof(*Readies)*readiesNum; + Readies = (uint8_t *) malloc(bytes); + if (Readies == NULL) + { + LOG_ERROR("Out of memory allocating " ZU " bytes", bytes); + return ERROR_FAIL; + } + uint8_t * ReadyPos = Readies; while (count--) @@ -603,22 +620,27 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - CHECK_RETVAL(jtag_execute_queue()); - - size_t error_count = 0; - - for (size_t i = 0; i < asizeof(Readies); i++) + int retval = jtag_execute_queue(); + if (retval == ERROR_OK) { - if (Readies[i] != 1) + size_t error_count = 0; + + for (size_t i = 0; i < readiesNum; i++) { - error_count++; + if (Readies[i] != 1) + { + error_count++; + } } + + if (error_count > 0 ) + LOG_ERROR(ZU " words out of " ZU " not transferred", error_count, readiesNum); + } - if (error_count) - LOG_ERROR("Transfer errors " ZU, error_count); + free(Readies); - return ERROR_OK; + return retval; } @@ -633,7 +655,7 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode, * \param data Data word to be passed to the core via DTR * */ -int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint32_t data) +int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { return arm11_run_instr_data_to_core(arm11, opcode, &data, 1); } @@ -652,7 +674,7 @@ int arm11_run_instr_data_to_core1(arm11_common_t * arm11, uint32_t opcode, uint3 * \param count Number of data words and instruction repetitions * */ -int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count) +int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); @@ -660,7 +682,7 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; uint32_t Data; uint8_t Ready; @@ -718,7 +740,7 @@ int arm11_run_instr_data_from_core(arm11_common_t * arm11, uint32_t opcode, uint * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed. * */ -int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data) +int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data) { int retval; retval = arm11_run_instr_no_data1(arm11, opcode); @@ -743,12 +765,19 @@ int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcod * \param data Data word that will be written to r0 before \p opcode is executed * */ -void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t data) +int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { + int retval; /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + if (retval != ERROR_OK) + return retval; + + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; - arm11_run_instr_no_data1(arm11, opcode); + return ERROR_OK; } /** Apply reads and writes to scan chain 7 @@ -760,13 +789,17 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, uint32_t opcode * \param count Number of instructions in the list. * */ -int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) +int arm11_sc7_run(struct arm11_common * arm11, arm11_sc7_action_t * actions, size_t count) { - arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + int retval; + + retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain7_fields[3]; + struct scan_field chain7_fields[3]; uint8_t nRW; uint32_t DataOut; @@ -840,7 +873,7 @@ int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t c * \param arm11 Target state variable. * */ -void arm11_sc7_clear_vbw(arm11_common_t * arm11) +void arm11_sc7_clear_vbw(struct arm11_common * arm11) { arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; arm11_sc7_action_t * pos = clear_bw; @@ -869,7 +902,7 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) * \param arm11 Target state variable. * \param value Value to be written */ -void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value) +void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value) { arm11_sc7_action_t set_vcr; @@ -890,9 +923,12 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value) * \param result Pointer where to store result * */ -int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result) +int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result) { - arm11_run_instr_data_prepare(arm11); + int retval; + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); @@ -900,9 +936,83 @@ int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); - arm11_run_instr_data_finish(arm11); + return arm11_run_instr_data_finish(arm11); +} + + +/** Write Embedded Trace Macrocell (ETM) via Scan chain 6 + * + * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe + * + * \param arm11 Target state variable. + * \param address 7 bit ETM register address + * \param value Value to be written + * + * \return Error status + * + * \remarks This is a stand-alone function that executes the JTAG command queue. + */ +int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value) +{ + CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT)); + + /* Uses INTEST for read and write */ + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + + struct scan_field chain6_fields[3]; + + uint8_t nRW = 1; + + arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0); + arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1); + arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2); + + arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE); + + CHECK_RETVAL(jtag_execute_queue()); return ERROR_OK; } +/** Read Embedded Trace Macrocell (ETM) via Scan chain 6 + * + * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe + * + * \param arm11 Target state variable. + * \param address 7 bit ETM register address + * \param value Pointer that receives value that was read + * + * \return Error status + * + * \remarks This is a stand-alone function that executes the JTAG command queue. + */ +int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t * value) +{ + CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT)); + + /* Uses INTEST for read and write */ + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + + struct scan_field chain6_fields[3]; + + uint8_t nRW = 0; + + arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0); + arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1); + arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2); + + arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE); + + /* Data is made available in Capture-DR and shifted out on the next access */ + + arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0); + arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1); + arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2); + + arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE); + + CHECK_RETVAL(jtag_execute_queue()); + + return ERROR_OK; +}