X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm11_dbgtap.c;h=f9582381f53ca0c5224276d869b96edae25f2f8c;hp=97ec2fba0e207b11b7659df70435102323516e54;hb=55926f576f99a0c67b2836fedf0dc1bfc1260428;hpb=da767f48da13464b6bd03b08270b529273c995f4 diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 97ec2fba0e..f9582381f5 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -1,5 +1,8 @@ /*************************************************************************** * Copyright (C) 2008 digenius technology GmbH. * + * Michael Bruck * + * * + * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -21,125 +24,121 @@ #include "config.h" #endif -#include "arm11.h" -#include "jtag.h" -#include "log.h" +#include "arm11_dbgtap.h" -#include -#include +#include "time_support.h" #if 0 -#define JTAG_DEBUG(expr ...) \ - do { \ - log_printf (LOG_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr); \ - } while(0) +#define JTAG_DEBUG(expr ...) DEBUG(expr) #else -#define JTAG_DEBUG(expr ...) \ - do {} while(0) +#define JTAG_DEBUG(expr ...) do {} while (0) #endif -enum tap_state arm11_move_pi_to_si_via_ci[] = +/* +This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The +behavior of the FTDI driver IIRC was to go via RTI. + +Conversely there may be other places in this code where the ARM11 code relies +on the driver to hit through RTI when coming from Update-?R. +*/ +static const tap_state_t arm11_move_pi_to_si_via_ci[] = { - TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI + TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; -int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state) +int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { - if (cmd_queue_cur_state == TAP_PI) - jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); + if (cmd_queue_cur_state == TAP_IRPAUSE) + jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); - return jtag_add_ir_scan(num_fields, fields, state); + jtag_add_ir_scan(num_fields, fields, state); + return ERROR_OK; } -enum tap_state arm11_move_pd_to_sd_via_cd[] = +static const tap_state_t arm11_move_pd_to_sd_via_cd[] = { - TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD + TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; -int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state) +int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { - if (cmd_queue_cur_state == TAP_PD) - jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); + if (cmd_queue_cur_state == TAP_DRPAUSE) + jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); - return jtag_add_dr_scan(num_fields, fields, state); + jtag_add_dr_scan(num_fields, fields, state); + return ERROR_OK; } -/** Code de-clutter: Construct scan_field_t to write out a value +/** Code de-clutter: Construct struct scan_field to write out a value * - * \param arm11 Target state variable. - * \param num_bits Length of the data field - * \param out_data pointer to the data that will be sent out - * (data is read when it is added to the JTAG queue) - * \param in_data pointer to the memory that will receive data that was clocked in - * (data is written when the JTAG queue is executed) - * \param field target data structure that will be initialized + * \param arm11 Target state variable. + * \param num_bits Length of the data field + * \param out_data pointer to the data that will be sent out + * (data is read when it is added to the JTAG queue) + * \param in_data pointer to the memory that will receive data that was clocked in + * (data is written when the JTAG queue is executed) + * \param field target data structure that will be initialized */ -void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field) +void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field) { - field->device = arm11->jtag_info.chain_pos; - field->num_bits = num_bits; - field->out_mask = NULL; - field->in_check_mask = NULL; - field->in_check_value = NULL; - field->in_handler = NULL; - field->in_handler_priv = NULL; - - field->out_value = out_data; - field->in_value = in_data; + field->tap = arm11->target->tap; + field->num_bits = num_bits; + field->out_value = out_data; + field->in_value = in_data; } /** Write JTAG instruction register * - * \param arm11 Target state variable. - * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions. - * \param state Pass the final TAP state or -1 for the default value (Pause-IR). + * \param arm11 Target state variable. + * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions. + * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR). * - * \remarks This adds to the JTAG command queue but does \em not execute it. + * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state) +void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) { - jtag_device_t *device = jtag_get_device(arm11->jtag_info.chain_pos); + struct jtag_tap *tap; + tap = arm11->target->tap; - if (buf_get_u32(device->cur_instr, 0, 5) == instr) - { - JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr); - return; - } + if (buf_get_u32(tap->cur_instr, 0, 5) == instr) + { + JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr); + return; + } - JTAG_DEBUG("IR <= 0x%02x", instr); + JTAG_DEBUG("IR <= 0x%02x", instr); - scan_field_t field; + struct scan_field field; - arm11_setup_field(arm11, 5, &instr, NULL, &field); + arm11_setup_field(arm11, 5, &instr, NULL, &field); - arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state); + arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state); } /** Verify shifted out data from Scan Chain Register (SCREG) - * Used as parameter to scan_field_t::in_handler in + * Used as parameter to struct scan_field::in_handler in * arm11_add_debug_SCAN_N(). * */ -static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field) +static void arm11_in_handler_SCAN_N(uint8_t *in_value) { - /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */ - u8 v = *in_value & 0x1F; + /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */ + uint8_t v = *in_value & 0x1F; - if (v != 0x10) - { - ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - exit(-1); - } + if (v != 0x10) + { + LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); + jtag_set_error(ERROR_FAIL); + } - JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); - return ERROR_OK; + JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); } /** Select and write to Scan Chain Register (SCREG) - * + * * This function sets the instruction register to SCAN_N and writes * the data register with the selected chain number. * @@ -147,147 +146,181 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s * * \param arm11 Target state variable. * \param chain Scan chain that will be selected. - * \param state Pass the final TAP state or -1 for the default - * value (Pause-DR). + * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default + * value (Pause-DR). * * The chain takes effect when Update-DR is passed (usually when subsequently * the INTEXT/EXTEST instructions are written). * - * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end - * in Pause-DR. The second call, due to the IR caching, will not - * go through Capture-DR when shifting in the new scan chain number. - * As a result the verification in arm11_in_handler_SCAN_N() must - * fail. + * \warning (Obsolete) Using this twice in a row will \em fail. The first + * call will end in Pause-DR. The second call, due to the IR + * caching, will not go through Capture-DR when shifting in the + * new scan chain number. As a result the verification in + * arm11_in_handler_SCAN_N() must fail. * - * \remarks This adds to the JTAG command queue but does \em not execute it. + * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state state) +int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state) { - JTAG_DEBUG("SCREG <= 0x%02x", chain); + JTAG_DEBUG("SCREG <= 0x%02x", chain); + + arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_SCAN_N, -1); + struct scan_field field; - scan_field_t field; + uint8_t tmp[1]; + arm11_setup_field(arm11, 5, &chain, &tmp, &field); - arm11_setup_field(arm11, 5, &chain, NULL, &field); + arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state); - field.in_handler = arm11_in_handler_SCAN_N; + jtag_execute_queue_noclear(); - arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state); + arm11_in_handler_SCAN_N(tmp); + + return jtag_execute_queue(); } /** Write an instruction into the ITR register - * - * \param arm11 Target state variable. - * \param inst An ARM11 processor instruction/opcode. - * \param flag Optional parameter to retrieve the InstCompl flag - * (this will be written when the JTAG chain is executed). - * \param state Pass the final TAP state or -1 for the default - * value (Run-Test/Idle). - * - * \remarks By default this ends with Run-Test/Idle state - * and causes the instruction to be executed. If - * a subsequent write to DTR is needed before - * executing the instruction then TAP_PD should be - * passed to \p state. - * - * \remarks This adds to the JTAG command queue but does \em not execute it. + * + * \param arm11 Target state variable. + * \param inst An ARM11 processor instruction/opcode. + * \param flag Optional parameter to retrieve the InstCompl flag + * (this will be written when the JTAG chain is executed). + * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default + * value (Run-Test/Idle). + * + * \remarks By default this ends with Run-Test/Idle state + * and causes the instruction to be executed. If + * a subsequent write to DTR is needed before + * executing the instruction then TAP_DRPAUSE should be + * passed to \p state. + * + * \remarks This adds to the JTAG command queue but does \em not execute it. */ -void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state) +void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state) { - JTAG_DEBUG("INST <= 0x%08x", inst); + JTAG_DEBUG("INST <= 0x%08x", inst); - scan_field_t itr[2]; + struct scan_field itr[2]; - arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); - arm11_setup_field(arm11, 1, NULL, flag, itr + 1); + arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); + arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state); + arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state); } /** Read the Debug Status and Control Register (DSCR) * * same as CP14 c1 * - * \param arm11 Target state variable. - * \return DSCR content - * - * \remarks This is a stand-alone function that executes the JTAG command queue. + * \param arm11 Target state variable. + * \param value DSCR content + * \return Error status + * + * \remarks This is a stand-alone function that executes the JTAG command queue. */ -u32 arm11_read_DSCR(arm11_common_t * arm11) +int arm11_read_DSCR(struct arm11_common * arm11, uint32_t *value) { - arm11_add_debug_SCAN_N(arm11, 0x01, -1); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - u32 dscr; - scan_field_t chain1_field; + uint32_t dscr; + struct scan_field chain1_field; - arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); + arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); - arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD); + arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); - if (arm11->last_dscr != dscr) - JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); + if (arm11->last_dscr != dscr) + JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); - arm11->last_dscr = dscr; + arm11->last_dscr = dscr; - return dscr; + *value = dscr; + + return ERROR_OK; } /** Write the Debug Status and Control Register (DSCR) * * same as CP14 c1 * - * \param arm11 Target state variable. - * \param dscr DSCR content - * - * \remarks This is a stand-alone function that executes the JTAG command queue. + * \param arm11 Target state variable. + * \param dscr DSCR content + * + * \remarks This is a stand-alone function that executes the JTAG command queue. */ -void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) +int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr) { - arm11_add_debug_SCAN_N(arm11, 0x01, -1); + int retval; + retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; + + arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + struct scan_field chain1_field; - scan_field_t chain1_field; + arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); - arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); + arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); - arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD); + CHECK_RETVAL(jtag_execute_queue()); - jtag_execute_queue(); + JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); - JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr); + arm11->last_dscr = dscr; - arm11->last_dscr = dscr; + return ERROR_OK; } /** Get the debug reason from Debug Status and Control Register (DSCR) * - * \param dscr DSCR value to analyze - * \return Debug reason - * + * \param dscr DSCR value to analyze + * \return Debug reason + * */ -enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) +enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr) { - switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK) - { - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT: return DBG_REASON_DBGRQ; - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT: return DBG_REASON_BREAKPOINT; - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT: return DBG_REASON_WATCHPOINT; - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION: return DBG_REASON_BREAKPOINT; - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ: return DBG_REASON_DBGRQ; - case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH: return DBG_REASON_BREAKPOINT; - - default: - return DBG_REASON_DBGRQ; - } + switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK) + { + case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT: + LOG_INFO("Debug entry: JTAG HALT"); + return DBG_REASON_DBGRQ; + + case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT: + LOG_INFO("Debug entry: breakpoint"); + return DBG_REASON_BREAKPOINT; + + case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT: + LOG_INFO("Debug entry: watchpoint"); + return DBG_REASON_WATCHPOINT; + + case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION: + LOG_INFO("Debug entry: BKPT instruction"); + return DBG_REASON_BREAKPOINT; + + case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ: + LOG_INFO("Debug entry: EDBGRQ signal"); + return DBG_REASON_DBGRQ; + + case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH: + LOG_INFO("Debug entry: VCR vector catch"); + return DBG_REASON_BREAKPOINT; + + default: + LOG_INFO("Debug entry: unknown"); + return DBG_REASON_DBGRQ; + } }; @@ -303,12 +336,12 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr) * shortcut is used instead of actually changing the Scan_N * register. * - * \param arm11 Target state variable. + * \param arm11 Target state variable. * */ -void arm11_run_instr_data_prepare(arm11_common_t * arm11) +int arm11_run_instr_data_prepare(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x05, -1); + return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT); } /** Cleanup after ITR/DTR operations @@ -317,20 +350,21 @@ void arm11_run_instr_data_prepare(arm11_common_t * arm11) * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish() * around a block of arm11_run_instr_... calls. * - * Any RTI can lead to an instruction execution when + * Any IDLE can lead to an instruction execution when * scan chains 4 or 5 are selected and the IR holds * INTEST or EXTEST. So we must disable that before - * any following activities lead to an RTI. + * any following activities lead to an IDLE. * - * \param arm11 Target state variable. + * \param arm11 Target state variable. * */ -void arm11_run_instr_data_finish(arm11_common_t * arm11) +int arm11_run_instr_data_finish(struct arm11_common * arm11) { - arm11_add_debug_SCAN_N(arm11, 0x00, -1); + return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT); } + /** Execute one or multiple instructions via ITR * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block @@ -340,26 +374,46 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11) * \param count Number of opcodes to execute * */ -void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) +int arm11_run_instr_no_data(struct arm11_common * arm11, uint32_t * opcode, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - while (count--) - { - arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI); - - while (1) + while (count--) { - u8 flag; + arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE); + + int i = 0; + while (1) + { + uint8_t flag; + + arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); + + CHECK_RETVAL(jtag_execute_queue()); + + if (flag) + break; - arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD); + long long then = 0; - jtag_execute_queue(); + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } - if (flag) - break; + i++; + } } - } + + return ERROR_OK; } /** Execute one instruction via ITR @@ -370,9 +424,9 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) * \param opcode ARM opcode * */ -void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) +int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) { - arm11_run_instr_no_data(arm11, &opcode, 1); + return arm11_run_instr_no_data(arm11, &opcode, 1); } @@ -389,68 +443,114 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD); + arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u32 Data; - u8 Ready; - u8 nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; - arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); + arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); - while (count--) - { - do + while (count--) { - Data = *data; + int i = 0; + do + { + Data = *data; + + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI); - jtag_execute_queue(); + CHECK_RETVAL(jtag_execute_queue()); + + JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; + } + while (!Ready); - JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); + data++; } - while (!Ready); - data++; - } + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + + int i = 0; + do + { + Data = 0; + + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - arm11_add_IR(arm11, ARM11_INTEST, -1); + CHECK_RETVAL(jtag_execute_queue()); - do - { - Data = 0; + JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); - jtag_execute_queue(); + long long then = 0; - JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); - } - while (!Ready); + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; + } + while (!Ready); + + return ERROR_OK; } /** JTAG path for arm11_run_instr_data_to_core_noack * - * The repeated TAP_RTI's do not cause a repeated execution + * The repeated TAP_IDLE's do not cause a repeated execution * if passed without leaving the state. * * Since this is more than 7 bits (adjustable via adding more - * TAP_RTI's) it produces an artificial delay in the lower + * TAP_IDLE's) it produces an artificial delay in the lower * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * + * To disable this code, try "memwrite burst false" + * + * FIX!!! should we use multiple TAP_IDLE here or not??? + * + * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html + * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ -enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] = +static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { - TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD + TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -470,62 +570,77 @@ enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] = * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); - - arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD); + arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - arm11_add_IR(arm11, ARM11_EXTEST, -1); + arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); - scan_field_t chain5_fields[3]; + arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); + struct scan_field chain5_fields[3]; - u8 Readies[count + 1]; - u8 * ReadyPos = Readies; + arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - while (count--) - { - chain5_fields[0].out_value = (void *)(data++); - chain5_fields[1].in_value = ReadyPos++; - - if (count) + uint8_t *Readies; + size_t readiesNum = (count + 1); + size_t bytes = sizeof(*Readies)*readiesNum; + Readies = (uint8_t *) malloc(bytes); + if (Readies == NULL) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD); - jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay), - arm11_MOVE_PD_RTI_PD_with_delay); + LOG_ERROR("Out of memory allocating " ZU " bytes", bytes); + return ERROR_FAIL; } - else + + uint8_t * ReadyPos = Readies; + + while (count--) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI); + chain5_fields[0].out_value = (void *)(data++); + chain5_fields[1].in_value = ReadyPos++; + + if (count) + { + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_DRPAUSE)); + jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay), + arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay); + } + else + { + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE)); + } } - } - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + + chain5_fields[0].out_value = 0; + chain5_fields[1].in_value = ReadyPos++; - chain5_fields[0].out_value = 0; - chain5_fields[1].in_value = ReadyPos++; + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); + int retval = jtag_execute_queue(); + if (retval == ERROR_OK) + { + size_t error_count = 0; - jtag_execute_queue(); + for (size_t i = 0; i < readiesNum; i++) + { + if (Readies[i] != 1) + { + error_count++; + } + } - size_t error_count = 0; + if (error_count > 0 ) + LOG_ERROR(ZU " words out of " ZU " not transferred", error_count, readiesNum); - {size_t i; - for (i = 0; i < asizeof(Readies); i++) - { - if (Readies[i] != 1) - { - error_count++; } - }} - if (error_count) - ERROR("Transfer errors %d", error_count); + free(Readies); + + return retval; } @@ -540,9 +655,9 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * \param data Data word to be passed to the core via DTR * */ -void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { - arm11_run_instr_data_to_core(arm11, opcode, &data, 1); + return arm11_run_instr_data_to_core(arm11, opcode, &data, 1); } @@ -559,37 +674,58 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data) * \param count Number of data words and instruction repetitions * */ -void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count) +int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count) { - arm11_add_IR(arm11, ARM11_ITRSEL, -1); + arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI); + arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE); - arm11_add_IR(arm11, ARM11_INTEST, -1); + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); - scan_field_t chain5_fields[3]; + struct scan_field chain5_fields[3]; - u32 Data; - u8 Ready; - u8 nRetry; + uint32_t Data; + uint8_t Ready; + uint8_t nRetry; - arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); - arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); - arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); + arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0); + arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1); + arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2); - while (count--) - { - do + while (count--) { - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD); - jtag_execute_queue(); + int i = 0; + do + { + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); - JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); + CHECK_RETVAL(jtag_execute_queue()); + + JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); + + long long then = 0; + + if (i == 1000) + { + then = timeval_ms(); + } + if (i >= 1000) + { + if ((timeval_ms()-then) > 1000) + { + LOG_WARNING("Timeout (1000ms) waiting for instructions to complete"); + return ERROR_FAIL; + } + } + + i++; + } + while (!Ready); + + *data++ = Data; } - while (!Ready); - *data++ = Data; - } + return ERROR_OK; } /** Execute one instruction via ITR @@ -604,12 +740,17 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed. * */ -void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data) +int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data) { - arm11_run_instr_no_data1(arm11, opcode); + int retval; + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; + + /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */ + arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1); - /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */ - arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1); + return ERROR_OK; } /** Load data into core via DTR then move it to r0 then @@ -624,12 +765,19 @@ void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u * \param data Data word that will be written to r0 before \p opcode is executed * */ -void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data) +int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data) { - /* MRC p14,0,r0,c0,c5,0 */ - arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + int retval; + /* MRC p14,0,r0,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data); + if (retval != ERROR_OK) + return retval; - arm11_run_instr_no_data1(arm11, opcode); + retval = arm11_run_instr_no_data1(arm11, opcode); + if (retval != ERROR_OK) + return retval; + + return ERROR_OK; } /** Apply reads and writes to scan chain 7 @@ -641,78 +789,83 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * \param count Number of instructions in the list. * */ -void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count) +int arm11_sc7_run(struct arm11_common * arm11, arm11_sc7_action_t * actions, size_t count) { - arm11_add_debug_SCAN_N(arm11, 0x07, -1); + int retval; - arm11_add_IR(arm11, ARM11_EXTEST, -1); + retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT); + if (retval != ERROR_OK) + return retval; - scan_field_t chain7_fields[3]; + arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT); - u8 nRW; - u32 DataOut; - u8 AddressOut; - u8 Ready; - u32 DataIn; - u8 AddressIn; + struct scan_field chain7_fields[3]; - arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); - arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); - arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); + uint8_t nRW; + uint32_t DataOut; + uint8_t AddressOut; + uint8_t Ready; + uint32_t DataIn; + uint8_t AddressIn; - {size_t i; - for (i = 0; i < count + 1; i++) - { - if (i < count) - { - nRW = actions[i].write ? 1 : 0; - DataOut = actions[i].value; - AddressOut = actions[i].address; - } - else - { - nRW = 0; - DataOut = 0; - AddressOut = 0; - } + arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0); + arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1); + arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2); - do + for (size_t i = 0; i < count + 1; i++) { - JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); + if (i < count) + { + nRW = actions[i].write ? 1 : 0; + DataOut = actions[i].value; + AddressOut = actions[i].address; + } + else + { + nRW = 0; + DataOut = 0; + AddressOut = 0; + } - arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD); - jtag_execute_queue(); + do + { + JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); - JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); - } - while (!Ready); /* 'nRW' is 'Ready' on read out */ + arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); - if (i > 0) - { - if (actions[i - 1].address != AddressIn) - { - WARNING("Scan chain 7 shifted out unexpected address"); - } - - if (!actions[i - 1].write) - { - actions[i - 1].value = DataIn; - } - else - { - if (actions[i - 1].value != DataIn) + CHECK_RETVAL(jtag_execute_queue()); + + JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); + } + while (!Ready); /* 'nRW' is 'Ready' on read out */ + + if (i > 0) { - WARNING("Scan chain 7 shifted out unexpected data"); + if (actions[i - 1].address != AddressIn) + { + LOG_WARNING("Scan chain 7 shifted out unexpected address"); + } + + if (!actions[i - 1].write) + { + actions[i - 1].value = DataIn; + } + else + { + if (actions[i - 1].value != DataIn) + { + LOG_WARNING("Scan chain 7 shifted out unexpected data"); + } + } } - } } - }} - {size_t i; - for (i = 0; i < count; i++) - { - JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value); - }} + for (size_t i = 0; i < count; i++) + { + JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value); + } + + return ERROR_OK; } /** Clear VCR and all breakpoints and watchpoints via scan chain 7 @@ -720,29 +873,28 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t * \param arm11 Target state variable. * */ -void arm11_sc7_clear_vbw(arm11_common_t * arm11) +void arm11_sc7_clear_vbw(struct arm11_common * arm11) { - arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; - arm11_sc7_action_t * pos = clear_bw; - - {size_t i; - for (i = 0; i < asizeof(clear_bw); i++) - { - clear_bw[i].write = 1; - clear_bw[i].value = 0; - }} - - {size_t i; - for (i = 0; i < arm11->brp; i++) - (pos++)->address = ARM11_SC7_BCR0 + i; - } - - {size_t i; - for (i = 0; i < arm11->wrp; i++) - (pos++)->address = ARM11_SC7_WCR0 + i; - } - - (pos++)->address = ARM11_SC7_VCR; + arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1]; + arm11_sc7_action_t * pos = clear_bw; + + for (size_t i = 0; i < asizeof(clear_bw); i++) + { + clear_bw[i].write = true; + clear_bw[i].value = 0; + } + + for (size_t i = 0; i < arm11->brp; i++) + (pos++)->address = ARM11_SC7_BCR0 + i; + + + for (size_t i = 0; i < arm11->wrp; i++) + (pos++)->address = ARM11_SC7_WCR0 + i; + + + (pos++)->address = ARM11_SC7_VCR; + + arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw)); } /** Write VCR register @@ -750,16 +902,16 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) * \param arm11 Target state variable. * \param value Value to be written */ -void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) +void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value) { - arm11_sc7_action_t set_vcr; + arm11_sc7_action_t set_vcr; - set_vcr.write = 0; - set_vcr.address = ARM11_SC7_VCR; - set_vcr.value = value; + set_vcr.write = true; + set_vcr.address = ARM11_SC7_VCR; + set_vcr.value = value; - arm11_sc7_run(arm11, &set_vcr, 1); + arm11_sc7_run(arm11, &set_vcr, 1); } @@ -771,17 +923,96 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value) * \param result Pointer where to store result * */ -void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result) +int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result) { - arm11_run_instr_data_prepare(arm11); + int retval; + retval = arm11_run_instr_data_prepare(arm11); + if (retval != ERROR_OK) + return retval; - /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ - arm11_run_instr_data_to_core1(arm11, 0xee100e15, address); + /* MRC p14,0,r0,c0,c5,0 (r0 = address) */ + CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address)); - /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ - arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1); + /* LDC p14,c5,[R0],#4 (DTR = [r0]) */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1)); - arm11_run_instr_data_finish(arm11); + return arm11_run_instr_data_finish(arm11); } +/** Write Embedded Trace Macrocell (ETM) via Scan chain 6 + * + * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe + * + * \param arm11 Target state variable. + * \param address 7 bit ETM register address + * \param value Value to be written + * + * \return Error status + * + * \remarks This is a stand-alone function that executes the JTAG command queue. + */ +int arm11_write_etm(struct arm11_common * arm11, uint8_t address, uint32_t value) +{ + CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT)); + + /* Uses INTEST for read and write */ + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + + struct scan_field chain6_fields[3]; + + uint8_t nRW = 1; + + arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0); + arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1); + arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2); + + arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE); + + CHECK_RETVAL(jtag_execute_queue()); + + return ERROR_OK; +} + +/** Read Embedded Trace Macrocell (ETM) via Scan chain 6 + * + * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe + * + * \param arm11 Target state variable. + * \param address 7 bit ETM register address + * \param value Pointer that receives value that was read + * + * \return Error status + * + * \remarks This is a stand-alone function that executes the JTAG command queue. + */ +int arm11_read_etm(struct arm11_common * arm11, uint8_t address, uint32_t * value) +{ + CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT)); + + /* Uses INTEST for read and write */ + arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT); + + struct scan_field chain6_fields[3]; + + uint8_t nRW = 0; + + arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0); + arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1); + arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2); + + arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE); + + /* Data is made available in Capture-DR and shifted out on the next access */ + + arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0); + arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1); + arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2); + + arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE); + + CHECK_RETVAL(jtag_execute_queue()); + + return ERROR_OK; +} +