X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=1d9efc04e3e528ed7b30e8ea0ecfe5de84baad6b;hp=24885d2e5e73185b94a7f38e10d255eeed373f06;hb=a28eaa85f73759bb189a46308642502c9fa5aa4b;hpb=0d7d64b5e9a463f63deb19f00efa14e6e5b1c34e diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 24885d2e5e..1d9efc04e3 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -24,6 +24,7 @@ #include "arm720t.h" #include "jtag.h" #include "log.h" +#include "time_support.h" #include #include @@ -41,9 +42,9 @@ int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /* forward declarations */ -int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target); +int arm720t_target_create(struct target_s *target,Jim_Interp *interp); int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm720t_quit(); +int arm720t_quit(void); int arm720t_arch_state(struct target_s *target); int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); @@ -70,6 +71,7 @@ target_type_t arm720t_target = .write_memory = arm720t_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -79,7 +81,7 @@ target_type_t arm720t_target = .remove_watchpoint = arm7_9_remove_watchpoint, .register_commands = arm720t_register_commands, - .target_command = arm720t_target_command, + .target_create = arm720t_target_create, .init_target = arm720t_init_target, .examine = arm7tdmi_examine, .quit = arm720t_quit @@ -87,6 +89,7 @@ target_type_t arm720t_target = int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; @@ -97,10 +100,16 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); jtag_add_end_state(TAP_PD); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + { + return retval; + } + if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) + { + return retval; + } - fields[0].device = jtag_info->chain_pos; + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; fields[0].out_mask = NULL; @@ -110,7 +119,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - fields[1].device = jtag_info->chain_pos; + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = out_buf; fields[1].out_mask = NULL; @@ -133,7 +142,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c jtag_add_runtest(0, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - jtag_execute_queue(); + if((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } if (in) LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); @@ -319,7 +331,7 @@ int arm720t_arch_state(struct target_s *target) "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, Cache: %s", armv4_5_state_strings[armv4_5->core_state], - target_debug_reason_strings[target->debug_reason], + Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -361,29 +373,42 @@ int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou int arm720t_soft_reset_halt(struct target_s *target) { + int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - int i; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - target->type->halt(target); + if ((retval = target_halt(target)) != ERROR_OK) + { + return retval; + } - for (i=0; i<10; i++) + long long then=timeval_ms(); + int timeout; + while (!(timeout=((timeval_ms()-then)>1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - jtag_execute_queue(); + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } } else { break; } - /* do not eat all CPU, time out after 1 se*/ - usleep(100*1000); + if (debug_level>=3) + { + alive_sleep(100); + } else + { + keep_alive(); + } } - if (i==10) + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; @@ -409,7 +434,10 @@ int arm720t_soft_reset_halt(struct target_s *target) arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) + { + return retval; + } return ERROR_OK; } @@ -422,18 +450,18 @@ int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *targ } -int arm720t_quit() +int arm720t_quit(void) { return ERROR_OK; } -int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chain_pos, char *variant) +int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap, const char *variant) { arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common; arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common; - arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant); + arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant); arm7tdmi->arch_info = arm720t; arm720t->common_magic = ARM720T_COMMON_MAGIC; @@ -453,27 +481,11 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, int chai return ERROR_OK; } -int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) +int arm720t_target_create(struct target_s *target, Jim_Interp *interp) { - int chain_pos; - char *variant = NULL; - arm720t_common_t *arm720t = malloc(sizeof(arm720t_common_t)); - memset(arm720t, 0, sizeof(*arm720t)); - - if (argc < 4) - { - LOG_ERROR("'target arm720t' requires at least one additional argument"); - exit(-1); - } - - chain_pos = strtoul(args[3], NULL, 0); - - if (argc >= 5) - variant = args[4]; - - LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant); + arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t)); - arm720t_init_arch_info(target, arm720t, chain_pos, variant); + arm720t_init_arch_info(target, arm720t, target->tap, target->variant); return ERROR_OK; } @@ -539,7 +551,11 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode); return ERROR_OK; } - jtag_execute_queue(); + + if ((retval = jtag_execute_queue()) != ERROR_OK) + { + return retval; + } command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); } @@ -635,4 +651,3 @@ int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char * return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } -