X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=3d12aba22aab48a7d6c0fae0fc7440f6e3512181;hp=b04a17f7eb1b2c72b4bbf4f47c7662ca5986b42e;hb=5c941edc7b0d6e0bed596293d81867453d1462e9;hpb=90465379e558ea7310867d9d39b79428c2050ddb diff --git a/src/target/arm720t.c b/src/target/arm720t.c index b04a17f7eb..3d12aba22a 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -2,6 +2,9 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2009 by Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -13,144 +16,85 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "arm720t.h" -#include "jtag.h" -#include "log.h" -#include "time_support.h" +#include +#include "target_type.h" +#include "register.h" +#include "arm_opcodes.h" + -#include -#include +/* + * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see + * ARM DDI 0229C especially Chapter 9 about debug support. + */ #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int arm720t_register_commands(struct command_context_s *cmd_ctx); - -int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm720t_target_create(struct target_s *target,Jim_Interp *interp); -int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm720t_quit(void); -int arm720t_arch_state(struct target_s *target); -int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); -int arm720t_soft_reset_halt(struct target_s *target); - -target_type_t arm720t_target = +static int arm720t_scan_cp15(struct target *target, + uint32_t out, uint32_t *in, int instruction, int clock_arg) { - .name = "arm720t", - - .poll = arm7_9_poll, - .arch_state = arm720t_arch_state, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm720t_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm720t_read_memory, - .write_memory = arm720t_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm720t_register_commands, - .target_create = arm720t_target_create, - .init_target = arm720t_init_target, - .examine = arm7tdmi_examine, - .quit = arm720t_quit -}; + int retval; + struct arm720t_common *arm720t = target_to_arm720(target); + struct arm_jtag *jtag_info; + struct scan_field fields[2]; + uint8_t out_buf[4]; + uint8_t instruction_buf = instruction; -int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock) -{ - int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[2]; - u8 out_buf[4]; - u8 instruction_buf = instruction; + jtag_info = &arm720t->arm7_9_common.jtag_info; buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - jtag_add_end_state(TAP_DRPAUSE); - if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) - { + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = out_buf; fields[1].in_value = NULL; - if (in) - { - u8 tmp[4]; - fields[1].in_value = tmp; - jtag_add_dr_scan_now(2, fields, TAP_INVALID); - *in=flip_u32(le_to_h_u32(tmp), 32); + if (in) { + fields[1].in_value = (uint8_t *)in; + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); + jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); } else - { - jtag_add_dr_scan(2, fields, TAP_INVALID); - } + jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); - if (clock) - jtag_add_runtest(0, TAP_INVALID); + if (clock_arg) + jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - if((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); else - LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg); #else - LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg); #endif return ERROR_OK; } -int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value) +static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -167,7 +111,7 @@ int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value) return ERROR_OK; } -int arm720t_write_cp15(target_t *target, u32 opcode, u32 value) +static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value) { /* fetch CP15 opcode */ arm720t_scan_cp15(target, opcode, NULL, 1, 1); @@ -183,25 +127,39 @@ int arm720t_write_cp15(target_t *target, u32 opcode, u32 value) return ERROR_OK; } -u32 arm720t_get_ttb(target_t *target) +static int arm720t_get_ttb(struct target *target, uint32_t *result) { - u32 ttb = 0x0; + uint32_t ttb = 0x0; - arm720t_read_cp15(target, 0xee120f10, &ttb); - jtag_execute_queue(); + int retval; + + retval = arm720t_read_cp15(target, 0xee120f10, &ttb); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; ttb &= 0xffffc000; - return ttb; + *result = ttb; + + return ERROR_OK; } -void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static int arm720t_disable_mmu_caches(struct target *target, + int mmu, int d_u_cache, int i_cache) { - u32 cp15_control; + uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm720t_read_cp15(target, 0xee110f10, &cp15_control); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control &= ~0x1U; @@ -209,16 +167,23 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ if (d_u_cache || i_cache) cp15_control &= ~0x4U; - arm720t_write_cp15(target, 0xee010f10, cp15_control); + retval = arm720t_write_cp15(target, 0xee010f10, cp15_control); + return retval; } -void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static int arm720t_enable_mmu_caches(struct target *target, + int mmu, int d_u_cache, int i_cache) { - u32 cp15_control; + uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm720t_read_cp15(target, 0xee110f10, &cp15_control); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control |= 0x1U; @@ -226,182 +191,167 @@ void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c if (d_u_cache || i_cache) cp15_control |= 0x4U; - arm720t_write_cp15(target, 0xee010f10, cp15_control); + retval = arm720t_write_cp15(target, 0xee010f10, cp15_control); + return retval; } -void arm720t_post_debug_entry(target_t *target) +static int arm720t_post_debug_entry(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); + int retval; /* examine cp15 control reg */ - arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); - jtag_execute_queue(); - LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg); + retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg); arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; /* save i/d fault status and address register */ - arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg); - arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg); + if (retval != ERROR_OK) + return retval; + retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + return retval; } -void arm720t_pre_restore_context(target_t *target) +static void arm720t_pre_restore_context(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); /* restore i/d fault status and address register */ arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg); arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); } -int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p) +static int arm720t_verify_pointer(struct command_context *cmd_ctx, + struct arm720t_common *arm720t) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } - - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } - - arm7tdmi = arm7_9->arch_info; - if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC) - { - return -1; - } - - arm720t = arm7tdmi->arch_info; - if (arm720t->common_magic != ARM720T_COMMON_MAGIC) - { - return -1; + if (arm720t->common_magic != ARM720T_COMMON_MAGIC) { + command_print(cmd_ctx, "target is not an ARM720"); + return ERROR_TARGET_INVALID; } - - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm7tdmi_p = arm7tdmi; - *arm720t_p = arm720t; - return ERROR_OK; } -int arm720t_arch_state(struct target_s *target) +static int arm720t_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); - char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); - } - - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8x pc: 0x%8.8x\n" - "MMU: %s, Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name , - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, Cache: %s", state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); return ERROR_OK; } -int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +static int arm720_mmu(struct target *target, int *enabled) +{ + if (target->state != TARGET_HALTED) { + LOG_ERROR("%s: target not halted", __func__); + return ERROR_TARGET_INVALID; + } + + *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled; + return ERROR_OK; +} + +static int arm720_virt2phys(struct target *target, + target_addr_t virtual, target_addr_t *physical) +{ + uint32_t cb; + struct arm720t_common *arm720t = target_to_arm720(target); + + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, + &arm720t->armv4_5_mmu, virtual, &cb, &ret); + if (retval != ERROR_OK) + return retval; + *physical = ret; + return ERROR_OK; +} + +static int arm720t_read_memory(struct target *target, + target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; + struct arm720t_common *arm720t = target_to_arm720(target); /* disable cache, but leave MMU enabled */ - if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - arm720t_disable_mmu_caches(target, 0, 1, 0); - + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { + retval = arm720t_disable_mmu_caches(target, 0, 1, 0); + if (retval != ERROR_OK) + return retval; + } retval = arm7_9_read_memory(target, address, size, count, buffer); - if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - arm720t_enable_mmu_caches(target, 0, 1, 0); + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { + retval = arm720t_enable_mmu_caches(target, 0, 1, 0); + if (retval != ERROR_OK) + return retval; + } return retval; } -int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +static int arm720t_read_phys_memory(struct target *target, + target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - int retval; + struct arm720t_common *arm720t = target_to_arm720(target); - if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) - return retval; + return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); +} - return retval; +static int arm720t_write_phys_memory(struct target *target, + target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) +{ + struct arm720t_common *arm720t = target_to_arm720(target); + + return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer); } -int arm720t_soft_reset_halt(struct target_s *target) +static int arm720t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; - arm720t_common_t *arm720t = arm7tdmi->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm720t_common *arm720t = target_to_arm720(target); + struct reg *dbg_stat = &arm720t->arm7_9_common + .eice_cache->reg_list[EICE_DBG_STAT]; + struct arm *arm = &arm720t->arm7_9_common.arm; - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } - long long then=timeval_ms(); + int64_t then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) - { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } } else - { break; - } - if (debug_level>=3) - { + if (debug_level >= 3) alive_sleep(100); - } else - { + else keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -409,51 +359,58 @@ int arm720t_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; - /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; + /* start fetching from 0x0 */ + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = 1; + arm->pc->valid = 1; - arm720t_disable_mmu_caches(target, 1, 1, 1); + retval = arm720t_disable_mmu_caches(target, 1, 1, 1); + if (retval != ERROR_OK) + return retval; arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } -int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target) { - arm7tdmi_init_target(cmd_ctx, target); - - return ERROR_OK; + return arm7tdmi_init_target(cmd_ctx, target); } -int arm720t_quit(void) +/* FIXME remove forward decls */ +static int arm720t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm720t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + +static int arm720t_init_arch_info(struct target *target, + struct arm720t_common *arm720t, struct jtag_tap *tap) { - return ERROR_OK; -} + struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common; -int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap) -{ - arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common; - arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common; + arm7_9->arm.mrc = arm720t_mrc; + arm7_9->arm.mcr = arm720t_mcr; - arm7tdmi_init_arch_info(target, arm7tdmi, tap); + arm7tdmi_init_arch_info(target, arm7_9, tap); - arm7tdmi->arch_info = arm720t; arm720t->common_magic = ARM720T_COMMON_MAGIC; arm7_9->post_debug_entry = arm720t_post_debug_entry; @@ -471,173 +428,161 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap return ERROR_OK; } -int arm720t_target_create(struct target_s *target, Jim_Interp *interp) -{ - arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t)); - - arm720t_init_arch_info(target, arm720t, target->tap); - - return ERROR_OK; -} - -int arm720t_register_commands(struct command_context_s *cmd_ctx) +static int arm720t_target_create(struct target *target, Jim_Interp *interp) { - int retval; - command_t *arm720t_cmd; - - - retval = arm7tdmi_register_commands(cmd_ctx); - - arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); - - register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa "); + struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); - register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words [count]"); - register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words [count]"); - register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes [count]"); - - register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word "); - register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word "); - register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte "); - - return ERROR_OK; + arm720t->arm7_9_common.arm.is_armv4 = true; + return arm720t_init_arch_info(target, arm720t, target->tap); } -int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm720t_handle_cp15_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; - } + struct target *target = get_current_target(CMD_CTX); + struct arm720t_common *arm720t = target_to_arm720(target); - jtag_info = &arm7_9->jtag_info; + retval = arm720t_verify_pointer(CMD_CTX, arm720t); + if (retval != ERROR_OK) + return retval; - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + if (target->state != TARGET_HALTED) { + command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) - { - u32 opcode = strtoul(args[0], NULL, 0); - - if (argc == 1) - { - u32 value; - if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode); + if (CMD_ARGC >= 1) { + uint32_t opcode; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); + + if (CMD_ARGC == 1) { + uint32_t value; + retval = arm720t_read_cp15(target, opcode, &value); + if (retval != ERROR_OK) { + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } - command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); - } - else if (argc == 2) - { - u32 value = strtoul(args[1], NULL, 0); - if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); + } else if (CMD_ARGC == 2) { + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + + retval = arm720t_write_cp15(target, opcode, value); + if (retval != ERROR_OK) { + command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); + command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); } } return ERROR_OK; } -int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int arm720t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; + if (cpnum != 15) { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; } - jtag_info = &arm7_9->jtag_info; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + /* read "to" r0 */ + return arm720t_read_cp15(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + value); - return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } -int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +static int arm720t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; + if (cpnum != 15) { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; } - jtag_info = &arm7_9->jtag_info; + /* write "from" r0 */ + return arm720t_write_cp15(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + value); +} - if (target->state != TARGET_HALTED) +static const struct command_registration arm720t_exec_command_handlers[] = { { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); -} + .name = "cp15", + .handler = arm720t_handle_cp15_command, + .mode = COMMAND_EXEC, + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value]", + }, + COMMAND_REGISTRATION_DONE +}; -int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm7tdmi_common_t *arm7tdmi; - arm720t_common_t *arm720t; - arm_jtag_t *jtag_info; - - if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK) +static const struct command_registration arm720t_command_handlers[] = { { - command_print(cmd_ctx, "current target isn't an ARM720t target"); - return ERROR_OK; - } + .chain = arm7_9_command_handlers, + }, + { + .name = "arm720t", + .mode = COMMAND_ANY, + .help = "arm720t command group", + .usage = "", + .chain = arm720t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; - jtag_info = &arm7_9->jtag_info; +/** Holds methods for ARM720 targets. */ +struct target_type arm720t_target = { + .name = "arm720t", - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + .poll = arm7_9_poll, + .arch_state = arm720t_arch_state, - return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); -} + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm720t_soft_reset_halt, + + .get_gdb_arch = arm_get_gdb_arch, + .get_gdb_reg_list = arm_get_gdb_reg_list, + + .read_memory = arm720t_read_memory, + .write_memory = arm7_9_write_memory_opt, + .read_phys_memory = arm720t_read_phys_memory, + .write_phys_memory = arm720t_write_phys_memory, + .mmu = arm720_mmu, + .virt2phys = arm720_virt2phys, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .commands = arm720t_command_handlers, + .target_create = arm720t_target_create, + .init_target = arm720t_init_target, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, +};