X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm720t.c;h=b592ffc47becec9a80adb2bfdda5e4c9d5121419;hp=71d4a0172bd1fb5513767b9dd4f7f4be6206c5b0;hb=7fafb3e96110a7712bb08611c57b14d64550fa0f;hpb=36df240cea04990e8c18aa0b90bd63374f22dbd3 diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 71d4a0172b..b592ffc47b 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -16,10 +16,9 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif @@ -41,7 +40,7 @@ #endif static int arm720t_scan_cp15(struct target *target, - uint32_t out, uint32_t *in, int instruction, int clock) + uint32_t out, uint32_t *in, int instruction, int clock_arg) { int retval; struct arm720t_common *arm720t = target_to_arm720(target); @@ -54,15 +53,12 @@ static int arm720t_scan_cp15(struct target *target, buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - jtag_set_end_state(TAP_DRPAUSE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } - if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK) - { + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE); + if (retval != ERROR_OK) return retval; - } fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; @@ -72,31 +68,27 @@ static int arm720t_scan_cp15(struct target *target, fields[1].out_value = out_buf; fields[1].in_value = NULL; - if (in) - { + if (in) { fields[1].in_value = (uint8_t *)in; jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); jtag_add_callback(arm7flip32, (jtag_callback_data_t)in); } else - { jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE); - } - if (clock) + if (clock_arg) jtag_add_runtest(0, TAP_DRPAUSE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } if (in) LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock); else - LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg); #else - LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock); + LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg); #endif return ERROR_OK; @@ -135,26 +127,39 @@ static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t v return ERROR_OK; } -static uint32_t arm720t_get_ttb(struct target *target) +static int arm720t_get_ttb(struct target *target, uint32_t *result) { uint32_t ttb = 0x0; - arm720t_read_cp15(target, 0xee120f10, &ttb); - jtag_execute_queue(); + int retval; + + retval = arm720t_read_cp15(target, 0xee120f10, &ttb); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; ttb &= 0xffffc000; - return ttb; + *result = ttb; + + return ERROR_OK; } -static void arm720t_disable_mmu_caches(struct target *target, +static int arm720t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm720t_read_cp15(target, 0xee110f10, &cp15_control); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control &= ~0x1U; @@ -162,17 +167,23 @@ static void arm720t_disable_mmu_caches(struct target *target, if (d_u_cache || i_cache) cp15_control &= ~0x4U; - arm720t_write_cp15(target, 0xee010f10, cp15_control); + retval = arm720t_write_cp15(target, 0xee010f10, cp15_control); + return retval; } -static void arm720t_enable_mmu_caches(struct target *target, +static int arm720t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm720t_read_cp15(target, 0xee110f10, &cp15_control); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control |= 0x1U; @@ -180,16 +191,22 @@ static void arm720t_enable_mmu_caches(struct target *target, if (d_u_cache || i_cache) cp15_control |= 0x4U; - arm720t_write_cp15(target, 0xee010f10, cp15_control); + retval = arm720t_write_cp15(target, 0xee010f10, cp15_control); + return retval; } -static void arm720t_post_debug_entry(struct target *target) +static int arm720t_post_debug_entry(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); + int retval; /* examine cp15 control reg */ - arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg); arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0; @@ -197,9 +214,14 @@ static void arm720t_post_debug_entry(struct target *target) arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; /* save i/d fault status and address register */ - arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg); - arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg); - jtag_execute_queue(); + retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg); + if (retval != ERROR_OK) + return retval; + retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + return retval; } static void arm720t_pre_restore_context(struct target *target) @@ -224,15 +246,11 @@ static int arm720t_verify_pointer(struct command_context *cmd_ctx, static int arm720t_arch_state(struct target *target) { struct arm720t_common *arm720t = target_to_arm720(target); - struct arm *armv4_5; - static const char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; - armv4_5 = &arm720t->arm7_9_common.armv4_5_common; - arm_arch_state(target); LOG_USER("MMU: %s, Cache: %s", state[arm720t->armv4_5_mmu.mmu_enabled], @@ -253,43 +271,45 @@ static int arm720_mmu(struct target *target, int *enabled) } static int arm720_virt2phys(struct target *target, - uint32_t virtual, uint32_t *physical) + target_addr_t virtual, target_addr_t *physical) { - int type; uint32_t cb; - int domain; - uint32_t ap; struct arm720t_common *arm720t = target_to_arm720(target); - uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); - if (type == -1) - { - return ret; - } + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, + &arm720t->armv4_5_mmu, virtual, &cb, &ret); + if (retval != ERROR_OK) + return retval; *physical = ret; return ERROR_OK; } static int arm720t_read_memory(struct target *target, - uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) + target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; struct arm720t_common *arm720t = target_to_arm720(target); /* disable cache, but leave MMU enabled */ - if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - arm720t_disable_mmu_caches(target, 0, 1, 0); - + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { + retval = arm720t_disable_mmu_caches(target, 0, 1, 0); + if (retval != ERROR_OK) + return retval; + } retval = arm7_9_read_memory(target, address, size, count, buffer); - if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - arm720t_enable_mmu_caches(target, 0, 1, 0); + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { + retval = arm720t_enable_mmu_caches(target, 0, 1, 0); + if (retval != ERROR_OK) + return retval; + } return retval; } static int arm720t_read_phys_memory(struct target *target, - uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) + target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm720t_common *arm720t = target_to_arm720(target); @@ -297,7 +317,7 @@ static int arm720t_read_phys_memory(struct target *target, } static int arm720t_write_phys_memory(struct target *target, - uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) + target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct arm720t_common *arm720t = target_to_arm720(target); @@ -310,39 +330,28 @@ static int arm720t_soft_reset_halt(struct target *target) struct arm720t_common *arm720t = target_to_arm720(target); struct reg *dbg_stat = &arm720t->arm7_9_common .eice_cache->reg_list[EICE_DBG_STAT]; - struct arm *armv4_5 = &arm720t->arm7_9_common - .armv4_5_common; + struct arm *arm = &arm720t->arm7_9_common.arm; - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } - long long then = timeval_ms(); + int64_t then = timeval_ms(); int timeout; - while (!(timeout = ((timeval_ms()-then) > 1000))) - { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } } else - { break; - } if (debug_level >= 3) - { alive_sleep(100); - } else - { + else keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -352,26 +361,27 @@ static int arm720t_soft_reset_halt(struct target *target) /* SVC, ARM state, IRQ and FIQ disabled */ uint32_t cpsr; - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); cpsr &= ~0xff; cpsr |= 0xd3; - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = true; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = true; + arm->pc->valid = true; - arm720t_disable_mmu_caches(target, 1, 1, 1); + retval = arm720t_disable_mmu_caches(target, 1, 1, 1); + if (retval != ERROR_OK) + return retval; arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { + retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); + if (retval != ERROR_OK) return retval; - } return ERROR_OK; } @@ -396,8 +406,8 @@ static int arm720t_init_arch_info(struct target *target, { struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common; - arm7_9->armv4_5_common.mrc = arm720t_mrc; - arm7_9->armv4_5_common.mcr = arm720t_mcr; + arm7_9->arm.mrc = arm720t_mrc; + arm7_9->arm.mcr = arm720t_mcr; arm7tdmi_init_arch_info(target, arm7_9, tap); @@ -422,7 +432,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp) { struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); - arm720t->arm7_9_common.armv4_5_common.is_armv4 = true; + arm720t->arm7_9_common.arm.is_armv4 = true; return arm720t_init_arch_info(target, arm720t, target->tap); } @@ -431,49 +441,40 @@ COMMAND_HANDLER(arm720t_handle_cp15_command) int retval; struct target *target = get_current_target(CMD_CTX); struct arm720t_common *arm720t = target_to_arm720(target); - struct arm_jtag *jtag_info; retval = arm720t_verify_pointer(CMD_CTX, arm720t); if (retval != ERROR_OK) return retval; - jtag_info = &arm720t->arm7_9_common.jtag_info; - - if (target->state != TARGET_HALTED) - { + if (target->state != TARGET_HALTED) { command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ - if (CMD_ARGC >= 1) - { + if (CMD_ARGC >= 1) { uint32_t opcode; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (CMD_ARGC == 1) - { + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK) - { + retval = arm720t_read_cp15(target, opcode, &value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value); - } - else if (CMD_ARGC == 2) - { + } else if (CMD_ARGC == 2) { uint32_t value; COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); - if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK) - { + retval = arm720t_write_cp15(target, opcode, value); + if (retval != ERROR_OK) { command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode); return ERROR_OK; } @@ -489,8 +490,7 @@ static int arm720t_mrc(struct target *target, int cpnum, uint32_t CRn, uint32_t CRm, uint32_t *value) { - if (cpnum!=15) - { + if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } @@ -507,8 +507,7 @@ static int arm720t_mcr(struct target *target, int cpnum, uint32_t CRn, uint32_t CRm, uint32_t value) { - if (cpnum!=15) - { + if (cpnum != 15) { LOG_ERROR("Only cp15 is supported"); return ERROR_FAIL; } @@ -540,14 +539,14 @@ static const struct command_registration arm720t_command_handlers[] = { .name = "arm720t", .mode = COMMAND_ANY, .help = "arm720t command group", + .usage = "", .chain = arm720t_exec_command_handlers, }, COMMAND_REGISTRATION_DONE }; /** Holds methods for ARM720 targets. */ -struct target_type arm720t_target = -{ +struct target_type arm720t_target = { .name = "arm720t", .poll = arm7_9_poll, @@ -561,17 +560,16 @@ struct target_type arm720t_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm720t_soft_reset_halt, + .get_gdb_arch = arm_get_gdb_arch, .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm720t_read_memory, - .write_memory = arm7_9_write_memory, + .write_memory = arm7_9_write_memory_opt, .read_phys_memory = arm720t_read_phys_memory, .write_phys_memory = arm720t_write_phys_memory, .mmu = arm720_mmu, .virt2phys = arm720_virt2phys, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm_checksum_memory, .blank_check_memory = arm_blank_check_memory,