X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=19244de32dc70df3edc4847aba1843b4410e5910;hp=21c5c7a2bb8bc51bafff8155b4289299785a1052;hb=46fc1d57ac9462fd788277609707a379c7a406cb;hpb=11a0afc932853fc9cb8d33a5fdce954195f406e2 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 21c5c7a2bb..19244de32d 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -38,17 +38,6 @@ int arm7_9_debug_entry(target_t *target); -int arm7_9_enable_sw_bkpts(struct target_s *target); - -/* command handler forward declarations */ -int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); /** * Clear watchpoints for an ARM7/9 target. @@ -56,7 +45,7 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char * @param arm7_9 Pointer to the common struct for an ARM7/9 target * @return JTAG error status after executing queue */ -static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) +static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9) { LOG_DEBUG("-"); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); @@ -77,7 +66,7 @@ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) * @param arm7_9 Pointer to the common struct for an ARM7/9 target * @param breakpoint Pointer to the breakpoint to be used as a watchpoint */ -static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) +static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, breakpoint_t *breakpoint) { if (!arm7_9->wp0_used) { @@ -108,7 +97,7 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) * @return Error codes if there is a problem finding a watchpoint or the result * of executing the JTAG queue */ -static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) +static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) { if (arm7_9->sw_breakpoints_added) { @@ -172,8 +161,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) */ int arm7_9_setup(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); return arm7_9_clear_watchpoints(arm7_9); } @@ -190,20 +178,20 @@ int arm7_9_setup(target_t *target) * targets * @return ERROR_OK if successful */ -int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) +int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + /* FIXME stop using this routine; just target_to_arm7_9() and + * verify the resulting pointer using a replacement routine + * that emits a usage message. + */ if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } + return ERROR_TARGET_INVALID; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } + return ERROR_TARGET_INVALID; *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; @@ -224,8 +212,7 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm */ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" , @@ -355,9 +342,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; - - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, breakpoint->unique_id, @@ -451,8 +436,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) */ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -503,8 +487,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { @@ -537,11 +520,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) * @return Error status if watchpoint set fails or the result of executing the * JTAG queue */ -int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int rw_mask = 1; uint32_t mask; @@ -609,11 +591,10 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @return Error status while trying to unset the watchpoint or the result of * executing the JTAG queue */ -int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -658,10 +639,9 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @param watchpoint Pointer to the watchpoint to be added * @return Error status while trying to add the watchpoint */ -int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { @@ -692,11 +672,10 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) * @param watchpoint Pointer to the watchpoint to be removed * @return Result of trying to unset the watchpoint */ -int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) +int arm7_9_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (watchpoint->set) { @@ -723,10 +702,8 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) int arm7_9_execute_sys_speed(struct target_s *target) { int retval; - - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ @@ -778,9 +755,8 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) static int set = 0; static uint8_t check_value[4], check_mask[4]; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ @@ -820,9 +796,8 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) */ int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t *data; int retval = ERROR_OK; uint32_t i; @@ -857,9 +832,8 @@ int arm7_9_handle_target_request(void *priv) target_t *target = priv; if (!target_was_examined(target)) return ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; if (!target->dbg_msg_enabled) @@ -916,8 +890,7 @@ int arm7_9_handle_target_request(void *priv) int arm7_9_poll(target_t *target) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* read debug status register */ @@ -1009,8 +982,8 @@ int arm7_9_poll(target_t *target) */ int arm7_9_assert_reset(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + LOG_DEBUG("target->state: %s", target_state_name(target)); @@ -1141,8 +1114,7 @@ int arm7_9_deassert_reset(target_t *target) */ int arm7_9_clear_halt(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; /* we used DBGRQ only if we didn't come out of reset */ @@ -1199,8 +1171,8 @@ int arm7_9_clear_halt(target_t *target) */ int arm7_9_soft_reset_halt(struct target_s *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int i; @@ -1318,8 +1290,7 @@ int arm7_9_halt(target_t *target) return ERROR_OK; } - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", @@ -1381,9 +1352,8 @@ int arm7_9_debug_entry(target_t *target) uint32_t r0_thumb, pc_thumb; uint32_t cpsr; int retval; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; @@ -1536,8 +1506,8 @@ int arm7_9_full_context(target_t *target) { int i; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; LOG_DEBUG("-"); @@ -1627,10 +1597,10 @@ int arm7_9_full_context(target_t *target) */ int arm7_9_restore_context(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *reg; - armv4_5_core_reg_t *reg_arch_info; + struct armv4_5_core_reg *reg_arch_info; enum armv4_5_mode current_mode = armv4_5->core_mode; int i, j; int dirty; @@ -1777,9 +1747,8 @@ int arm7_9_restore_context(target_t *target) */ int arm7_9_restart_core(struct target_s *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ jtag_set_end_state(TAP_IDLE); @@ -1801,7 +1770,7 @@ int arm7_9_restart_core(struct target_s *target) */ void arm7_9_enable_watchpoints(struct target_s *target) { - watchpoint_t *watchpoint = target->watchpoints; + struct watchpoint *watchpoint = target->watchpoints; while (watchpoint) { @@ -1831,8 +1800,8 @@ void arm7_9_enable_breakpoints(struct target_s *target) int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; breakpoint_t *breakpoint = target->breakpoints; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; @@ -1991,9 +1960,8 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); @@ -2029,8 +1997,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) void arm7_9_disable_eice_step(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]); @@ -2045,8 +2012,8 @@ void arm7_9_disable_eice_step(target_t *target) int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; breakpoint_t *breakpoint = NULL; int err, retval; @@ -2141,13 +2108,13 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod uint32_t* reg_p[16]; uint32_t value; int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; + enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) return ERROR_INVALID_ARGUMENTS; @@ -2177,7 +2144,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod /* read a program status register * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr */ - armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; + struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1; arm7_9->read_xpsr(target, &value, spsr); @@ -2205,13 +2172,13 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) { uint32_t reg[16]; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; + enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode; if ((num < 0) || (num > 16)) return ERROR_INVALID_ARGUMENTS; @@ -2240,7 +2207,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo /* write a program status register * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr */ - armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; + struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info; int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1; /* if we're writing the CPSR, mask the T bit */ @@ -2265,9 +2232,8 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t reg[16]; uint32_t num_accesses = 0; int thisrun_accesses; @@ -2441,8 +2407,8 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; uint32_t reg[16]; @@ -2628,8 +2594,7 @@ static uint8_t *dcc_buffer; static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) return retval; @@ -2644,9 +2609,9 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); buffer += 4; - embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; + struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; uint8_t reg_addr = ice_reg->addr & 0x1f; - jtag_tap_t *tap; + struct jtag_tap *tap; tap = ice_reg->jtag_info->tap; embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2); @@ -2689,13 +2654,12 @@ static const uint32_t dcc_code[] = 0xeafffff9 /* b w */ }; -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); +int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int i; if (!arm7_9->dcc_downloads) @@ -2726,8 +2690,8 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, } } - armv4_5_algorithm_t armv4_5_info; - reg_param_t reg_params[1]; + struct armv4_5_algorithm armv4_5_info; + struct reg_param reg_params[1]; armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; armv4_5_info.core_mode = ARMV4_5_MODE_SVC; @@ -2759,9 +2723,9 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) { - working_area_t *crc_algorithm; - armv4_5_algorithm_t armv4_5_info; - reg_param_t reg_params[2]; + struct working_area *crc_algorithm; + struct armv4_5_algorithm armv4_5_info; + struct reg_param reg_params[2]; int retval; static const uint32_t arm7_9_crc_code[] = { @@ -2843,9 +2807,9 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) { - working_area_t *erase_check_algorithm; - reg_param_t reg_params[3]; - armv4_5_algorithm_t armv4_5_info; + struct working_area *erase_check_algorithm; + struct reg_param reg_params[3]; + struct armv4_5_algorithm armv4_5_info; int retval; uint32_t i; @@ -2907,39 +2871,14 @@ int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_ return ERROR_OK; } -int arm7_9_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *arm7_9_cmd; - - arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands"); - - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); - - register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register "); - - register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, - COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); - register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses "); - register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, - COMMAND_ANY, "use DCC downloads for larger memory writes "); - - armv4_5_register_commands(cmd_ctx); - - etm_register_commands(cmd_ctx); - - return ERROR_OK; -} - -int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_xpsr_command) { uint32_t value; int spsr; int retval; target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -2976,7 +2915,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm return ERROR_OK; } -int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command) { uint32_t value; int rotate; @@ -2984,7 +2923,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char int retval; target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -3018,14 +2957,14 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) { uint32_t value; uint32_t mode; int num; target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -3052,11 +2991,11 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char return arm7_9_write_core_reg(target, num, mode, value); } -int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -3085,11 +3024,11 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch return ERROR_OK; } -int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -3118,11 +3057,11 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, return ERROR_OK; } -int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) { target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) { @@ -3151,7 +3090,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char return ERROR_OK; } -int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) +int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common; @@ -3159,48 +3098,61 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) arm7_9->common_magic = ARM7_9_COMMON_MAGIC; if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) - { return retval; - } - - arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */ - arm7_9->wp_available_max = 2; - arm7_9->sw_breakpoints_added = 0; - arm7_9->sw_breakpoint_count = 0; - arm7_9->breakpoint_count = 0; - arm7_9->wp0_used = 0; - arm7_9->wp1_used = 0; - arm7_9->wp1_used_default = 0; - arm7_9->use_dbgrq = 0; - arm7_9->etm_ctx = NULL; - arm7_9->has_single_step = 0; - arm7_9->has_monitor_mode = 0; - arm7_9->has_vector_catch = 0; + /* caller must have allocated via calloc(), so everything's zeroed */ - arm7_9->debug_entry_from_reset = 0; - - arm7_9->dcc_working_area = NULL; + arm7_9->wp_available_max = 2; arm7_9->fast_memory_access = fast_and_dangerous; arm7_9->dcc_downloads = fast_and_dangerous; - arm7_9->need_bypass_before_restart = 0; - armv4_5->arch_info = arm7_9; armv4_5->read_core_reg = arm7_9_read_core_reg; armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->full_context = arm7_9_full_context; if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) - { return retval; - } - if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) - { - return retval; - } + return target_register_timer_callback(arm7_9_handle_target_request, + 1, 1, target); +} + +int arm7_9_register_commands(struct command_context_s *cmd_ctx) +{ + command_t *arm7_9_cmd; + + arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", + NULL, COMMAND_ANY, "arm7/9 specific commands"); + + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", + handle_arm7_9_write_xpsr_command, COMMAND_EXEC, + "write program status register "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", + handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, + "write program status register " + "<8bit immediate> "); + + register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", + handle_arm7_9_write_core_reg_command, COMMAND_EXEC, + "write core register "); + + register_command(cmd_ctx, arm7_9_cmd, "dbgrq", + handle_arm7_9_dbgrq_command, COMMAND_ANY, + "use EmbeddedICE dbgrq instead of breakpoint " + "for target halt requests "); + register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", + handle_arm7_9_fast_memory_access_command, COMMAND_ANY, + "use fast memory accesses instead of slower " + "but potentially safer accesses "); + register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", + handle_arm7_9_dcc_downloads_command, COMMAND_ANY, + "use DCC downloads for larger memory writes "); + + armv4_5_register_commands(cmd_ctx); + + etm_register_commands(cmd_ctx); return ERROR_OK; }