X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=2a0aefca4c8a54035bd279fd37c9dd7b1e24e7d7;hp=909e108f594e904366ef1189c96ed0f8299ee8b3;hb=03ac53a2cfdb7d0715f7060cecf8719068f6fae1;hpb=db7e77237c5a8104b527aeb23a2546b4bab92d8a

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 909e108f59..2a0aefca4c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dominic.Rath@gmx.de                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyvind.harboe@zylin.com                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -58,8 +58,10 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char
  */
 static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
 {
+	LOG_DEBUG("-");
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
+	arm7_9->sw_breakpoint_count = 0;
 	arm7_9->sw_breakpoints_added = 0;
 	arm7_9->wp0_used = 0;
 	arm7_9->wp1_used = arm7_9->wp1_used_default;
@@ -93,6 +95,10 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
 	{
 		LOG_ERROR("BUG: no hardware comparator available");
 	}
+	LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
+			  breakpoint->unique_id,
+			  breakpoint->address,
+			  breakpoint->set );
 }
 
 /**
@@ -118,11 +124,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
 	/* pick a breakpoint unit */
 	if (!arm7_9->wp0_used)
 	{
-		arm7_9->sw_breakpoints_added=1;
+		arm7_9->sw_breakpoints_added = 1;
 		arm7_9->wp0_used = 3;
 	} else if (!arm7_9->wp1_used)
 	{
-		arm7_9->sw_breakpoints_added=2;
+		arm7_9->sw_breakpoints_added = 2;
 		arm7_9->wp1_used = 3;
 	}
 	else
@@ -131,7 +137,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
 		return ERROR_FAIL;
 	}
 
-	if (arm7_9->sw_breakpoints_added==1)
+	if (arm7_9->sw_breakpoints_added == 1)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
@@ -139,7 +145,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 	}
-	else if (arm7_9->sw_breakpoints_added==2)
+	else if (arm7_9->sw_breakpoints_added == 2)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
@@ -152,6 +158,8 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
 		LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 		return ERROR_FAIL;
 	}
+	LOG_DEBUG("SW BP using hw wp: %d",
+			  arm7_9->sw_breakpoints_added );
 
 	return jtag_execute_queue();
 }
@@ -164,8 +172,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
  */
 int arm7_9_setup(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
 	return arm7_9_clear_watchpoints(arm7_9);
 }
@@ -184,18 +191,18 @@ int arm7_9_setup(target_t *target)
  */
 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
+	/* FIXME stop using this routine; just target_to_arm7_9() and
+	 * verify the resulting pointer using a replacement routine
+	 * that emits a usage message.
+	 */
 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
-	{
-		return -1;
-	}
+		return ERROR_TARGET_INVALID;
 
 	if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
-	{
-		return -1;
-	}
+		return ERROR_TARGET_INVALID;
 
 	*armv4_5_p = armv4_5;
 	*arm7_9_p = arm7_9;
@@ -216,9 +223,13 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm
  */
 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	int retval=ERROR_OK;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	int retval = ERROR_OK;
+
+	LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
+			  breakpoint->unique_id,
+			  breakpoint->address,
+			  breakpoint->type);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -232,12 +243,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 
 		/* reassign a hw breakpoint */
-		if (breakpoint->set==0)
+		if (breakpoint->set == 0)
 		{
 			arm7_9_assign_wp(arm7_9, breakpoint);
 		}
 
-		if (breakpoint->set==1)
+		if (breakpoint->set == 1)
 		{
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
@@ -245,7 +256,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
 		}
-		else if (breakpoint->set==2)
+		else if (breakpoint->set == 2)
 		{
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
@@ -259,13 +270,10 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			return ERROR_OK;
 		}
 
-		retval=jtag_execute_queue();
+		retval = jtag_execute_queue();
 	}
 	else if (breakpoint->type == BKPT_SOFT)
 	{
-		if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK)
-			return retval;
-
 		/* did we already set this breakpoint? */
 		if (breakpoint->set)
 			return ERROR_OK;
@@ -290,7 +298,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			}
 			if (verify != arm7_9->arm_bkpt)
 			{
-				LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+				LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 				return ERROR_OK;
 			}
 		}
@@ -314,10 +322,16 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			}
 			if (verify != arm7_9->thumb_bkpt)
 			{
-				LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+				LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 				return ERROR_OK;
 			}
 		}
+
+		if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
+			return retval;
+
+		arm7_9->sw_breakpoint_count++;
+
 		breakpoint->set = 1;
 	}
 
@@ -339,9 +353,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	int retval = ERROR_OK;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+			  breakpoint->unique_id,
+			  breakpoint->address );
 
 	if (!breakpoint->set)
 	{
@@ -351,6 +367,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 
 	if (breakpoint->type == BKPT_HARD)
 	{
+		LOG_DEBUG("BPID: %d Releasing hw wp: %d",
+				  breakpoint->unique_id,
+				  breakpoint->set );
 		if (breakpoint->set == 1)
 		{
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -377,7 +396,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			{
 				return retval;
 			}
-			if (current_instr==arm7_9->arm_bkpt)
+			if (current_instr == arm7_9->arm_bkpt)
 				if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
 				{
 					return retval;
@@ -391,12 +410,26 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 			{
 				return retval;
 			}
-			if (current_instr==arm7_9->thumb_bkpt)
+			if (current_instr == arm7_9->thumb_bkpt)
 				if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
 				{
 					return retval;
 				}
 		}
+
+		if (--arm7_9->sw_breakpoint_count==0)
+		{
+			/* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
+			if (arm7_9->sw_breakpoints_added == 1)
+			{
+				embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
+			}
+			else if (arm7_9->sw_breakpoints_added == 2)
+			{
+				embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
+			}
+		}
+
 		breakpoint->set = 0;
 	}
 
@@ -414,8 +447,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
  */
 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -423,7 +455,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	if (arm7_9->breakpoint_count==0)
+	if (arm7_9->breakpoint_count == 0)
 	{
 		/* make sure we don't have any dangling breakpoints. This is vital upon
 		 * GDB connect/disconnect
@@ -466,10 +498,9 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	int retval = ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
-	if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
+	if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -478,10 +509,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		arm7_9->wp_available++;
 
 	arm7_9->breakpoint_count--;
-	if (arm7_9->breakpoint_count==0)
+	if (arm7_9->breakpoint_count == 0)
 	{
 		/* make sure we don't have any dangling breakpoints */
-		if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
+		if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -503,8 +534,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	int retval = ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	int rw_mask = 1;
 	uint32_t mask;
 
@@ -526,12 +556,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
-		if( watchpoint->mask != 0xffffffffu )
+		if (watchpoint->mask != 0xffffffffu)
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -543,12 +573,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
-		if( watchpoint->mask != 0xffffffffu )
+		if (watchpoint->mask != 0xffffffffu)
 			embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -575,8 +605,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	int retval = ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -593,7 +622,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	if (watchpoint->set == 1)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -602,7 +631,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	else if (watchpoint->set == 2)
 	{
 		embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-		if((retval = jtag_execute_queue()) != ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -623,8 +652,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
  */
 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -658,12 +686,11 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	int retval = ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
 	if (watchpoint->set)
 	{
-		if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
+		if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -686,9 +713,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 int arm7_9_execute_sys_speed(struct target_s *target)
 {
 	int retval;
-
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
@@ -700,9 +725,9 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 	}
 	arm_jtag_set_instr(jtag_info, 0x4, NULL);
 
-	long long then=timeval_ms();
+	long long then = timeval_ms();
 	int timeout;
-	while (!(timeout=((timeval_ms()-then)>1000)))
+	while (!(timeout = ((timeval_ms()-then) > 1000)))
 	{
 		/* read debug status register */
 		embeddedice_read_reg(dbg_stat);
@@ -711,7 +736,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 		if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
 				   && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
 			break;
-		if (debug_level>=3)
+		if (debug_level >= 3)
 		{
 			alive_sleep(100);
 		} else
@@ -721,7 +746,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 	}
 	if (timeout)
 	{
-		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
+		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 		return ERROR_TARGET_TIMEOUT;
 	}
 
@@ -738,11 +763,10 @@ int arm7_9_execute_sys_speed(struct target_s *target)
  */
 int arm7_9_execute_fast_sys_speed(struct target_s *target)
 {
-	static int set=0;
+	static int set = 0;
 	static uint8_t check_value[4], check_mask[4];
 
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
@@ -764,7 +788,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 		 * */
 		buf_set_u32(check_value, 0, 32, 0x9);
 		buf_set_u32(check_mask, 0, 32, 0x9);
-		set=1;
+		set = 1;
 	}
 
 	/* read debug status register */
@@ -783,8 +807,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
  */
 int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	uint32_t *data;
 	int retval = ERROR_OK;
@@ -820,8 +843,7 @@ int arm7_9_handle_target_request(void *priv)
 	target_t *target = priv;
 	if (!target_was_examined(target))
 		return ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 	reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
 
@@ -862,11 +884,11 @@ int arm7_9_handle_target_request(void *priv)
  * what happens:
  *
  * <table>
- * 		<tr><th>State</th><th>Action</th></tr>
- * 		<tr><td>TARGET_RUNNING | TARGET_RESET</td><td>Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
- * 		<tr><td>TARGET_UNKNOWN</td><td>Warning is logged</td></tr>
- * 		<tr><td>TARGET_DEBUG_RUNNING</td><td>Enters debug mode</td></tr>
- * 		<tr><td>TARGET_HALTED</td><td>Nothing</td></tr>
+ * 		<tr><th > State</th><th > Action</th></tr>
+ * 		<tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
+ * 		<tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
+ * 		<tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
+ * 		<tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
  * </table>
  *
  * If the target does not end up in the halted state, a warning is produced.  If
@@ -879,8 +901,7 @@ int arm7_9_handle_target_request(void *priv)
 int arm7_9_poll(target_t *target)
 {
 	int retval;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
 	/* read debug status register */
@@ -895,18 +916,19 @@ int arm7_9_poll(target_t *target)
 /*		LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
 		if (target->state == TARGET_UNKNOWN)
 		{
+			/* Starting OpenOCD with target in debug-halt */
 			target->state = TARGET_RUNNING;
-			LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
+			LOG_DEBUG("DBGACK already set during server startup.");
 		}
 		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 		{
-			int check_pc=0;
+			int check_pc = 0;
 			if (target->state == TARGET_RESET)
 			{
 				if (target->reset_halt)
 				{
 					enum reset_types jtag_reset_config = jtag_get_reset_config();
-					if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)
+					if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
 					{
 						check_pc = 1;
 					}
@@ -922,7 +944,7 @@ int arm7_9_poll(target_t *target)
 			{
 				reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
 				uint32_t t=*((uint32_t *)reg->value);
-				if (t!=0)
+				if (t != 0)
 				{
 					LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
 				}
@@ -971,10 +993,10 @@ int arm7_9_poll(target_t *target)
  */
 int arm7_9_assert_reset(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+
 	LOG_DEBUG("target->state: %s",
-		  Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+		  target_state_name(target));
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -983,6 +1005,24 @@ int arm7_9_assert_reset(target_t *target)
 		return ERROR_FAIL;
 	}
 
+	/* At this point trst has been asserted/deasserted once. We would
+	 * like to program EmbeddedICE while SRST is asserted, instead of
+	 * depending on SRST to leave that module alone.  However, many CPUs
+	 * gate the JTAG clock while SRST is asserted; or JTAG may need
+	 * clock stability guarantees (adaptive clocking might help).
+	 *
+	 * So we assume JTAG access during SRST is off the menu unless it's
+	 * been specifically enabled.
+	 */
+	bool srst_asserted = false;
+
+	if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
+			&& (jtag_reset_config & RESET_SRST_NO_GATING))
+	{
+		jtag_add_reset(0, 1);
+		srst_asserted = true;
+	}
+
 	if (target->reset_halt)
 	{
 		/*
@@ -996,6 +1036,9 @@ int arm7_9_assert_reset(target_t *target)
 		{
 			/* program vector catch register to catch reset vector */
 			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+
+			/* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
+			jtag_add_runtest(1, jtag_get_end_state());
 		}
 		else
 		{
@@ -1012,7 +1055,7 @@ int arm7_9_assert_reset(target_t *target)
 	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
 		jtag_add_reset(1, 1);
-	} else
+	} else if (!srst_asserted)
 	{
 		jtag_add_reset(0, 1);
 	}
@@ -1022,7 +1065,7 @@ int arm7_9_assert_reset(target_t *target)
 
 	armv4_5_invalidate_core_regs(target);
 
-	if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0))
+	if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
 	{
 		/* debug entry was already prepared in arm7_9_assert_reset() */
 		target->debug_reason = DBG_REASON_DBGRQ;
@@ -1042,27 +1085,27 @@ int arm7_9_assert_reset(target_t *target)
  */
 int arm7_9_deassert_reset(target_t *target)
 {
-	int retval=ERROR_OK;
+	int retval = ERROR_OK;
 	LOG_DEBUG("target->state: %s",
-		Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+		target_state_name(target));
 
 	/* deassert reset lines */
 	jtag_add_reset(0, 0);
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
-	if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
+	if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
 	{
 		LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
 		/* set up embedded ice registers again */
 		if ((retval = target_examine_one(target)) != ERROR_OK)
 			return retval;
 
-		if ((retval=target_poll(target))!=ERROR_OK)
+		if ((retval = target_poll(target)) != ERROR_OK)
 		{
 			return retval;
 		}
 
-		if ((retval=target_halt(target))!=ERROR_OK)
+		if ((retval = target_halt(target)) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -1082,8 +1125,7 @@ int arm7_9_deassert_reset(target_t *target)
  */
 int arm7_9_clear_halt(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 	/* we used DBGRQ only if we didn't come out of reset */
@@ -1140,26 +1182,33 @@ int arm7_9_clear_halt(target_t *target)
  */
 int arm7_9_soft_reset_halt(struct target_s *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int i;
 	int retval;
 
-	if ((retval=target_halt(target))!=ERROR_OK)
+	/* FIX!!! replace some of this code with tcl commands
+	 *
+	 * halt # the halt command is synchronous
+	 * armv4_5 core_state arm
+	 *
+	 */
+
+	if ((retval = target_halt(target)) != ERROR_OK)
 		return retval;
 
-	long long then=timeval_ms();
+	long long then = timeval_ms();
 	int timeout;
-	while (!(timeout=((timeval_ms()-then)>1000)))
+	while (!(timeout = ((timeval_ms()-then) > 1000)))
 	{
 		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
 			break;
 		embeddedice_read_reg(dbg_stat);
-		if ((retval=jtag_execute_queue())!=ERROR_OK)
+		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
-		if (debug_level>=3)
+		if (debug_level >= 3)
 		{
 			alive_sleep(100);
 		} else
@@ -1246,18 +1295,17 @@ int arm7_9_soft_reset_halt(struct target_s *target)
  */
 int arm7_9_halt(target_t *target)
 {
-	if (target->state==TARGET_RESET)
+	if (target->state == TARGET_RESET)
 	{
 		LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
 		return ERROR_OK;
 	}
 
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 	LOG_DEBUG("target->state: %s",
-		  Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name);
+		  target_state_name(target));
 
 	if (target->state == TARGET_HALTED)
 	{
@@ -1315,9 +1363,8 @@ int arm7_9_debug_entry(target_t *target)
 	uint32_t r0_thumb, pc_thumb;
 	uint32_t cpsr;
 	int retval;
-	/* get pointers to arch-specific information */
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
@@ -1325,9 +1372,6 @@ int arm7_9_debug_entry(target_t *target)
 	LOG_DEBUG("-");
 #endif
 
-	if (arm7_9->pre_debug_entry)
-		arm7_9->pre_debug_entry(target);
-
 	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
 	 * ensure that DBGRQ is cleared
 	 */
@@ -1363,7 +1407,7 @@ int arm7_9_debug_entry(target_t *target)
 		/* Entered debug from Thumb mode */
 		armv4_5->core_state = ARMV4_5_STATE_THUMB;
 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
-		LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
+		LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
 	}
 	else
 	{
@@ -1412,31 +1456,23 @@ int arm7_9_debug_entry(target_t *target)
 		context[15] -= 3 * 4;
 	}
 
-	if ((target->debug_reason == DBG_REASON_BREAKPOINT)
-			|| (target->debug_reason == DBG_REASON_SINGLESTEP)
-			|| (target->debug_reason == DBG_REASON_WATCHPOINT)
-			|| (target->debug_reason == DBG_REASON_WPTANDBKPT)
-			|| ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
+	if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
 		context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
-	else if (target->debug_reason == DBG_REASON_DBGRQ)
-		context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 	else
-	{
-		LOG_ERROR("unknown debug reason: %i", target->debug_reason);
-	}
+		context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
-	for (i=0; i<=15; i++)
+	for (i = 0; i <= 15; i++)
 	{
-		LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
+		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 	}
 
-	LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
+	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
@@ -1481,8 +1517,8 @@ int arm7_9_full_context(target_t *target)
 {
 	int i;
 	int retval;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
 	LOG_DEBUG("-");
 
@@ -1572,8 +1608,8 @@ int arm7_9_full_context(target_t *target)
  */
 int arm7_9_restore_context(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	reg_t *reg;
 	armv4_5_core_reg_t *reg_arch_info;
 	enum armv4_5_mode current_mode = armv4_5->core_mode;
@@ -1662,7 +1698,7 @@ int arm7_9_restore_context(target_t *target)
 					num_regs++;
 					reg->dirty = 0;
 					reg->valid = 1;
-					LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
+					LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
 				}
 			}
 
@@ -1675,7 +1711,7 @@ int arm7_9_restore_context(target_t *target)
 			reg_arch_info = reg->arch_info;
 			if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
 			{
-				LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
+				LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
 				arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
 			}
 		}
@@ -1689,20 +1725,20 @@ int arm7_9_restore_context(target_t *target)
 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 		tmp_cpsr |= armv4_5_number_to_mode(i);
 		tmp_cpsr &= ~0x20;
-		LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
+		LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 	}
 	else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
 	{
 		/* CPSR has been changed, full restore necessary (mask T bit) */
-		LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+		LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
 		arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 	}
 
 	/* restore PC */
-	LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+	LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 	arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 	armv4_5->core_cache->reg_list[15].dirty = 0;
 
@@ -1722,8 +1758,7 @@ int arm7_9_restore_context(target_t *target)
  */
 int arm7_9_restart_core(struct target_s *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
 	/* set RESTART instruction */
@@ -1776,8 +1811,8 @@ void arm7_9_enable_breakpoints(struct target_s *target)
 
 int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	breakpoint_t *breakpoint = target->breakpoints;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int err, retval = ERROR_OK;
@@ -1807,7 +1842,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
 	{
 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
 		{
-			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+			LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
 			if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
 			{
 				return retval;
@@ -1819,7 +1854,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
 			{
 				uint32_t current_opcode;
 				target_read_u32(target, current_pc, &current_opcode);
-				LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+				LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
 				return retval;
 			}
 
@@ -1863,9 +1898,9 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
 			}
 
 			arm7_9_debug_entry(target);
-			LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+			LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 
-			LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
+			LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 			if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
 			{
 				return retval;
@@ -1936,13 +1971,12 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha
 
 void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	uint32_t current_pc;
 	current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
 
-	if(next_pc != current_pc)
+	if (next_pc != current_pc)
 	{
 		/* setup an inverse breakpoint on the current PC
 		* - comparator 1 matches the current address
@@ -1951,7 +1985,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff);
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
@@ -1974,8 +2008,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc)
 
 void arm7_9_disable_eice_step(target_t *target)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
 	embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
@@ -1990,8 +2023,8 @@ void arm7_9_disable_eice_step(target_t *target)
 
 int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	breakpoint_t *breakpoint = NULL;
 	int err, retval;
 
@@ -2024,7 +2057,7 @@ int arm7_9_step(struct target_s *target, int current, uint32_t address, int hand
 	{
 		uint32_t current_opcode;
 		target_read_u32(target, current_pc, &current_opcode);
-		LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+		LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
 		return retval;
 	}
 
@@ -2086,8 +2119,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 	uint32_t* reg_p[16];
 	uint32_t value;
 	int retval;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
@@ -2150,8 +2183,8 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
 {
 	uint32_t reg[16];
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
@@ -2210,9 +2243,8 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
 
 int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	uint32_t reg[16];
 	uint32_t num_accesses = 0;
 	int thisrun_accesses;
@@ -2221,7 +2253,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 	int retval;
 	int last_reg = 0;
 
-	LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -2240,7 +2272,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 	reg[0] = address;
 	arm7_9->write_core_regs(target, 0x1, reg);
 
-	int j=0;
+	int j = 0;
 
 	switch (size)
 	{
@@ -2272,7 +2304,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 				buffer += thisrun_accesses * 4;
 				num_accesses += thisrun_accesses;
 
-				if ((j++%1024)==0)
+				if ((j++%1024) == 0)
 				{
 					keep_alive();
 				}
@@ -2297,7 +2329,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 						retval = arm7_9_execute_fast_sys_speed(target);
 					else
 						retval = arm7_9_execute_sys_speed(target);
-					if(retval != ERROR_OK)
+					if (retval != ERROR_OK)
 					{
 						return retval;
 					}
@@ -2310,7 +2342,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 				buffer += thisrun_accesses * 2;
 				num_accesses += thisrun_accesses;
 
-				if ((j++%1024)==0)
+				if ((j++%1024) == 0)
 				{
 					keep_alive();
 				}
@@ -2335,7 +2367,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 						retval = arm7_9_execute_fast_sys_speed(target);
 					else
 						retval = arm7_9_execute_sys_speed(target);
-					if(retval != ERROR_OK)
+					if (retval != ERROR_OK)
 					{
 						return retval;
 					}
@@ -2347,7 +2379,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 				buffer += thisrun_accesses * 1;
 				num_accesses += thisrun_accesses;
 
-				if ((j++%1024)==0)
+				if ((j++%1024) == 0)
 				{
 					keep_alive();
 				}
@@ -2362,7 +2394,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
-	for (i=0; i<=last_reg; i++)
+	for (i = 0; i <= last_reg; i++)
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
 	arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2374,7 +2406,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 
 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
 	{
-		LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+		LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2386,8 +2418,8 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 
 int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
+	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 	uint32_t reg[16];
@@ -2451,7 +2483,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 					retval = arm7_9_execute_fast_sys_speed(target);
 				else
 					retval = arm7_9_execute_sys_speed(target);
-				if(retval != ERROR_OK)
+				if (retval != ERROR_OK)
 				{
 					return retval;
 				}
@@ -2487,7 +2519,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 						retval = arm7_9_execute_fast_sys_speed(target);
 					else
 						retval = arm7_9_execute_sys_speed(target);
-					if(retval != ERROR_OK)
+					if (retval != ERROR_OK)
 					{
 						return retval;
 					}
@@ -2522,7 +2554,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 						retval = arm7_9_execute_fast_sys_speed(target);
 					else
 						retval = arm7_9_execute_sys_speed(target);
-					if(retval != ERROR_OK)
+					if (retval != ERROR_OK)
 					{
 						return retval;
 					}
@@ -2545,7 +2577,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
 
-	for (i=0; i<=last_reg; i++)
+	for (i = 0; i <= last_reg; i++)
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
 
 	arm7_9->read_xpsr(target, &cpsr, 0);
@@ -2557,7 +2589,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size
 
 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
 	{
-		LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+		LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2573,21 +2605,20 @@ static uint8_t *dcc_buffer;
 static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
 	int retval = ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 
-	if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK)
+	if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
 		return retval;
 
-	int little=target->endianness==TARGET_LITTLE_ENDIAN;
-	int count=dcc_count;
-	uint8_t *buffer=dcc_buffer;
-	if (count>2)
+	int little = target->endianness == TARGET_LITTLE_ENDIAN;
+	int count = dcc_count;
+	uint8_t *buffer = dcc_buffer;
+	if (count > 2)
 	{
 		/* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
 		 * core function repeated. */
 		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
-		buffer+=4;
+		buffer += 4;
 
 		embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
 		uint8_t reg_addr = ice_reg->addr & 0x1f;
@@ -2608,7 +2639,7 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
 		}
 	}
 
-	if((retval = target_halt(target))!= ERROR_OK)
+	if ((retval = target_halt(target))!= ERROR_OK)
 	{
 		return retval;
 	}
@@ -2617,8 +2648,21 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i
 
 static const uint32_t dcc_code[] =
 {
-	/* MRC      TST         BNE         MRC         STR         B */
-	0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
+	/* r0 == input, points to memory buffer
+	 * r1 == scratch
+	 */
+
+	/* spin until DCC control (c0) reports data arrived */
+	0xee101e10,	/* w: mrc p14, #0, r1, c0, c0 */
+	0xe3110001,	/*    tst r1, #1              */
+	0x0afffffc,	/*    bne w                   */
+
+	/* read word from DCC (c1), write to memory */
+	0xee111e10,	/*    mrc p14, #0, r1, c1, c0 */
+	0xe4801004,	/*    str r1, [r0], #4        */
+
+	/* repeat */
+	0xeafffff9	/*    b   w                   */
 };
 
 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
@@ -2626,8 +2670,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
 int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	int retval;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target);
 	int i;
 
 	if (!arm7_9->dcc_downloads)
@@ -2669,18 +2712,18 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count,
 
 	buf_set_u32(reg_params[0].value, 0, 32, address);
 
-	dcc_count=count;
-	dcc_buffer=buffer;
+	dcc_count = count;
+	dcc_buffer = buffer;
 	retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
-			arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+			arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
 
-	if (retval==ERROR_OK)
+	if (retval == ERROR_OK)
 	{
-		uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
-		if (endaddress!=(address+count*4))
+		uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
+		if (endaddress != (address + count*4))
 		{
-			LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
-			retval=ERROR_FAIL;
+			LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
+			retval = ERROR_FAIL;
 		}
 	}
 
@@ -2696,7 +2739,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
 	reg_param_t reg_params[2];
 	int retval;
 
-	uint32_t arm7_9_crc_code[] = {
+	static const uint32_t arm7_9_crc_code[] = {
 		0xE1A02000,				/* mov		r2, r0 */
 		0xE3E00000,				/* mov		r0, #0xffffffff */
 		0xE1A03001,				/* mov		r3, r1 */
@@ -2734,7 +2777,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
 	/* convert flash writing code into a buffer in target endianness */
 	for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
 	{
-		if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i]))!=ERROR_OK)
+		if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
 		{
 			return retval;
 		}
@@ -2750,8 +2793,11 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c
 	buf_set_u32(reg_params[0].value, 0, 32, address);
 	buf_set_u32(reg_params[1].value, 0, 32, count);
 
+	/* 20 second timeout/megabyte */
+	int timeout = 20000 * (1 + (count / (1024*1024)));
+
 	if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
-		crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
+		crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), timeout, &armv4_5_info)) != ERROR_OK)
 	{
 		LOG_ERROR("error executing arm7_9 crc algorithm");
 		destroy_reg_param(&reg_params[0]);
@@ -2778,15 +2824,15 @@ int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_
 	int retval;
 	uint32_t i;
 
-	uint32_t erase_check_code[] =
+	static const uint32_t erase_check_code[] =
 	{
-						/* loop: */
-		0xe4d03001,		/* ldrb r3, [r0], #1	*/
-		0xe0022003,		/* and r2, r2, r3 		*/
-		0xe2511001, 	/* subs r1, r1, #1		*/
-		0x1afffffb,		/* bne loop				*/
-						/* end: */
-		0xeafffffe		/* b end				*/
+		/* loop: */
+		0xe4d03001,		/* ldrb r3, [r0], #1 */
+		0xe0022003,		/* and r2, r2, r3    */
+		0xe2511001,		/* subs r1, r1, #1   */
+		0x1afffffb,		/* bne loop          */
+		/* end: */
+		0xeafffffe		/* b end             */
 	};
 
 	/* make sure we have a working area */
@@ -2842,17 +2888,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 
 	arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
 
-	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
-	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
+	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr | spsr>");
+	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr | spsr>");
 
 	register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
 
 	register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
-		COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
+		COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable | disable>");
 	register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
-		 COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable|disable>");
+		 COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable | disable>");
 	register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
-		COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
+		COMMAND_ANY, "use DCC downloads for larger memory writes <enable | disable>");
 
 	armv4_5_register_commands(cmd_ctx);
 
@@ -2884,12 +2930,12 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
 
 	if (argc < 2)
 	{
-		command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
+		command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr | spsr>");
 		return ERROR_OK;
 	}
 
-	value = strtoul(args[0], NULL, 0);
-	spsr = strtol(args[1], NULL, 0);
+	COMMAND_PARSE_NUMBER(u32, args[0], value);
+	COMMAND_PARSE_NUMBER(int, args[1], spsr);
 
 	/* if we're writing the CPSR, mask the T bit */
 	if (!spsr)
@@ -2929,13 +2975,13 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
 
 	if (argc < 3)
 	{
-		command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
+		command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr | spsr>");
 		return ERROR_OK;
 	}
 
-	value = strtoul(args[0], NULL, 0);
-	rotate = strtol(args[1], NULL, 0);
-	spsr = strtol(args[2], NULL, 0);
+	COMMAND_PARSE_NUMBER(u32, args[0], value);
+	COMMAND_PARSE_NUMBER(int, args[1], rotate);
+	COMMAND_PARSE_NUMBER(int, args[2], spsr);
 
 	arm7_9->write_xpsr_im8(target, value, rotate, spsr);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2974,9 +3020,9 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char
 		return ERROR_OK;
 	}
 
-	num = strtol(args[0], NULL, 0);
-	mode = strtoul(args[1], NULL, 0);
-	value = strtoul(args[2], NULL, 0);
+	COMMAND_PARSE_NUMBER(int, args[0], num);
+	COMMAND_PARSE_NUMBER(u32, args[1], mode);
+	COMMAND_PARSE_NUMBER(u32, args[2], value);
 
 	return arm7_9_write_core_reg(target, num, mode, value);
 }
@@ -3005,7 +3051,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch
 		}
 		else
 		{
-			command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
+			command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable | disable>");
 		}
 	}
 
@@ -3038,7 +3084,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx,
 		}
 		else
 		{
-			command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
+			command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable | disable>");
 		}
 	}
 
@@ -3071,7 +3117,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
 		}
 		else
 		{
-			command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
+			command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable | disable>");
 		}
 	}
 
@@ -3087,7 +3133,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 
 	arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
-	if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+	if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -3095,6 +3141,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 	arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
 	arm7_9->wp_available_max = 2;
 	arm7_9->sw_breakpoints_added = 0;
+	arm7_9->sw_breakpoint_count = 0;
 	arm7_9->breakpoint_count = 0;
 	arm7_9->wp0_used = 0;
 	arm7_9->wp1_used = 0;
@@ -3120,12 +3167,12 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 	armv4_5->write_core_reg = arm7_9_write_core_reg;
 	armv4_5->full_context = arm7_9_full_context;
 
-	if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+	if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
 	{
 		return retval;
 	}
 
-	if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
+	if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK)
 	{
 		return retval;
 	}