X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=35cbe6e50785fc2cd28cfd051fbcea08641542c5;hp=8e74dedab29711b40cdcea892d2f5891e73b7808;hb=20e4e77cdf366dedac21ff5670c54291feadfc05;hpb=4fc97d3f2726efa147cfdb0c456eace51550e1e3 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 8e74dedab2..35cbe6e507 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -25,6 +25,7 @@ #include "embeddedice.h" #include "target.h" +#include "target_request.h" #include "armv4_5.h" #include "arm_jtag.h" #include "jtag.h" @@ -54,6 +55,7 @@ int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int arm7_9_reinit_embeddedice(target_t *target) { @@ -186,15 +188,15 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { /* keep the original instruction in target endianness */ target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr); - /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ + /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */ target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt); } else { /* keep the original instruction in target endianness */ target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); - /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */ - target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt); + /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */ + target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt); } breakpoint->set = 1; } @@ -543,7 +545,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) /* set RESTART instruction */ jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, 0x4); + arm_jtag_set_instr(jtag_info, 0x4, NULL); for (timeout=0; timeout<50; timeout++) { @@ -576,7 +578,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) /* set RESTART instruction */ jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, 0x4); + arm_jtag_set_instr(jtag_info, 0x4, NULL); /* check for DBGACK and SYSCOMP set (others don't care) */ buf_set_u32(check_value, 0, 32, 0x9); @@ -588,6 +590,55 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) return ERROR_OK; } +int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + arm_jtag_t *jtag_info = &arm7_9->jtag_info; + u32 *data; + int i; + + data = malloc(size * (sizeof(u32))); + + embeddedice_receive(jtag_info, data, size); + + for (i = 0; i < size; i++) + { + h_u32_to_le(buffer + (i * 4), data[i]); + } + + free(data); + + return ERROR_OK; +} + +int arm7_9_handle_target_request(void *priv) +{ + target_t *target = priv; + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + arm_jtag_t *jtag_info = &arm7_9->jtag_info; + reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; + + if (target->state == TARGET_RUNNING) + { + /* read DCC control register */ + embeddedice_read_reg(dcc_control); + jtag_execute_queue(); + + /* check W bit */ + if (buf_get_u32(dcc_control->value, 1, 1) == 1) + { + u32 request; + + embeddedice_receive(jtag_info, &request, 1); + target_request(target, request); + } + } + + return ERROR_OK; +} + enum target_state arm7_9_poll(target_t *target) { int retval; @@ -723,9 +774,8 @@ int arm7_9_deassert_reset(target_t *target) /* deassert reset lines */ jtag_add_reset(0, 0); - + return ERROR_OK; - } int arm7_9_clear_halt(target_t *target) @@ -734,7 +784,8 @@ int arm7_9_clear_halt(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - if (arm7_9->use_dbgrq) + /* we used DBGRQ only if we didn't come out of reset */ + if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq) { /* program EmbeddedICE Debug Control Register to deassert DBGRQ */ @@ -743,18 +794,29 @@ int arm7_9_clear_halt(target_t *target) } else { - /* restore registers if watchpoint unit 0 was in use - */ - if (arm7_9->wp0_used) + if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch) { - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]); - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]); + /* if we came out of reset, and vector catch is supported, we used + * vector catch to enter debug state + * restore the register in that case + */ + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]); + } + else + { + /* restore registers if watchpoint unit 0 was in use + */ + if (arm7_9->wp0_used) + { + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]); + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]); + } + /* control value always has to be restored, as it was either disabled, + * or enabled with possibly different bits + */ + embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]); } - /* control value always has to be restored, as it was either disabled, - * or enabled with possibly different bits - */ - embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]); } return ERROR_OK; @@ -773,7 +835,7 @@ int arm7_9_soft_reset_halt(struct target_s *target) target->type->halt(target); } - while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0) + while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); jtag_execute_queue(); @@ -829,6 +891,35 @@ int arm7_9_soft_reset_halt(struct target_s *target) return ERROR_OK; } +int arm7_9_prepare_reset_halt(target_t *target) +{ + armv4_5_common_t *armv4_5 = target->arch_info; + arm7_9_common_t *arm7_9 = armv4_5->arch_info; + + /* poll the target, and resume if it was currently halted */ + arm7_9_poll(target); + if (target->state == TARGET_HALTED) + { + arm7_9_resume(target, 1, 0x0, 0, 1); + } + + if (arm7_9->has_vector_catch) + { + /* program vector catch register to catch reset vector */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1); + } + else + { + /* program watchpoint unit to match on reset vector address */ + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7); + } + + return ERROR_OK; +} + int arm7_9_halt(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -841,17 +932,29 @@ int arm7_9_halt(target_t *target) { WARNING("target was already halted"); return ERROR_TARGET_ALREADY_HALTED; - } + } if (target->state == TARGET_UNKNOWN) { WARNING("target was in unknown state when halt was requested"); } - if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst)) + if (target->state == TARGET_RESET) { - ERROR("can't request a halt while in reset if nSRST pulls nTRST"); - return ERROR_TARGET_FAILURE; + if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) + { + ERROR("can't request a halt while in reset if nSRST pulls nTRST"); + return ERROR_TARGET_FAILURE; + } + else + { + /* we came here in a reset_halt or reset_init sequence + * debug entry was already prepared in arm7_9_prepare_reset_halt() + */ + target->debug_reason = DBG_REASON_DBGRQ; + + return ERROR_OK; + } } if (arm7_9->use_dbgrq) @@ -891,7 +994,7 @@ int arm7_9_debug_entry(target_t *target) reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; #ifdef _DEBUG_ARM7_9_ - DEBUG(""); + DEBUG("-"); #endif if (arm7_9->pre_debug_entry) @@ -1041,7 +1144,7 @@ int arm7_9_full_context(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - DEBUG(""); + DEBUG("-"); if (target->state != TARGET_HALTED) { @@ -1124,7 +1227,7 @@ int arm7_9_restore_context(target_t *target) int dirty; int mode_change; - DEBUG(""); + DEBUG("-"); if (target->state != TARGET_HALTED) { @@ -1261,7 +1364,7 @@ int arm7_9_restart_core(struct target_s *target) /* set RESTART instruction */ jtag_add_end_state(TAP_RTI); - arm_jtag_set_instr(jtag_info, 0x4); + arm_jtag_set_instr(jtag_info, 0x4, NULL); jtag_add_runtest(1, TAP_RTI); if ((jtag_execute_queue()) != ERROR_OK) @@ -1325,7 +1428,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ breakpoint_t *breakpoint = target->breakpoints; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - DEBUG(""); + DEBUG("-"); if (target->state != TARGET_HALTED) { @@ -2049,7 +2152,7 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) command_t *arm7_9_cmd; arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands"); - + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); @@ -2068,6 +2171,8 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) armv4_5_register_commands(cmd_ctx); + etm_register_commands(cmd_ctx); + return ERROR_OK; } @@ -2389,13 +2494,15 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) arm7_9->force_hw_bkpts = 0; arm7_9->use_dbgrq = 0; - arm7_9->has_etm = 0; + arm7_9->etm_ctx = NULL; arm7_9->has_single_step = 0; arm7_9->has_monitor_mode = 0; arm7_9->has_vector_catch = 0; arm7_9->reinit_embeddedice = 0; + arm7_9->debug_entry_from_reset = 0; + arm7_9->dcc_working_area = NULL; arm7_9->fast_memory_access = 0; @@ -2410,5 +2517,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) armv4_5_init_arch_info(target, armv4_5); + target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target); + return ERROR_OK; }