X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=35cbe6e50785fc2cd28cfd051fbcea08641542c5;hp=b793ba51531a1b359b48bb58edcc178b4487b921;hb=20e4e77cdf366dedac21ff5670c54291feadfc05;hpb=e8ead33804f1aede5157a5afc1bc249038799e6b

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b793ba5153..35cbe6e507 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -25,6 +25,7 @@
 
 #include "embeddedice.h"
 #include "target.h"
+#include "target_request.h"
 #include "armv4_5.h"
 #include "arm_jtag.h"
 #include "jtag.h"
@@ -54,6 +55,7 @@ int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char
 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
 int arm7_9_reinit_embeddedice(target_t *target)
 {
@@ -186,15 +188,15 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 		{
 			/* keep the original instruction in target endianness */
 			target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
-			/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
+			/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 			target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
 		}
 		else
 		{
 			/* keep the original instruction in target endianness */
 			target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
-			/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
-			target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
+			/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
+			target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
 		}
 		breakpoint->set = 1;
 	}
@@ -253,7 +255,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	return ERROR_OK;
 }
 
-int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum breakpoint_type type)
+int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -266,30 +268,31 @@ int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum
 	
 	if (arm7_9->force_hw_bkpts)
 	{
-		type = BKPT_HARD;
+		DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
+		breakpoint->type = BKPT_HARD;
 	}
 	
-	if ((type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
+	if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
 	{
 		INFO("sw breakpoint requested, but software breakpoints not enabled");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 	
-	if ((type == BKPT_HARD) && (arm7_9->wp_available < 1))
+	if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
 	{
 		INFO("no watchpoint unit available for hardware breakpoint");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 	
-	if (type == BKPT_HARD)
-		arm7_9->wp_available--;
-	
-	if ((length != 2) && (length != 4))
+	if ((breakpoint->length != 2) && (breakpoint->length != 4))
 	{
 		INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 	
+	if (breakpoint->type == BKPT_HARD)
+		arm7_9->wp_available--;
+	
 	return ERROR_OK;
 }
 
@@ -406,7 +409,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	return ERROR_OK;
 }
 
-int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw)
+int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -422,7 +425,7 @@ int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 	
-	if ((length != 1) && (length != 2) && (length != 4))
+	if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
 	{
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
@@ -542,7 +545,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
 				
 	/* set RESTART instruction */
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_set_instr(jtag_info, 0x4);
+	arm_jtag_set_instr(jtag_info, 0x4, NULL);
 	
 	for (timeout=0; timeout<50; timeout++)
 	{
@@ -575,7 +578,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 				
 	/* set RESTART instruction */
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_set_instr(jtag_info, 0x4);
+	arm_jtag_set_instr(jtag_info, 0x4, NULL);
 	
 	/* check for DBGACK and SYSCOMP set (others don't care) */
 	buf_set_u32(check_value, 0, 32, 0x9);
@@ -587,6 +590,55 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target)
 	return ERROR_OK;
 }
 
+int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer)
+{
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
+	u32 *data;
+	int i;
+	
+	data = malloc(size * (sizeof(u32)));
+	
+	embeddedice_receive(jtag_info, data, size);
+	
+	for (i = 0; i < size; i++)
+	{
+		h_u32_to_le(buffer + (i * 4), data[i]);
+	}
+	
+	free(data);
+	
+	return ERROR_OK;
+}
+
+int arm7_9_handle_target_request(void *priv)
+{
+	target_t *target = priv;
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	arm_jtag_t *jtag_info = &arm7_9->jtag_info; 
+	reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
+	
+	if (target->state == TARGET_RUNNING)
+	{
+		/* read DCC control register */
+		embeddedice_read_reg(dcc_control);
+		jtag_execute_queue();
+		
+		/* check W bit */
+		if (buf_get_u32(dcc_control->value, 1, 1) == 1)
+		{
+			u32 request;
+			
+			embeddedice_receive(jtag_info, &request, 1);
+			target_request(target, request);
+		}
+	}
+	
+	return ERROR_OK;
+}
+
 enum target_state arm7_9_poll(target_t *target)
 {
 	int retval;
@@ -656,6 +708,9 @@ int arm7_9_assert_reset(target_t *target)
 	
 	if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
 	{
+		/* if the target wasn't running, there might be working areas allocated */
+		target_free_all_working_areas(target);
+		
 		/* assert SRST and TRST */
 		/* system would get ouf sync if we didn't reset test-logic, too */
 		if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
@@ -719,9 +774,52 @@ int arm7_9_deassert_reset(target_t *target)
 	
 	/* deassert reset lines */
 	jtag_add_reset(0, 0);
-		
+	
 	return ERROR_OK;
+}
 
+int arm7_9_clear_halt(target_t *target)
+{
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+	
+	/* we used DBGRQ only if we didn't come out of reset */
+	if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
+	{
+		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
+		 */
+		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
+		embeddedice_store_reg(dbg_ctrl);
+	}
+	else
+	{
+		if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
+		{
+			/* if we came out of reset, and vector catch is supported, we used
+			 * vector catch to enter debug state
+			 * restore the register in that case
+			 */
+			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
+		}
+		else
+		{
+			/* restore registers if watchpoint unit 0 was in use
+			 */
+			if (arm7_9->wp0_used)
+			{
+				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
+				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
+				embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
+			}
+			/* control value always has to be restored, as it was either disabled, 
+			 * or enabled with possibly different bits
+			 */
+			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
+		}
+	}
+	
+	return ERROR_OK;
 }
 
 int arm7_9_soft_reset_halt(struct target_s *target)
@@ -729,6 +827,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	int i;
 	
 	if (target->state == TARGET_RUNNING)
@@ -736,13 +835,33 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 		target->type->halt(target);
 	}
 	
-	while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+	while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 	{
 		embeddedice_read_reg(dbg_stat);
 		jtag_execute_queue();
 	}
 	target->state = TARGET_HALTED;
 	
+	/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
+	 * ensure that DBGRQ is cleared
+	 */
+	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
+	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
+	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
+	embeddedice_store_reg(dbg_ctrl);
+	
+	arm7_9_clear_halt(target);
+	
+	/* if the target is in Thumb state, change to ARM state */
+	if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
+	{
+		u32 r0_thumb, pc_thumb;
+		DEBUG("target entered debug from Thumb state, changing to ARM");
+		/* Entered debug from Thumb mode */
+		armv4_5->core_state = ARMV4_5_STATE_THUMB;
+		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
+	}
+	
 	/* all register content is now invalid */
 	armv4_5_invalidate_core_regs(target);
 	
@@ -772,6 +891,35 @@ int arm7_9_soft_reset_halt(struct target_s *target)
 	return ERROR_OK;
 }
 
+int arm7_9_prepare_reset_halt(target_t *target)
+{
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+	
+	/* poll the target, and resume if it was currently halted */
+	arm7_9_poll(target);
+	if (target->state == TARGET_HALTED)
+	{
+		arm7_9_resume(target, 1, 0x0, 0, 1);
+	}
+	
+	if (arm7_9->has_vector_catch)
+	{
+		/* program vector catch register to catch reset vector */
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+	}
+	else
+	{
+		/* program watchpoint unit to match on reset vector address */
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
+		embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
+	}
+	
+	return ERROR_OK;
+}
+
 int arm7_9_halt(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -784,17 +932,29 @@ int arm7_9_halt(target_t *target)
 	{
 		WARNING("target was already halted");
 		return ERROR_TARGET_ALREADY_HALTED;
-	} 
+	}
 	
 	if (target->state == TARGET_UNKNOWN)
 	{
 		WARNING("target was in unknown state when halt was requested");
 	}
 	
-	if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
+	if (target->state == TARGET_RESET) 
 	{
-		ERROR("can't request a halt while in reset if nSRST pulls nTRST");
-		return ERROR_TARGET_FAILURE;
+		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
+		{
+			ERROR("can't request a halt while in reset if nSRST pulls nTRST");
+			return ERROR_TARGET_FAILURE;
+		}
+		else
+		{
+			/* we came here in a reset_halt or reset_init sequence
+			 * debug entry was already prepared in arm7_9_prepare_reset_halt()
+			 */
+			target->debug_reason = DBG_REASON_DBGRQ;
+			
+			return ERROR_OK; 
+		}
 	}
 
 	if (arm7_9->use_dbgrq)
@@ -819,38 +979,6 @@ int arm7_9_halt(target_t *target)
 	return ERROR_OK;
 }
 
-int arm7_9_clear_halt(target_t *target)
-{
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
-	
-	if (arm7_9->use_dbgrq)
-	{
-		/* program EmbeddedICE Debug Control Register to deassert DBGRQ
-		 */
-		buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);	
-		embeddedice_store_reg(dbg_ctrl);
-	}
-	else
-	{
-		/* restore registers if watchpoint unit 0 was in use
-		 */
-		if (arm7_9->wp0_used)
-		{
-			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
-			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
-			embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
-		}
-		/* control value always has to be restored, as it was either disabled, 
-		 * or enabled with possibly different bits
-		 */
-		embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
-	}
-	
-	return ERROR_OK;
-}
-
 int arm7_9_debug_entry(target_t *target)
 {
 	int i;
@@ -866,7 +994,7 @@ int arm7_9_debug_entry(target_t *target)
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
 #ifdef _DEBUG_ARM7_9_
-	DEBUG("");
+	DEBUG("-");
 #endif
 
 	if (arm7_9->pre_debug_entry)
@@ -1016,7 +1144,7 @@ int arm7_9_full_context(target_t *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-	DEBUG("");
+	DEBUG("-");
 	
 	if (target->state != TARGET_HALTED)
 	{
@@ -1099,7 +1227,7 @@ int arm7_9_restore_context(target_t *target)
 	int dirty;
 	int mode_change;
 	
-	DEBUG("");
+	DEBUG("-");
 	
 	if (target->state != TARGET_HALTED)
 	{
@@ -1236,7 +1364,7 @@ int arm7_9_restart_core(struct target_s *target)
 	
 	/* set RESTART instruction */
 	jtag_add_end_state(TAP_RTI);
-	arm_jtag_set_instr(jtag_info, 0x4);
+	arm_jtag_set_instr(jtag_info, 0x4, NULL);
 	
 	jtag_add_runtest(1, TAP_RTI);
 	if ((jtag_execute_queue()) != ERROR_OK)
@@ -1300,7 +1428,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
 	breakpoint_t *breakpoint = target->breakpoints;
 	reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 	
-	DEBUG("");
+	DEBUG("-");
 	
 	if (target->state != TARGET_HALTED)
 	{
@@ -1448,7 +1576,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
-	breakpoint_t *breakpoint = target->breakpoints;
+	breakpoint_t *breakpoint = NULL;
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -2024,7 +2152,7 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 	command_t *arm7_9_cmd;
 	
 	arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
-	
+
 	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
 	register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
 	
@@ -2043,6 +2171,8 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
 
 	armv4_5_register_commands(cmd_ctx);
 	
+	etm_register_commands(cmd_ctx);
+	
 	return ERROR_OK;
 }
 
@@ -2363,10 +2493,16 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 	arm7_9->wp1_used = 0;
 	arm7_9->force_hw_bkpts = 0;
 	arm7_9->use_dbgrq = 0;
-	arm7_9->has_etm = 0;
+	
+	arm7_9->etm_ctx = NULL;
+	arm7_9->has_single_step = 0;
+	arm7_9->has_monitor_mode = 0;
+	arm7_9->has_vector_catch = 0;
 	
 	arm7_9->reinit_embeddedice = 0;
 	
+	arm7_9->debug_entry_from_reset = 0;
+	
 	arm7_9->dcc_working_area = NULL;
 	
 	arm7_9->fast_memory_access = 0;
@@ -2381,5 +2517,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
 	
 	armv4_5_init_arch_info(target, armv4_5);
 	
+	target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target);
+	
 	return ERROR_OK;
 }