X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=37aa06609d45f2b47bdb32fa065025ac9adb4d3e;hp=b29eb5cc5e71a626f216cd78e7ebf3dffbc27d21;hb=181d401d59419ec2f5a5d89e2600d9a6dbf8f9ed;hpb=2861877b32a7a2f4022a1c3d9b66c9b4879878ac

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b29eb5cc5e..37aa06609d 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1242,9 +1242,6 @@ int arm7_9_soft_reset_halt(struct target *target)
 	armv4_5->core_mode = ARMV4_5_MODE_SVC;
 	armv4_5->core_state = ARMV4_5_STATE_ARM;
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-		return ERROR_FAIL;
-
 	/* reset registers */
 	for (i = 0; i <= 14; i++)
 	{
@@ -1413,14 +1410,15 @@ static int arm7_9_debug_entry(struct target *target)
 
 	armv4_5->core_mode = cpsr & 0x1f;
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+	if (!is_arm_mode(armv4_5->core_mode))
 	{
 		target->state = TARGET_UNKNOWN;
 		LOG_ERROR("cpsr contains invalid mode value - communication failure");
 		return ERROR_TARGET_FAILURE;
 	}
 
-	LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
+	LOG_DEBUG("target entered debug state in %s mode",
+			 arm_mode_name(armv4_5->core_mode));
 
 	if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 	{
@@ -1438,9 +1436,6 @@ static int arm7_9_debug_entry(struct target *target)
 	else
 		context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-		return ERROR_FAIL;
-
 	for (i = 0; i <= 15; i++)
 	{
 		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
@@ -1451,9 +1446,6 @@ static int arm7_9_debug_entry(struct target *target)
 
 	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-		return ERROR_FAIL;
-
 	/* exceptions other than USR & SYS have a saved program status register */
 	if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
 	{
@@ -1505,7 +1497,7 @@ int arm7_9_full_context(struct target *target)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -1605,7 +1597,7 @@ int arm7_9_restore_context(struct target *target)
 	if (arm7_9->pre_restore_context)
 		arm7_9->pre_restore_context(target);
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
 	/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
@@ -1613,7 +1605,8 @@ int arm7_9_restore_context(struct target *target)
 	 */
 	for (i = 0; i < 6; i++)
 	{
-		LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
+		LOG_DEBUG("examining %s mode",
+				arm_mode_name(armv4_5->core_mode));
 		dirty = 0;
 		mode_change = 0;
 		/* check if there are dirty registers in the current mode
@@ -1675,7 +1668,10 @@ int arm7_9_restore_context(struct target *target)
 					num_regs++;
 					reg->dirty = 0;
 					reg->valid = 1;
-					LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
+					LOG_DEBUG("writing register %i mode %s "
+						"with value 0x%8.8" PRIx32, j,
+						arm_mode_name(armv4_5->core_mode),
+						regs[j]);
 				}
 			}
 
@@ -2099,7 +2095,7 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
 	enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -2163,7 +2159,7 @@ int arm7_9_write_core_reg(struct target *target, int num, enum armv4_5_mode mode
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
 	enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
@@ -2368,7 +2364,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
 			break;
 	}
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
 	for (i = 0; i <= last_reg; i++)
@@ -2551,7 +2547,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 	buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
 	embeddedice_store_reg(dbg_ctrl);
 
-	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
+	if (!is_arm_mode(armv4_5->core_mode))
 		return ERROR_FAIL;
 
 	for (i = 0; i <= last_reg; i++)