X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=617ee78406224922c3833e54017b8a383c75dbf2;hp=3461da4c48a3689f93ac5156ce9c600d10197333;hb=dccbf7d88d05a1f7a22f164ef149777718a399ed;hpb=d2d4f776d8e24e8e651d1c896c90c15c38633172 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 3461da4c48..617ee78406 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -26,7 +26,7 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -103,7 +103,7 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br arm7_9->wp_available--; } else LOG_ERROR("BUG: no hardware comparator available"); - LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + LOG_DEBUG("BPID: %" PRId32 " (0x%08" PRIx32 ") using hw wp: %d", breakpoint->unique_id, breakpoint->address, breakpoint->set); @@ -189,7 +189,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d", + LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" PRIx32 ", Type: %d", breakpoint->unique_id, breakpoint->address, breakpoint->type); @@ -301,7 +301,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" PRIx32, breakpoint->unique_id, breakpoint->address); @@ -311,7 +311,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre } if (breakpoint->type == BKPT_HARD) { - LOG_DEBUG("BPID: %d Releasing hw wp: %d", + LOG_DEBUG("BPID: %" PRId32 " Releasing hw wp: %d", breakpoint->unique_id, breakpoint->set); if (breakpoint->set == 1) { @@ -1719,7 +1719,7 @@ int arm7_9_resume(struct target *target, breakpoint = breakpoint_find(target, buf_get_u32(arm->pc->value, 0, 32)); if (breakpoint != NULL) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %" PRId32, breakpoint->address, breakpoint->unique_id); retval = arm7_9_unset_breakpoint(target, breakpoint); @@ -2033,7 +2033,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, } static int arm7_9_write_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode, uint32_t value) + int num, enum arm_mode mode, uint8_t *value) { uint32_t reg[16]; struct arm_reg *areg = r->arch_info; @@ -2058,7 +2058,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, if ((num >= 0) && (num <= 15)) { /* write a normal core register */ - reg[num] = value; + reg[num] = buf_get_u32(value, 0, 32); arm7_9->write_core_regs(target, 1 << num, reg); } else { @@ -2067,11 +2067,12 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, */ int spsr = (areg->mode != ARM_MODE_ANY); + uint32_t t = buf_get_u32(value, 0, 32); /* if we're writing the CPSR, mask the T bit */ if (!spsr) - value &= ~0x20; + t &= ~0x20; - arm7_9->write_xpsr(target, value, spsr); + arm7_9->write_xpsr(target, t, spsr); } r->valid = 1; @@ -2469,6 +2470,37 @@ int arm7_9_write_memory(struct target *target, return ERROR_OK; } +int arm7_9_write_memory_opt(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) +{ + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + int retval; + + if (size == 4 && count > 32 && arm7_9->bulk_write_memory) { + /* Attempt to do a bulk write */ + retval = arm7_9->bulk_write_memory(target, address, count, buffer); + + if (retval == ERROR_OK) + return ERROR_OK; + } + + return arm7_9->write_memory(target, address, size, count, buffer); +} + +int arm7_9_write_memory_no_opt(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) +{ + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + + return arm7_9->write_memory(target, address, size, count, buffer); +} + static int dcc_count; static const uint8_t *dcc_buffer; @@ -2545,10 +2577,12 @@ int arm7_9_bulk_write_memory(struct target *target, { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - int i; + + if (address % 4 != 0) + return ERROR_TARGET_UNALIGNED_ACCESS; if (!arm7_9->dcc_downloads) - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; /* regrab previously allocated working_area, or allocate a new one */ if (!arm7_9->dcc_working_area) { @@ -2557,15 +2591,15 @@ int arm7_9_bulk_write_memory(struct target *target, /* make sure we have a working area */ if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* copy target instructions to target endianness */ - for (i = 0; i < 6; i++) - target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); + target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code); - /* write DCC code to working area */ - retval = target_write_memory(target, + /* write DCC code to working area, using the non-optimized + * memory write to avoid ending up here again */ + retval = arm7_9_write_memory_no_opt(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf); if (retval != ERROR_OK) return retval; @@ -2659,6 +2693,46 @@ int arm7_9_check_reset(struct target *target) return ERROR_OK; } +int arm7_9_endianness_callback(jtag_callback_data_t pu8_in, + jtag_callback_data_t i_size, jtag_callback_data_t i_be, + jtag_callback_data_t i_flip) +{ + uint8_t *in = (uint8_t *)pu8_in; + int size = (int)i_size; + int be = (int)i_be; + int flip = (int)i_flip; + uint32_t readback; + + switch (size) { + case 4: + readback = le_to_h_u32(in); + if (flip) + readback = flip_u32(readback, 32); + if (be) + h_u32_to_be(in, readback); + else + h_u32_to_le(in, readback); + break; + case 2: + readback = le_to_h_u16(in); + if (flip) + readback = flip_u32(readback, 16); + if (be) + h_u16_to_be(in, readback & 0xffff); + else + h_u16_to_le(in, readback & 0xffff); + break; + case 1: + readback = *in; + if (flip) + readback = flip_u32(readback, 8); + *in = readback & 0xff; + break; + } + + return ERROR_OK; +} + COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { struct target *target = get_current_target(CMD_CTX); @@ -2766,6 +2840,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) arm7_9->dcc_downloads = false; arm->arch_info = arm7_9; + arm->core_type = ARM_MODE_ANY; arm->read_core_reg = arm7_9_read_core_reg; arm->write_core_reg = arm7_9_write_core_reg; arm->full_context = arm7_9_full_context;