X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=7ad70ea04aeca4cf26f076285303f0cef166f9ef;hp=9f1bb2e64722145d7c17a7b730e568df3835cc60;hb=4668bd264cfe64c3e3ddd0f75cb5bf2e5e85f717;hpb=a8a9eddca0f8f5d8ab73f22c5a159fe1748272d5 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 9f1bb2e647..7ad70ea04a 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007-2009 Øyvind Harboe * + * Copyright (C) 2007-2010 Øyvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * @@ -377,6 +377,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre { return retval; } + current_instr = target_buffer_get_u32(target, (uint8_t *)¤t_instr); if (current_instr == arm7_9->arm_bkpt) if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { @@ -391,6 +392,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre { return retval; } + current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); if (current_instr == arm7_9->thumb_bkpt) if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { @@ -689,9 +691,13 @@ int arm7_9_execute_sys_speed(struct target *target) /* set RESTART instruction */ if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; } - arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; long long then = timeval_ms(); int timeout; @@ -737,13 +743,18 @@ static int arm7_9_execute_fast_sys_speed(struct target *target) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + int retval; /* set RESTART instruction */ if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; } - arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; if (!set) { @@ -1064,24 +1075,29 @@ int arm7_9_deassert_reset(struct target *target) /* deassert reset lines */ jtag_add_reset(0, 0); + /* In case polling is disabled, we need to examine the + * target and poll here for this target to work correctly. + * + * Otherwise, e.g. halt will fail afterwards with bogus + * error messages as halt will believe that reset is + * still in effect. + */ + if ((retval = target_examine_one(target)) != ERROR_OK) + return retval; + + if ((retval = target_poll(target)) != ERROR_OK) + { + return retval; + } + enum reset_types jtag_reset_config = jtag_get_reset_config(); if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) { LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset."); - /* set up embedded ice registers again */ - if ((retval = target_examine_one(target)) != ERROR_OK) - return retval; - - if ((retval = target_poll(target)) != ERROR_OK) - { - return retval; - } - if ((retval = target_halt(target)) != ERROR_OK) { return retval; } - } return retval; } @@ -1469,7 +1485,11 @@ static int arm7_9_debug_entry(struct target *target) return retval; if (arm7_9->post_debug_entry) - arm7_9->post_debug_entry(target); + { + retval = arm7_9->post_debug_entry(target); + if (retval != ERROR_OK) + return retval; + } return ERROR_OK; } @@ -1499,7 +1519,10 @@ static int arm7_9_full_context(struct target *target) } if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS @@ -1584,7 +1607,6 @@ static int arm7_9_restore_context(struct target *target) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *armv4_5 = &arm7_9->armv4_5_common; struct reg *reg; - struct arm_reg *reg_arch_info; enum arm_mode current_mode = armv4_5->core_mode; int i, j; int dirty; @@ -1602,7 +1624,10 @@ static int arm7_9_restore_context(struct target *target) arm7_9->pre_restore_context(target); if (!is_arm_mode(armv4_5->core_mode)) + { + LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; + } /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS @@ -1618,13 +1643,14 @@ static int arm7_9_restore_context(struct target *target) for (j = 0; j <= 16; j++) { reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); - reg_arch_info = reg->arch_info; if (reg->dirty == 1) { if (reg->valid == 1) { dirty = 1; LOG_DEBUG("examining dirty reg: %s", reg->name); + struct arm_reg *reg_arch_info; + reg_arch_info = reg->arch_info; if ((reg_arch_info->mode != ARM_MODE_ANY) && (reg_arch_info->mode != current_mode) && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS)) @@ -1663,8 +1689,6 @@ static int arm7_9_restore_context(struct target *target) for (j = 0; j <= 14; j++) { reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); - reg_arch_info = reg->arch_info; - if (reg->dirty == 1) { @@ -1686,6 +1710,7 @@ static int arm7_9_restore_context(struct target *target) } reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16); + struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) { @@ -1739,13 +1764,19 @@ static int arm7_9_restart_core(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm_jtag *jtag_info = &arm7_9->jtag_info; + int retval; /* set RESTART instruction */ if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; } - arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; jtag_add_runtest(1, TAP_IDLE); return jtag_execute_queue(); @@ -1791,7 +1822,6 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *armv4_5 = &arm7_9->armv4_5_common; - struct breakpoint *breakpoint = target->breakpoints; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; @@ -1818,6 +1848,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { + struct breakpoint *breakpoint; breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->pc->value, 0, 32)); if (breakpoint != NULL) @@ -1877,7 +1908,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand return err; } - arm7_9_debug_entry(target); + retval = arm7_9_debug_entry(target); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("new PC after step: 0x%8.8" PRIx32, buf_get_u32(armv4_5->pc->value, 0, 32)); @@ -2078,7 +2111,9 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle { target->state = TARGET_UNKNOWN; } else { - arm7_9_debug_entry(target); + retval = arm7_9_debug_entry(target); + if (retval != ERROR_OK) + return retval; if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) { return retval; @@ -2099,7 +2134,6 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, int num, enum arm_mode mode) { uint32_t* reg_p[16]; - uint32_t value; int retval; struct arm_reg *areg = r->arch_info; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); @@ -2108,7 +2142,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; if ((num < 0) || (num > 16)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if ((mode != ARM_MODE_ANY) && (mode != armv4_5->core_mode) @@ -2123,6 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); } + uint32_t value = 0; if ((num >= 0) && (num <= 15)) { /* read a normal core register */ @@ -2170,7 +2205,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; if ((num < 0) || (num > 16)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if ((mode != ARM_MODE_ANY) && (mode != armv4_5->core_mode) @@ -2242,7 +2277,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -2396,7 +2431,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u return ERROR_OK; } -int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *armv4_5 = &arm7_9->armv4_5_common; @@ -2422,7 +2457,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, /* sanitize arguments */ if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer)) - return ERROR_INVALID_ARGUMENTS; + return ERROR_COMMAND_SYNTAX_ERROR; if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; @@ -2462,7 +2497,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); else + { retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + if (retval != ERROR_OK) { return retval; @@ -2498,7 +2546,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); else + { retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + if (retval != ERROR_OK) { return retval; @@ -2533,7 +2594,20 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, if (arm7_9->fast_memory_access) retval = arm7_9_execute_fast_sys_speed(target); else - retval = arm7_9_execute_sys_speed(target); + { + retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + if (retval != ERROR_OK) { return retval; @@ -2581,7 +2655,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, } static int dcc_count; -static uint8_t *dcc_buffer; +static const uint8_t *dcc_buffer; static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { @@ -2593,7 +2667,7 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int int little = target->endianness == TARGET_LITTLE_ENDIAN; int count = dcc_count; - uint8_t *buffer = dcc_buffer; + const uint8_t *buffer = dcc_buffer; if (count > 2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the @@ -2646,7 +2720,7 @@ static const uint32_t dcc_code[] = 0xeafffff9 /* b w */ }; -int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer) +int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target);