X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=8f87d9cdae03f8f9abb6f2c3351cc0b5b269fd8a;hp=3461da4c48a3689f93ac5156ce9c600d10197333;hb=HEAD;hpb=d2d4f776d8e24e8e651d1c896c90c15c38633172 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 3461da4c48..ad814e0541 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + /*************************************************************************** * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * @@ -12,21 +14,6 @@ * hontor@126.com * * * * Copyright (C) 2009 by David Brownell * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -57,8 +44,8 @@ * shadowed registers, and support for the Thumb instruction set. * * Processor differences include things like presence or absence of MMU - * and cache, pipeline sizes, use of a modified Harvard Architecure - * (with separate instruction and data busses from the CPU), support + * and cache, pipeline sizes, use of a modified Harvard Architecture + * (with separate instruction and data buses from the CPU), support * for cpu clock gating during idle, and more. */ @@ -95,18 +82,20 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br { if (!arm7_9->wp0_used) { arm7_9->wp0_used = 1; - breakpoint->set = 1; + breakpoint_hw_set(breakpoint, 0); arm7_9->wp_available--; } else if (!arm7_9->wp1_used) { arm7_9->wp1_used = 1; - breakpoint->set = 2; + breakpoint_hw_set(breakpoint, 1); arm7_9->wp_available--; - } else + } else { LOG_ERROR("BUG: no hardware comparator available"); - LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + } + + LOG_DEBUG("BPID: %" PRIu32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %u", breakpoint->unique_id, breakpoint->address, - breakpoint->set); + breakpoint->number); } /** @@ -142,13 +131,13 @@ static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else if (arm7_9->sw_breakpoints_added == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else { LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); @@ -189,13 +178,13 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int retval = ERROR_OK; - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d", + LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d", breakpoint->unique_id, breakpoint->address, breakpoint->type); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -204,20 +193,20 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u; /* reassign a hw breakpoint */ - if (breakpoint->set == 0) + if (!breakpoint->is_set) arm7_9_assign_wp(arm7_9, breakpoint); - if (breakpoint->set == 1) { + if (breakpoint->number == 0) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - } else if (breakpoint->set == 2) { + } else if (breakpoint->number == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu); - embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } else { LOG_ERROR("BUG: no hardware comparator available"); @@ -227,7 +216,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break retval = jtag_execute_queue(); } else if (breakpoint->type == BKPT_SOFT) { /* did we already set this breakpoint? */ - if (breakpoint->set) + if (breakpoint->is_set) return ERROR_OK; if (breakpoint->length == 4) { @@ -246,7 +235,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break if (retval != ERROR_OK) return retval; if (verify != arm7_9->arm_bkpt) { - LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 + LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" TARGET_PRIxADDR " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } @@ -266,7 +255,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break if (retval != ERROR_OK) return retval; if (verify != arm7_9->thumb_bkpt) { - LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 + LOG_ERROR("Unable to set thumb software breakpoint at address %08" TARGET_PRIxADDR " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } @@ -278,7 +267,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break arm7_9->sw_breakpoint_count++; - breakpoint->set = 1; + breakpoint->is_set = true; } return retval; @@ -301,30 +290,30 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR, breakpoint->unique_id, breakpoint->address); - if (!breakpoint->set) { + if (!breakpoint->is_set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } if (breakpoint->type == BKPT_HARD) { - LOG_DEBUG("BPID: %d Releasing hw wp: %d", + LOG_DEBUG("BPID: %" PRIu32 " Releasing hw wp: %d", breakpoint->unique_id, - breakpoint->set); - if (breakpoint->set == 1) { + breakpoint->is_set); + if (breakpoint->number == 0) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); arm7_9->wp0_used = 0; arm7_9->wp_available++; - } else if (breakpoint->set == 2) { + } else if (breakpoint->number == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->wp1_used = 0; arm7_9->wp_available++; } retval = jtag_execute_queue(); - breakpoint->set = 0; + breakpoint->is_set = false; } else { /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { @@ -350,12 +339,12 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre if (retval != ERROR_OK) return retval; current_instr = target_buffer_get_u16(target, (uint8_t *)¤t_instr); - if (current_instr == arm7_9->thumb_bkpt) + if (current_instr == arm7_9->thumb_bkpt) { retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr); if (retval != ERROR_OK) return retval; - + } } if (--arm7_9->sw_breakpoint_count == 0) { @@ -369,7 +358,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre EICE_W1_CONTROL_VALUE], 0); } - breakpoint->set = 0; + breakpoint->is_set = false; } return retval; @@ -462,11 +451,12 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch struct arm7_9_common *arm7_9 = target_to_arm7_9(target); int rw_mask = 1; uint32_t mask; + const uint32_t wp_data_mask = watchpoint->mask; mask = watchpoint->length - 1; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -480,38 +470,38 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], - watchpoint->mask); - if (watchpoint->mask != 0xffffffffu) + wp_data_mask); + if (wp_data_mask != (uint32_t)WATCHPOINT_IGNORE_DATA_VALUE_MASK) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], - 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); + 0xff & ~EICE_W_CTRL_NOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], - EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); + EICE_W_CTRL_ENABLE | EICE_W_CTRL_NOPC | (watchpoint->rw & 1)); retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; - watchpoint->set = 1; + watchpoint_set(watchpoint, 1); arm7_9->wp0_used = 2; } else if (!arm7_9->wp1_used) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], - watchpoint->mask); - if (watchpoint->mask != 0xffffffffu) + wp_data_mask); + if (wp_data_mask != (uint32_t)WATCHPOINT_IGNORE_DATA_VALUE_MASK) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], - 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); + 0xff & ~EICE_W_CTRL_NOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], - EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); + EICE_W_CTRL_ENABLE | EICE_W_CTRL_NOPC | (watchpoint->rw & 1)); retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; - watchpoint->set = 2; + watchpoint_set(watchpoint, 2); arm7_9->wp1_used = 2; } else { LOG_ERROR("BUG: no hardware comparator available"); @@ -535,29 +525,29 @@ static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *wat struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } - if (!watchpoint->set) { + if (!watchpoint->is_set) { LOG_WARNING("breakpoint not set"); return ERROR_OK; } - if (watchpoint->set == 1) { + if (watchpoint->number == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; arm7_9->wp0_used = 0; - } else if (watchpoint->set == 2) { + } else if (watchpoint->number == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; arm7_9->wp1_used = 0; } - watchpoint->set = 0; + watchpoint->is_set = false; return ERROR_OK; } @@ -598,7 +588,7 @@ int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoin int retval = ERROR_OK; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - if (watchpoint->set) { + if (watchpoint->is_set) { retval = arm7_9_unset_watchpoint(target, watchpoint); if (retval != ERROR_OK) return retval; @@ -628,16 +618,16 @@ int arm7_9_execute_sys_speed(struct target *target) /* set RESTART instruction */ if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; } - retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, 0x4, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; - long long then = timeval_ms(); - int timeout; + int64_t then = timeval_ms(); + bool timeout; while (!(timeout = ((timeval_ms()-then) > 1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -682,11 +672,11 @@ static int arm7_9_execute_fast_sys_speed(struct target *target) /* set RESTART instruction */ if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; } - retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, 0x4, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -875,6 +865,13 @@ int arm7_9_assert_reset(struct target *target) enum reset_types jtag_reset_config = jtag_get_reset_config(); bool use_event = false; + /* TODO: apply hw reset signal in not examined state */ + if (!(target_was_examined(target))) { + LOG_WARNING("Reset is not asserted because the target is not examined."); + LOG_WARNING("Use a reset button or power cycle the target."); + return ERROR_TARGET_NOT_EXAMINED; + } + LOG_DEBUG("target->state: %s", target_state_name(target)); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) @@ -927,7 +924,7 @@ int arm7_9_assert_reset(struct target *target) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_NOPC & 0xff); } } @@ -1003,7 +1000,7 @@ int arm7_9_deassert_reset(struct target *target) /** * Clears the halt condition for an ARM7/9 target. If it isn't coming out of - * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset + * reset and if DBGRQ is used, it is programmed to be deasserted. If the reset * vector catch was used, it is restored. Otherwise, the control value is * restored and the watchpoint unit is restored if it was in use. * @@ -1135,20 +1132,20 @@ int arm7_9_soft_reset_halt(struct target *target) cpsr &= ~0xff; cpsr |= 0xd3; arm_set_cpsr(arm, cpsr); - arm->cpsr->dirty = 1; + arm->cpsr->dirty = true; /* start fetching from 0x0 */ buf_set_u32(arm->pc->value, 0, 32, 0x0); - arm->pc->dirty = 1; - arm->pc->valid = 1; + arm->pc->dirty = true; + arm->pc->valid = true; /* reset registers */ for (i = 0; i <= 14; i++) { struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, 0xffffffff); - r->dirty = 1; - r->valid = 1; + r->dirty = true; + r->valid = true; } retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED); @@ -1206,7 +1203,7 @@ int arm7_9_halt(struct target *target) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + ~EICE_W_CTRL_NOPC & 0xff); } target->debug_reason = DBG_REASON_DBGRQ; @@ -1263,7 +1260,7 @@ static int arm7_9_debug_entry(struct target *target) return retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1340,7 +1337,7 @@ static int arm7_9_debug_entry(struct target *target) buf_set_u32(r->value, 0, 32, context[i]); /* r0 and r15 (pc) have to be restored later */ r->dirty = (i == 0) || (i == 15); - r->valid = 1; + r->valid = true; } LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]); @@ -1353,8 +1350,8 @@ static int arm7_9_debug_entry(struct target *target) if (retval != ERROR_OK) return retval; buf_set_u32(arm->spsr->value, 0, 32, spsr); - arm->spsr->dirty = 0; - arm->spsr->valid = 1; + arm->spsr->dirty = false; + arm->spsr->valid = true; } retval = jtag_execute_queue(); @@ -1385,11 +1382,16 @@ static int arm7_9_full_context(struct target *target) int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; + struct { + uint32_t value; + uint8_t *reg_p; + } read_cache[6 * (16 + 1)]; + int read_cache_idx = 0; LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1405,13 +1407,13 @@ static int arm7_9_full_context(struct target *target) uint32_t mask = 0; uint32_t *reg_p[16]; int j; - int valid = 1; + bool valid = true; /* check if there are invalid registers in the current mode */ for (j = 0; j <= 16; j++) { - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) - valid = 0; + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid) + valid = false; } if (!valid) { @@ -1425,19 +1427,21 @@ static int arm7_9_full_context(struct target *target) arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); for (j = 0; j < 15; j++) { - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, - armv4_5_number_to_mode(i), j).valid == 0) { - reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE( + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), j).valid) { + read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE( arm->core_cache, armv4_5_number_to_mode(i), j).value; + reg_p[j] = &read_cache[read_cache_idx].value; + read_cache_idx++; mask |= 1 << j; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - j).valid = 1; + j).valid = true; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - j).dirty = 0; + j).dirty = false; } } @@ -1446,15 +1450,16 @@ static int arm7_9_full_context(struct target *target) arm7_9->read_core_regs(target, mask, reg_p); /* check if the PSR has to be read */ - if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - 16).valid == 0) { - arm7_9->read_xpsr(target, - (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, - armv4_5_number_to_mode(i), 16).value, 1); + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), + 16).valid) { + read_cache[read_cache_idx].reg_p = ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), 16).value; + arm7_9->read_xpsr(target, &read_cache[read_cache_idx].value, 1); + read_cache_idx++; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - 16).valid = 1; + 16).valid = true; ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), - 16).dirty = 0; + 16).dirty = false; } } } @@ -1466,6 +1471,14 @@ static int arm7_9_full_context(struct target *target) retval = jtag_execute_queue(); if (retval != ERROR_OK) return retval; + /* + * FIXME: regs in cache should be tagged as 'valid' only now, + * not before the jtag_execute_queue() + */ + while (read_cache_idx) { + read_cache_idx--; + buf_set_u32(read_cache[read_cache_idx].reg_p, 0, 32, read_cache[read_cache_idx].value); + } return ERROR_OK; } @@ -1488,13 +1501,13 @@ static int arm7_9_restore_context(struct target *target) struct reg *reg; enum arm_mode current_mode = arm->core_mode; int i, j; - int dirty; + bool dirty; int mode_change; LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1512,15 +1525,15 @@ static int arm7_9_restore_context(struct target *target) for (i = 0; i < 6; i++) { LOG_DEBUG("examining %s mode", arm_mode_name(arm->core_mode)); - dirty = 0; + dirty = false; mode_change = 0; /* check if there are dirty registers in the current mode */ for (j = 0; j <= 16; j++) { reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); - if (reg->dirty == 1) { - if (reg->valid == 1) { - dirty = 1; + if (reg->dirty) { + if (reg->valid) { + dirty = true; LOG_DEBUG("examining dirty reg: %s", reg->name); struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; @@ -1541,7 +1554,6 @@ static int arm7_9_restore_context(struct target *target) if (dirty) { uint32_t mask = 0x0; - int num_regs = 0; uint32_t regs[16]; if (mode_change) { @@ -1561,12 +1573,11 @@ static int arm7_9_restore_context(struct target *target) armv4_5_number_to_mode(i), j); - if (reg->dirty == 1) { + if (reg->dirty) { regs[j] = buf_get_u32(reg->value, 0, 32); mask |= 1 << j; - num_regs++; - reg->dirty = 0; - reg->valid = 1; + reg->dirty = false; + reg->valid = true; LOG_DEBUG("writing register %i mode %s " "with value 0x%8.8" PRIx32, j, arm_mode_name(arm->core_mode), @@ -1608,15 +1619,15 @@ static int arm7_9_restore_context(struct target *target) arm7_9->write_xpsr(target, buf_get_u32(arm->cpsr->value, 0, 32) & ~0x20, 0); - arm->cpsr->dirty = 0; - arm->cpsr->valid = 1; + arm->cpsr->dirty = false; + arm->cpsr->valid = true; } /* restore PC */ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, buf_get_u32(arm->pc->value, 0, 32)); arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32)); - arm->pc->dirty = 0; + arm->pc->dirty = false; return ERROR_OK; } @@ -1639,11 +1650,11 @@ static int arm7_9_restart_core(struct target *target) if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; - retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; } - retval = arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE); + retval = arm_jtag_set_instr(jtag_info->tap, 0x4, NULL, TAP_IDLE); if (retval != ERROR_OK) return retval; @@ -1662,7 +1673,7 @@ static void arm7_9_enable_watchpoints(struct target *target) struct watchpoint *watchpoint = target->watchpoints; while (watchpoint) { - if (watchpoint->set == 0) + if (!watchpoint->is_set) arm7_9_set_watchpoint(target, watchpoint); watchpoint = watchpoint->next; } @@ -1687,7 +1698,7 @@ static void arm7_9_enable_breakpoints(struct target *target) int arm7_9_resume(struct target *target, int current, - uint32_t address, + target_addr_t address, int handle_breakpoints, int debug_execution) { @@ -1699,7 +1710,7 @@ int arm7_9_resume(struct target *target, LOG_DEBUG("-"); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1718,8 +1729,8 @@ int arm7_9_resume(struct target *target, struct breakpoint *breakpoint; breakpoint = breakpoint_find(target, buf_get_u32(arm->pc->value, 0, 32)); - if (breakpoint != NULL) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", + if (breakpoint) { + LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRIu32, breakpoint->address, breakpoint->unique_id); retval = arm7_9_unset_breakpoint(target, breakpoint); @@ -1778,7 +1789,7 @@ int arm7_9_resume(struct target *target, LOG_DEBUG("new PC after step: 0x%8.8" PRIx32, buf_get_u32(arm->pc->value, 0, 32)); - LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address); retval = arm7_9_set_breakpoint(target, breakpoint); if (retval != ERROR_OK) return retval; @@ -1851,14 +1862,14 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], - ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); + ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_NOPC) & 0xff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + ~EICE_W_CTRL_NOPC & 0xff); } else { embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); @@ -1870,7 +1881,7 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], - ~EICE_W_CTRL_nOPC & 0xff); + ~EICE_W_CTRL_NOPC & 0xff); } } @@ -1889,7 +1900,7 @@ void arm7_9_disable_eice_step(struct target *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]); } -int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints) +int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct arm *arm = &arm7_9->arm; @@ -1897,7 +1908,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle int err, retval; if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -1910,7 +1921,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) breakpoint = breakpoint_find(target, current_pc); - if (breakpoint != NULL) { + if (breakpoint) { retval = arm7_9_unset_breakpoint(target, breakpoint); if (retval != ERROR_OK) return retval; @@ -2018,8 +2029,8 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, if (retval != ERROR_OK) return retval; - r->valid = 1; - r->dirty = 0; + r->valid = true; + r->dirty = false; buf_set_u32(r->value, 0, 32, value); if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) @@ -2033,7 +2044,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, } static int arm7_9_write_core_reg(struct target *target, struct reg *r, - int num, enum arm_mode mode, uint32_t value) + int num, enum arm_mode mode, uint8_t *value) { uint32_t reg[16]; struct arm_reg *areg = r->arch_info; @@ -2058,7 +2069,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, if ((num >= 0) && (num <= 15)) { /* write a normal core register */ - reg[num] = value; + reg[num] = buf_get_u32(value, 0, 32); arm7_9->write_core_regs(target, 1 << num, reg); } else { @@ -2067,15 +2078,16 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, */ int spsr = (areg->mode != ARM_MODE_ANY); + uint32_t t = buf_get_u32(value, 0, 32); /* if we're writing the CPSR, mask the T bit */ if (!spsr) - value &= ~0x20; + t &= ~0x20; - arm7_9->write_xpsr(target, value, spsr); + arm7_9->write_xpsr(target, t, spsr); } - r->valid = 1; - r->dirty = 0; + r->valid = true; + r->dirty = false; if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { @@ -2088,7 +2100,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, } int arm7_9_read_memory(struct target *target, - uint32_t address, + target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer) @@ -2103,11 +2115,11 @@ int arm7_9_read_memory(struct target *target, int retval; int last_reg = 0; - LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", + LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2241,7 +2253,8 @@ int arm7_9_read_memory(struct target *target, if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { LOG_WARNING( - "memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", + "memory read caused data abort " + "(address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); @@ -2257,7 +2270,7 @@ int arm7_9_read_memory(struct target *target, } int arm7_9_write_memory(struct target *target, - uint32_t address, + target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer) @@ -2279,7 +2292,7 @@ int arm7_9_write_memory(struct target *target, #endif if (target->state != TARGET_HALTED) { - LOG_WARNING("target not halted"); + LOG_TARGET_ERROR(target, "not halted"); return ERROR_TARGET_NOT_HALTED; } @@ -2454,7 +2467,8 @@ int arm7_9_write_memory(struct target *target, if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { LOG_WARNING( - "memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", + "memory write caused data abort " + "(address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); @@ -2469,12 +2483,43 @@ int arm7_9_write_memory(struct target *target, return ERROR_OK; } +int arm7_9_write_memory_opt(struct target *target, + target_addr_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) +{ + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + int retval; + + if (size == 4 && count > 32 && arm7_9->bulk_write_memory) { + /* Attempt to do a bulk write */ + retval = arm7_9->bulk_write_memory(target, address, count, buffer); + + if (retval == ERROR_OK) + return ERROR_OK; + } + + return arm7_9->write_memory(target, address, size, count, buffer); +} + +int arm7_9_write_memory_no_opt(struct target *target, + uint32_t address, + uint32_t size, + uint32_t count, + const uint8_t *buffer) +{ + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + + return arm7_9->write_memory(target, address, size, count, buffer); +} + static int dcc_count; static const uint8_t *dcc_buffer; static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, - int timeout_ms, + unsigned int timeout_ms, void *arch_info) { int retval = ERROR_OK; @@ -2539,16 +2584,18 @@ static const uint32_t dcc_code[] = { }; int arm7_9_bulk_write_memory(struct target *target, - uint32_t address, + target_addr_t address, uint32_t count, const uint8_t *buffer) { int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - int i; + + if (address % 4 != 0) + return ERROR_TARGET_UNALIGNED_ACCESS; if (!arm7_9->dcc_downloads) - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; /* regrab previously allocated working_area, or allocate a new one */ if (!arm7_9->dcc_working_area) { @@ -2557,15 +2604,15 @@ int arm7_9_bulk_write_memory(struct target *target, /* make sure we have a working area */ if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target_write_memory(target, address, 4, count, buffer); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } /* copy target instructions to target endianness */ - for (i = 0; i < 6; i++) - target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]); + target_buffer_set_u32_array(target, dcc_code_buf, ARRAY_SIZE(dcc_code), dcc_code); - /* write DCC code to working area */ - retval = target_write_memory(target, + /* write DCC code to working area, using the non-optimized + * memory write to avoid ending up here again */ + retval = arm7_9_write_memory_no_opt(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf); if (retval != ERROR_OK) return retval; @@ -2593,7 +2640,7 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); if (endaddress != (address + count*4)) { LOG_ERROR( - "DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", + "DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "", (address + count*4), endaddress); retval = ERROR_FAIL; @@ -2617,7 +2664,7 @@ int arm7_9_examine(struct target *target) struct reg_cache *t, **cache_p; t = embeddedice_build_reg_cache(target, arm7_9); - if (t == NULL) + if (!t) return ERROR_FAIL; cache_p = register_get_last_cache_p(&target->reg_cache); @@ -2640,6 +2687,15 @@ int arm7_9_examine(struct target *target) return retval; } +void arm7_9_deinit(struct target *target) +{ + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + + if (target_was_examined(target)) + embeddedice_free_reg_cache(arm7_9->eice_cache); + + arm_jtag_close_connection(&arm7_9->jtag_info); +} int arm7_9_check_reset(struct target *target) { @@ -2659,20 +2715,60 @@ int arm7_9_check_reset(struct target *target) return ERROR_OK; } +int arm7_9_endianness_callback(jtag_callback_data_t pu8_in, + jtag_callback_data_t i_size, jtag_callback_data_t i_be, + jtag_callback_data_t i_flip) +{ + uint8_t *in = (uint8_t *)pu8_in; + int size = (int)i_size; + int be = (int)i_be; + int flip = (int)i_flip; + uint32_t readback; + + switch (size) { + case 4: + readback = le_to_h_u32(in); + if (flip) + readback = flip_u32(readback, 32); + if (be) + h_u32_to_be(in, readback); + else + h_u32_to_le(in, readback); + break; + case 2: + readback = le_to_h_u16(in); + if (flip) + readback = flip_u32(readback, 16); + if (be) + h_u16_to_be(in, readback & 0xffff); + else + h_u16_to_le(in, readback & 0xffff); + break; + case 1: + readback = *in; + if (flip) + readback = flip_u32(readback, 8); + *in = readback & 0xff; + break; + } + + return ERROR_OK; +} + COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { struct target *target = get_current_target(CMD_CTX); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (!is_arm7_9(arm7_9)) { - command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + command_print(CMD, "current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } if (CMD_ARGC > 0) COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->use_dbgrq); - command_print(CMD_CTX, + command_print(CMD, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled"); @@ -2685,14 +2781,14 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (!is_arm7_9(arm7_9)) { - command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + command_print(CMD, "current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } if (CMD_ARGC > 0) COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access); - command_print(CMD_CTX, + command_print(CMD, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled"); @@ -2705,14 +2801,14 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (!is_arm7_9(arm7_9)) { - command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target"); + command_print(CMD, "current target isn't an ARM7/ARM9 target"); return ERROR_TARGET_INVALID; } if (CMD_ARGC > 0) COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads); - command_print(CMD_CTX, + command_print(CMD, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled"); @@ -2766,6 +2862,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) arm7_9->dcc_downloads = false; arm->arch_info = arm7_9; + arm->core_type = ARM_CORE_TYPE_STD; arm->read_core_reg = arm7_9_read_core_reg; arm->write_core_reg = arm7_9_write_core_reg; arm->full_context = arm7_9_full_context; @@ -2776,12 +2873,12 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) return retval; return target_register_timer_callback(arm7_9_handle_target_request, - 1, 1, target); + 1, TARGET_TIMER_TYPE_PERIODIC, target); } static const struct command_registration arm7_9_any_command_handlers[] = { { - "dbgrq", + .name = "dbgrq", .handler = handle_arm7_9_dbgrq_command, .mode = COMMAND_ANY, .usage = "['enable'|'disable']", @@ -2789,7 +2886,7 @@ static const struct command_registration arm7_9_any_command_handlers[] = { "for target halt requests", }, { - "fast_memory_access", + .name = "fast_memory_access", .handler = handle_arm7_9_fast_memory_access_command, .mode = COMMAND_ANY, .usage = "['enable'|'disable']", @@ -2797,7 +2894,7 @@ static const struct command_registration arm7_9_any_command_handlers[] = { "but potentially safer accesses", }, { - "dcc_downloads", + .name = "dcc_downloads", .handler = handle_arm7_9_dcc_downloads_command, .mode = COMMAND_ANY, .usage = "['enable'|'disable']",