X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=e35940bc9fd0b6b445ca6d4189fb391b9eb48033;hp=474f94678b6fcef61a7d3b3d557b27be6f75d24e;hb=83655bf49bfa03b0c57c20123984cf09c4c09393;hpb=d61714f4d5d72f9f39fbccbb1c3ba5f3d8982020 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 474f94678b..e35940bc9f 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 �yvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * @@ -58,6 +58,7 @@ int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char */ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) { + LOG_DEBUG("-"); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->sw_breakpoints_added = 0; @@ -93,6 +94,10 @@ static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) { LOG_ERROR("BUG: no hardware comparator available"); } + LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + breakpoint->unique_id, + breakpoint->address, + breakpoint->set ); } /** @@ -118,11 +123,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) /* pick a breakpoint unit */ if (!arm7_9->wp0_used) { - arm7_9->sw_breakpoints_added=1; + arm7_9->sw_breakpoints_added = 1; arm7_9->wp0_used = 3; } else if (!arm7_9->wp1_used) { - arm7_9->sw_breakpoints_added=2; + arm7_9->sw_breakpoints_added = 2; arm7_9->wp1_used = 3; } else @@ -131,7 +136,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) return ERROR_FAIL; } - if (arm7_9->sw_breakpoints_added==1) + if (arm7_9->sw_breakpoints_added == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); @@ -139,7 +144,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } - else if (arm7_9->sw_breakpoints_added==2) + else if (arm7_9->sw_breakpoints_added == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); @@ -152,6 +157,8 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); return ERROR_FAIL; } + LOG_DEBUG("SW BP using hw wp: %d", + arm7_9->sw_breakpoints_added ); return jtag_execute_queue(); } @@ -218,7 +225,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - int retval=ERROR_OK; + int retval = ERROR_OK; + + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + breakpoint->unique_id, + breakpoint->address ); if (target->state != TARGET_HALTED) { @@ -232,12 +243,12 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u; /* reassign a hw breakpoint */ - if (breakpoint->set==0) + if (breakpoint->set == 0) { arm7_9_assign_wp(arm7_9, breakpoint); } - if (breakpoint->set==1) + if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); @@ -245,7 +256,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } - else if (breakpoint->set==2) + else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); @@ -259,11 +270,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } - retval=jtag_execute_queue(); + retval = jtag_execute_queue(); } else if (breakpoint->type == BKPT_SOFT) { - if ((retval=arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) + if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) return retval; /* did we already set this breakpoint? */ @@ -343,6 +354,10 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + breakpoint->unique_id, + breakpoint->address ); + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); @@ -351,6 +366,9 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { + LOG_DEBUG("BPID: %d Releasing hw wp: %d", + breakpoint->unique_id, + breakpoint->set ); if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); @@ -377,7 +395,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { return retval; } - if (current_instr==arm7_9->arm_bkpt) + if (current_instr == arm7_9->arm_bkpt) if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; @@ -391,7 +409,7 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { return retval; } - if (current_instr==arm7_9->thumb_bkpt) + if (current_instr == arm7_9->thumb_bkpt) if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; @@ -423,7 +441,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_TARGET_NOT_HALTED; } - if (arm7_9->breakpoint_count==0) + if (arm7_9->breakpoint_count == 0) { /* make sure we don't have any dangling breakpoints. This is vital upon * GDB connect/disconnect @@ -478,7 +496,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) arm7_9->wp_available++; arm7_9->breakpoint_count--; - if (arm7_9->breakpoint_count==0) + if (arm7_9->breakpoint_count == 0) { /* make sure we don't have any dangling breakpoints */ if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK) @@ -526,7 +544,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask); - if ( watchpoint->mask != 0xffffffffu ) + if (watchpoint->mask != 0xffffffffu) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); @@ -543,7 +561,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask); - if ( watchpoint->mask != 0xffffffffu ) + if (watchpoint->mask != 0xffffffffu) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); @@ -700,9 +718,9 @@ int arm7_9_execute_sys_speed(struct target_s *target) } arm_jtag_set_instr(jtag_info, 0x4, NULL); - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -711,7 +729,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) break; - if (debug_level>=3) + if (debug_level >= 3) { alive_sleep(100); } else @@ -738,7 +756,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) */ int arm7_9_execute_fast_sys_speed(struct target_s *target) { - static int set=0; + static int set = 0; static uint8_t check_value[4], check_mask[4]; armv4_5_common_t *armv4_5 = target->arch_info; @@ -764,7 +782,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) * */ buf_set_u32(check_value, 0, 32, 0x9); buf_set_u32(check_mask, 0, 32, 0x9); - set=1; + set = 1; } /* read debug status register */ @@ -862,11 +880,11 @@ int arm7_9_handle_target_request(void *priv) * what happens: * * - * - * - * - * - * + * + * + * + * + * *
StateAction
TARGET_RUNNING | TARGET_RESETEnters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWNWarning is logged
TARGET_DEBUG_RUNNINGEnters debug mode
TARGET_HALTEDNothing
State Action
TARGET_RUNNING | TARGET_RESET Enters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWN Warning is logged
TARGET_DEBUG_RUNNING Enters debug mode
TARGET_HALTED Nothing
* * If the target does not end up in the halted state, a warning is produced. If @@ -895,18 +913,19 @@ int arm7_9_poll(target_t *target) /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/ if (target->state == TARGET_UNKNOWN) { + /* Starting OpenOCD with target in debug-halt */ target->state = TARGET_RUNNING; - LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target."); + LOG_DEBUG("DBGACK already set during server startup."); } if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - int check_pc=0; + int check_pc = 0; if (target->state == TARGET_RESET) { if (target->reset_halt) { enum reset_types jtag_reset_config = jtag_get_reset_config(); - if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0) + if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) { check_pc = 1; } @@ -974,7 +993,7 @@ int arm7_9_assert_reset(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (!(jtag_reset_config & RESET_HAS_SRST)) @@ -1022,7 +1041,7 @@ int arm7_9_assert_reset(target_t *target) armv4_5_invalidate_core_regs(target); - if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)) + if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)) { /* debug entry was already prepared in arm7_9_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; @@ -1042,27 +1061,27 @@ int arm7_9_assert_reset(target_t *target) */ int arm7_9_deassert_reset(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); enum reset_types jtag_reset_config = jtag_get_reset_config(); - if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) + if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) { LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset."); /* set up embedded ice registers again */ if ((retval = target_examine_one(target)) != ERROR_OK) return retval; - if ((retval=target_poll(target)) != ERROR_OK) + if ((retval = target_poll(target)) != ERROR_OK) { return retval; } - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) { return retval; } @@ -1147,19 +1166,19 @@ int arm7_9_soft_reset_halt(struct target_s *target) int i; int retval; - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); - if ((retval=jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - if (debug_level>=3) + if (debug_level >= 3) { alive_sleep(100); } else @@ -1246,7 +1265,7 @@ int arm7_9_soft_reset_halt(struct target_s *target) */ int arm7_9_halt(target_t *target) { - if (target->state==TARGET_RESET) + if (target->state == TARGET_RESET) { LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()"); return ERROR_OK; @@ -1257,7 +1276,7 @@ int arm7_9_halt(target_t *target) reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -1412,23 +1431,15 @@ int arm7_9_debug_entry(target_t *target) context[15] -= 3 * 4; } - if ((target->debug_reason == DBG_REASON_BREAKPOINT) - || (target->debug_reason == DBG_REASON_SINGLESTEP) - || (target->debug_reason == DBG_REASON_WATCHPOINT) - || (target->debug_reason == DBG_REASON_WPTANDBKPT) - || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0))) + if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq)) context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); - else if (target->debug_reason == DBG_REASON_DBGRQ) - context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); else - { - LOG_ERROR("unknown debug reason: %i", target->debug_reason); - } + context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=15; i++) + for (i = 0; i <= 15; i++) { LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]); @@ -1807,7 +1818,7 @@ int arm7_9_resume(struct target_s *target, int current, uint32_t address, int ha { if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id ); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { return retval; @@ -1951,7 +1962,7 @@ void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); @@ -2240,7 +2251,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, reg[0] = address; arm7_9->write_core_regs(target, 0x1, reg); - int j=0; + int j = 0; switch (size) { @@ -2272,7 +2283,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, buffer += thisrun_accesses * 4; num_accesses += thisrun_accesses; - if ((j++%1024)==0) + if ((j++%1024) == 0) { keep_alive(); } @@ -2310,7 +2321,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, buffer += thisrun_accesses * 2; num_accesses += thisrun_accesses; - if ((j++%1024)==0) + if ((j++%1024) == 0) { keep_alive(); } @@ -2347,7 +2358,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, buffer += thisrun_accesses * 1; num_accesses += thisrun_accesses; - if ((j++%1024)==0) + if ((j++%1024) == 0) { keep_alive(); } @@ -2362,7 +2373,7 @@ int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2545,7 +2556,7 @@ int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2576,13 +2587,13 @@ static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, i armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) + if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) return retval; - int little=target->endianness==TARGET_LITTLE_ENDIAN; - int count=dcc_count; - uint8_t *buffer=dcc_buffer; - if (count>2) + int little = target->endianness == TARGET_LITTLE_ENDIAN; + int count = dcc_count; + uint8_t *buffer = dcc_buffer; + if (count > 2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the * core function repeated. */ @@ -2669,18 +2680,18 @@ int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, buf_set_u32(reg_params[0].value, 0, 32, address); - dcc_count=count; - dcc_buffer=buffer; + dcc_count = count; + dcc_buffer = buffer; retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, - arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); + arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); - if (retval==ERROR_OK) + if (retval == ERROR_OK) { - uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32); - if (endaddress != (address+count*4)) + uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); + if (endaddress != (address + count*4)) { - LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress); - retval=ERROR_FAIL; + LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress); + retval = ERROR_FAIL; } } @@ -2734,7 +2745,7 @@ int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t c /* convert flash writing code into a buffer in target endianness */ for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++) { - if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) + if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) { return retval; } @@ -2842,17 +2853,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands"); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register "); register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, - COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); + COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses "); + COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses "); register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, - COMMAND_ANY, "use DCC downloads for larger memory writes "); + COMMAND_ANY, "use DCC downloads for larger memory writes "); armv4_5_register_commands(cmd_ctx); @@ -2884,7 +2895,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm if (argc < 2) { - command_print(cmd_ctx, "usage: write_xpsr "); + command_print(cmd_ctx, "usage: write_xpsr "); return ERROR_OK; } @@ -2929,7 +2940,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char if (argc < 3) { - command_print(cmd_ctx, "usage: write_xpsr_im8 "); + command_print(cmd_ctx, "usage: write_xpsr_im8 "); return ERROR_OK; } @@ -3005,7 +3016,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch } else { - command_print(cmd_ctx, "usage: arm7_9 dbgrq "); + command_print(cmd_ctx, "usage: arm7_9 dbgrq "); } } @@ -3038,7 +3049,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, } else { - command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); + command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); } } @@ -3071,7 +3082,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char } else { - command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); + command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); } }