X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.c;h=e35940bc9fd0b6b445ca6d4189fb391b9eb48033;hp=8814636b604e80644d6bfa639bcaee2a87bde60f;hb=83655bf49bfa03b0c57c20123984cf09c4c09393;hpb=368daf44ff6aecb522952872a44bcf9e26b836f3 diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 8814636b60..e35940bc9f 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dominic.Rath@gmx.de * * * - * Copyright (C) 2007,2008 Øyvind Harboe * + * Copyright (C) 2007,2008 �yvind Harboe * * oyvind.harboe@zylin.com * * * * Copyright (C) 2008 by Spencer Oliver * @@ -30,28 +30,12 @@ #include "config.h" #endif -#include "replacements.h" - #include "embeddedice.h" -#include "target.h" #include "target_request.h" -#include "armv4_5.h" -#include "arm_jtag.h" -#include "jtag.h" -#include "log.h" #include "arm7_9_common.h" -#include "breakpoints.h" #include "time_support.h" #include "arm_simulator.h" -#include -#include -#include - -#include -#include -#include -#include int arm7_9_debug_entry(target_t *target); int arm7_9_enable_sw_bkpts(struct target_s *target); @@ -66,9 +50,15 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - +/** + * Clear watchpoints for an ARM7/9 target. + * + * @param arm7_9 Pointer to the common struct for an ARM7/9 target + * @return JTAG error status after executing queue + */ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) { + LOG_DEBUG("-"); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->sw_breakpoints_added = 0; @@ -79,7 +69,44 @@ static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9) return jtag_execute_queue(); } -/* set up embedded ice registers */ +/** + * Assign a watchpoint to one of the two available hardware comparators in an + * ARM7 or ARM9 target. + * + * @param arm7_9 Pointer to the common struct for an ARM7/9 target + * @param breakpoint Pointer to the breakpoint to be used as a watchpoint + */ +static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint) +{ + if (!arm7_9->wp0_used) + { + arm7_9->wp0_used = 1; + breakpoint->set = 1; + arm7_9->wp_available--; + } + else if (!arm7_9->wp1_used) + { + arm7_9->wp1_used = 1; + breakpoint->set = 2; + arm7_9->wp_available--; + } + else + { + LOG_ERROR("BUG: no hardware comparator available"); + } + LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", + breakpoint->unique_id, + breakpoint->address, + breakpoint->set ); +} + +/** + * Setup an ARM7/9 target's embedded ICE registers for software breakpoints. + * + * @param arm7_9 Pointer to common struct for ARM7/9 targets + * @return Error codes if there is a problem finding a watchpoint or the result + * of executing the JTAG queue + */ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) { if (arm7_9->sw_breakpoints_added) @@ -96,11 +123,11 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) /* pick a breakpoint unit */ if (!arm7_9->wp0_used) { - arm7_9->sw_breakpoints_added=1; + arm7_9->sw_breakpoints_added = 1; arm7_9->wp0_used = 3; } else if (!arm7_9->wp1_used) { - arm7_9->sw_breakpoints_added=2; + arm7_9->sw_breakpoints_added = 2; arm7_9->wp1_used = 3; } else @@ -109,7 +136,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) return ERROR_FAIL; } - if (arm7_9->sw_breakpoints_added==1) + if (arm7_9->sw_breakpoints_added == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0); @@ -117,7 +144,7 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } - else if (arm7_9->sw_breakpoints_added==2) + else if (arm7_9->sw_breakpoints_added == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0); @@ -130,11 +157,18 @@ static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9) LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1"); return ERROR_FAIL; } + LOG_DEBUG("SW BP using hw wp: %d", + arm7_9->sw_breakpoints_added ); return jtag_execute_queue(); } -/* set things up after a reset / on startup */ +/** + * Setup the common pieces for an ARM7/9 target after reset or on startup. + * + * @param target Pointer to an ARM7/9 target to setup + * @return Result of clearing the watchpoints on the target + */ int arm7_9_setup(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -143,7 +177,18 @@ int arm7_9_setup(target_t *target) return arm7_9_clear_watchpoints(arm7_9); } - +/** + * Retrieves the architecture information pointers for ARMv4/5 and ARM7/9 + * targets. A return of ERROR_OK signifies that the target is a valid target + * and that the pointers have been set properly. + * + * @param target Pointer to the target device to get the pointers from + * @param armv4_5_p Pointer to be filled in with the common struct for ARMV4/5 + * targets + * @param arm7_9_p Pointer to be filled in with the common struct for ARM7/9 + * targets + * @return ERROR_OK if successful + */ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -165,14 +210,26 @@ int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm return ERROR_OK; } -/* we set up the breakpoint even if it is already set. Some action, e.g. reset - * might have erased the values in embedded ice +/** + * Set either a hardware or software breakpoint on an ARM7/9 target. The + * breakpoint is set up even if it is already set. Some actions, e.g. reset, + * might have erased the values in Embedded ICE. + * + * @param target Pointer to the target device to set the breakpoints on + * @param breakpoint Pointer to the breakpoint to be set + * @return For hardware breakpoints, this is the result of executing the JTAG + * queue. For software breakpoints, this will be the status of the + * required memory reads and writes */ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - int retval=ERROR_OK; + int retval = ERROR_OK; + + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + breakpoint->unique_id, + breakpoint->address ); if (target->state != TARGET_HALTED) { @@ -183,8 +240,15 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */ - u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u; - if (breakpoint->set==1) + uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u; + + /* reassign a hw breakpoint */ + if (breakpoint->set == 0) + { + arm7_9_assign_wp(arm7_9, breakpoint); + } + + if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); @@ -192,7 +256,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); } - else if (breakpoint->set==2) + else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); @@ -206,11 +270,11 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } - retval=jtag_execute_queue(); + retval = jtag_execute_queue(); } else if (breakpoint->type == BKPT_SOFT) { - if ((retval=arm7_9_set_software_breakpoints(arm7_9))!=ERROR_OK) + if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK) return retval; /* did we already set this breakpoint? */ @@ -219,9 +283,9 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->length == 4) { - u32 verify = 0xffffffff; + uint32_t verify = 0xffffffff; /* keep the original instruction in target endianness */ - if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -237,15 +301,15 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } if (verify != arm7_9->arm_bkpt) { - LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address); + LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } } else { - u16 verify = 0xffff; + uint16_t verify = 0xffff; /* keep the original instruction in target endianness */ - if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -261,7 +325,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } if (verify != arm7_9->thumb_bkpt) { - LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address); + LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address); return ERROR_OK; } } @@ -269,9 +333,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } return retval; - } +/** + * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware + * breakpoint, the watchpoint used will be freed and the Embedded ICE registers + * will be updated. Otherwise, the software breakpoint will be restored to its + * original instruction if it hasn't already been modified. + * + * @param target Pointer to ARM7/9 target to unset the breakpoint from + * @param breakpoint Pointer to breakpoint to be unset + * @return For hardware breakpoints, this is the result of executing the JTAG + * queue. For software breakpoints, this will be the status of the + * required memory reads and writes + */ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; @@ -279,6 +354,10 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; + LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32, + breakpoint->unique_id, + breakpoint->address ); + if (!breakpoint->set) { LOG_WARNING("breakpoint not set"); @@ -287,15 +366,20 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { + LOG_DEBUG("BPID: %d Releasing hw wp: %d", + breakpoint->unique_id, + breakpoint->set ); if (breakpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); arm7_9->wp0_used = 0; + arm7_9->wp_available++; } else if (breakpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); arm7_9->wp1_used = 0; + arm7_9->wp_available++; } retval = jtag_execute_queue(); breakpoint->set = 0; @@ -305,28 +389,28 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) /* restore original instruction (kept in target endianness) */ if (breakpoint->length == 4) { - u32 current_instr; + uint32_t current_instr; /* check that user program as not modified breakpoint instruction */ - if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)¤t_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK) { return retval; } - if (current_instr==arm7_9->arm_bkpt) - if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) + if (current_instr == arm7_9->arm_bkpt) + if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } } else { - u16 current_instr; + uint16_t current_instr; /* check that user program as not modified breakpoint instruction */ - if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)¤t_instr)) != ERROR_OK) + if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK) { return retval; } - if (current_instr==arm7_9->thumb_bkpt) - if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) + if (current_instr == arm7_9->thumb_bkpt) + if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK) { return retval; } @@ -337,6 +421,15 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return retval; } +/** + * Add a breakpoint to an ARM7/9 target. This makes sure that there are no + * dangling breakpoints and that the desired breakpoint can be added. + * + * @param target Pointer to the target ARM7/9 device to add a breakpoint to + * @param breakpoint Pointer to the breakpoint to be added + * @return An error status if there is a problem adding the breakpoint or the + * result of setting the breakpoint + */ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -348,7 +441,7 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_TARGET_NOT_HALTED; } - if (arm7_9->breakpoint_count==0) + if (arm7_9->breakpoint_count == 0) { /* make sure we don't have any dangling breakpoints. This is vital upon * GDB connect/disconnect @@ -370,37 +463,31 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) if (breakpoint->type == BKPT_HARD) { - arm7_9->wp_available--; - - if (!arm7_9->wp0_used) - { - arm7_9->wp0_used = 1; - breakpoint->set = 1; - } - else if (!arm7_9->wp1_used) - { - arm7_9->wp1_used = 1; - breakpoint->set = 2; - } - else - { - LOG_ERROR("BUG: no hardware comparator available"); - } + arm7_9_assign_wp(arm7_9, breakpoint); } - arm7_9->breakpoint_count++; return arm7_9_set_breakpoint(target, breakpoint); } +/** + * Removes a breakpoint from an ARM7/9 target. This will make sure there are no + * dangling breakpoints and updates available watchpoints if it is a hardware + * breakpoint. + * + * @param target Pointer to the target to have a breakpoint removed + * @param breakpoint Pointer to the breakpoint to be removed + * @return Error status if there was a problem unsetting the breakpoint or the + * watchpoints could not be cleared + */ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) + if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { return retval; } @@ -409,10 +496,10 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) arm7_9->wp_available++; arm7_9->breakpoint_count--; - if (arm7_9->breakpoint_count==0) + if (arm7_9->breakpoint_count == 0) { /* make sure we don't have any dangling breakpoints */ - if((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK) + if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK) { return retval; } @@ -421,13 +508,23 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint) return ERROR_OK; } +/** + * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is + * considered a bug to call this function when there are no available watchpoint + * units. + * + * @param target Pointer to an ARM7/9 target to set a watchpoint on + * @param watchpoint Pointer to the watchpoint to be set + * @return Error status if watchpoint set fails or the result of executing the + * JTAG queue + */ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; int rw_mask = 1; - u32 mask; + uint32_t mask; mask = watchpoint->length - 1; @@ -447,12 +544,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask); - if( watchpoint->mask != 0xffffffffu ) + if (watchpoint->mask != 0xffffffffu) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -464,12 +561,12 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask); - if( watchpoint->mask != 0xffffffffu ) + if (watchpoint->mask != 0xffffffffu) embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask); embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1)); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -485,6 +582,14 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Unset an existing watchpoint and clear the used watchpoint unit. + * + * @param target Pointer to the target to have the watchpoint removed + * @param watchpoint Pointer to the watchpoint to be removed + * @return Error status while trying to unset the watchpoint or the result of + * executing the JTAG queue + */ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; @@ -506,7 +611,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (watchpoint->set == 1) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -515,7 +620,7 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) else if (watchpoint->set == 2) { embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0); - if((retval = jtag_execute_queue()) != ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } @@ -526,6 +631,14 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units + * available, an error response is returned. + * + * @param target Pointer to the ARM7/9 target to add a watchpoint to + * @param watchpoint Pointer to the watchpoint to be added + * @return Error status while trying to add the watchpoint + */ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -552,6 +665,14 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } +/** + * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and + * the used watchpoint unit will be reopened. + * + * @param target Pointer to the target to remove a watchpoint from + * @param watchpoint Pointer to the watchpoint to be removed + * @return Result of trying to unset the watchpoint + */ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) { int retval = ERROR_OK; @@ -560,7 +681,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) if (watchpoint->set) { - if((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK) + if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK) { return retval; } @@ -571,9 +692,15 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint) return ERROR_OK; } - - - +/** + * Restarts the target by sending a RESTART instruction and moving the JTAG + * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be + * asserted by the processor. + * + * @param target Pointer to target to issue commands to + * @return Error status if there is a timeout or a problem while executing the + * JTAG queue + */ int arm7_9_execute_sys_speed(struct target_s *target) { int retval; @@ -584,16 +711,16 @@ int arm7_9_execute_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); } arm_jtag_set_instr(jtag_info, 0x4, NULL); - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { /* read debug status register */ embeddedice_read_reg(dbg_stat); @@ -602,7 +729,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1))) break; - if (debug_level>=3) + if (debug_level >= 3) { alive_sleep(100); } else @@ -612,17 +739,25 @@ int arm7_9_execute_sys_speed(struct target_s *target) } if (timeout) { - LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); + LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size)); return ERROR_TARGET_TIMEOUT; } return ERROR_OK; } +/** + * Restarts the target by sending a RESTART instruction and moving the JTAG + * state to IDLE. This validates that DBGACK and SYSCOMP are set without + * waiting until they are. + * + * @param target Pointer to the target to issue commands to + * @return Always ERROR_OK + */ int arm7_9_execute_fast_sys_speed(struct target_s *target) { - static int set=0; - static u8 check_value[4], check_mask[4]; + static int set = 0; + static uint8_t check_value[4], check_mask[4]; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -630,7 +765,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -642,32 +777,42 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) /* check for DBGACK and SYSCOMP set (others don't care) */ /* NB! These are constants that must be available until after next jtag_execute() and - we evaluate the values upon first execution in lieu of setting up these constants - during early setup. - */ + * we evaluate the values upon first execution in lieu of setting up these constants + * during early setup. + * */ buf_set_u32(check_value, 0, 32, 0x9); buf_set_u32(check_mask, 0, 32, 0x9); - set=1; + set = 1; } /* read debug status register */ - embeddedice_read_reg_w_check(dbg_stat, check_value, check_value); + embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask); return ERROR_OK; } -int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) +/** + * Get some data from the ARM7/9 target. + * + * @param target Pointer to the ARM7/9 target to read data from + * @param size The number of 32bit words to be read + * @param buffer Pointer to the buffer that will hold the data + * @return The result of receiving data from the Embedded ICE unit + */ +int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - u32 *data; - int i, retval = ERROR_OK; + uint32_t *data; + int retval = ERROR_OK; + uint32_t i; - data = malloc(size * (sizeof(u32))); + data = malloc(size * (sizeof(uint32_t))); retval = embeddedice_receive(jtag_info, data, size); + /* return the 32-bit ints in the 8-bit array */ for (i = 0; i < size; i++) { h_u32_to_le(buffer + (i * 4), data[i]); @@ -678,18 +823,26 @@ int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer) return retval; } +/** + * Handles requests to an ARM7/9 target. If debug messaging is enabled, the + * target is running and the DCC control register has the W bit high, this will + * execute the request on the target. + * + * @param priv Void pointer expected to be a target_t pointer + * @return ERROR_OK unless there are issues with the JTAG queue or when reading + * from the Embedded ICE unit + */ int arm7_9_handle_target_request(void *priv) { int retval = ERROR_OK; target_t *target = priv; - if (!target->type->examined) + if (!target_was_examined(target)) return ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL]; - if (!target->dbg_msg_enabled) return ERROR_OK; @@ -705,7 +858,7 @@ int arm7_9_handle_target_request(void *priv) /* check W bit */ if (buf_get_u32(dcc_control->value, 1, 1) == 1) { - u32 request; + uint32_t request; if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK) { @@ -721,6 +874,26 @@ int arm7_9_handle_target_request(void *priv) return ERROR_OK; } +/** + * Polls an ARM7/9 target for its current status. If DBGACK is set, the target + * is manipulated to the right halted state based on its current state. This is + * what happens: + * + * + * + * + * + * + * + *
State Action
TARGET_RUNNING | TARGET_RESET Enters debug mode. If TARGET_RESET, pc may be checked
TARGET_UNKNOWN Warning is logged
TARGET_DEBUG_RUNNING Enters debug mode
TARGET_HALTED Nothing
+ * + * If the target does not end up in the halted state, a warning is produced. If + * DBGACK is cleared, then the target is expected to either be running or + * running in debug. + * + * @param target Pointer to the ARM7/9 target to poll + * @return ERROR_OK or an error status if a command fails + */ int arm7_9_poll(target_t *target) { int retval; @@ -740,17 +913,19 @@ int arm7_9_poll(target_t *target) /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/ if (target->state == TARGET_UNKNOWN) { + /* Starting OpenOCD with target in debug-halt */ target->state = TARGET_RUNNING; - LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target."); + LOG_DEBUG("DBGACK already set during server startup."); } if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - int check_pc=0; + int check_pc = 0; if (target->state == TARGET_RESET) { if (target->reset_halt) { - if ((jtag_reset_config & RESET_SRST_PULLS_TRST)==0) + enum reset_types jtag_reset_config = jtag_get_reset_config(); + if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) { check_pc = 1; } @@ -765,8 +940,8 @@ int arm7_9_poll(target_t *target) if (check_pc) { reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1); - u32 t=*((u32 *)reg->value); - if (t!=0) + uint32_t t=*((uint32_t *)reg->value); + if (t != 0) { LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?"); } @@ -790,7 +965,7 @@ int arm7_9_poll(target_t *target) } if (target->state != TARGET_HALTED) { - LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state); + LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state); } } else @@ -802,21 +977,25 @@ int arm7_9_poll(target_t *target) return ERROR_OK; } -/* - Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S - in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock - while the core is held in reset(SRST). It isn't possible to program the halt - condition once reset was asserted, hence a hook that allows the target to set - up its reset-halt condition prior to asserting reset. -*/ - +/** + * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in + * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is + * affected) completely stop the JTAG clock while the core is held in reset + * (SRST). It isn't possible to program the halt condition once reset is + * asserted, hence a hook that allows the target to set up its reset-halt + * condition is setup prior to asserting reset. + * + * @param target Pointer to an ARM7/9 target to assert reset on + * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK + */ int arm7_9_assert_reset(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); + enum reset_types jtag_reset_config = jtag_get_reset_config(); if (!(jtag_reset_config & RESET_HAS_SRST)) { LOG_ERROR("Can't assert SRST"); @@ -848,7 +1027,7 @@ int arm7_9_assert_reset(target_t *target) } } - /* here we should issue a srst only, but we may have to assert trst as well */ + /* here we should issue an SRST only, but we may have to assert TRST as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) { jtag_add_reset(1, 1); @@ -857,45 +1036,52 @@ int arm7_9_assert_reset(target_t *target) jtag_add_reset(0, 1); } - target->state = TARGET_RESET; jtag_add_sleep(50000); armv4_5_invalidate_core_regs(target); - if ((target->reset_halt)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)==0)) + if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)) { /* debug entry was already prepared in arm7_9_assert_reset() */ target->debug_reason = DBG_REASON_DBGRQ; } return ERROR_OK; - } +/** + * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST + * and the target is being reset into a halt, a warning will be triggered + * because it is not possible to reset into a halted mode in this case. The + * target is halted using the target's functions. + * + * @param target Pointer to the target to have the reset deasserted + * @return ERROR_OK or an error from polling or halting the target + */ int arm7_9_deassert_reset(target_t *target) { - int retval=ERROR_OK; + int retval = ERROR_OK; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); - + target_state_name(target)); /* deassert reset lines */ jtag_add_reset(0, 0); - if (target->reset_halt&&(jtag_reset_config & RESET_SRST_PULLS_TRST)!=0) + enum reset_types jtag_reset_config = jtag_get_reset_config(); + if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) { LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset."); /* set up embedded ice registers again */ - if ((retval=target->type->examine(target))!=ERROR_OK) + if ((retval = target_examine_one(target)) != ERROR_OK) return retval; - if ((retval=target_poll(target))!=ERROR_OK) + if ((retval = target_poll(target)) != ERROR_OK) { return retval; } - if ((retval=target_halt(target))!=ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) { return retval; } @@ -904,6 +1090,15 @@ int arm7_9_deassert_reset(target_t *target) return retval; } +/** + * Clears the halt condition for an ARM7/9 target. If it isn't coming out of + * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset + * vector catch was used, it is restored. Otherwise, the control value is + * restored and the watchpoint unit is restored if it was in use. + * + * @param target Pointer to the ARM7/9 target to have halt cleared + * @return Always ERROR_OK + */ int arm7_9_clear_halt(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -952,6 +1147,16 @@ int arm7_9_clear_halt(target_t *target) return ERROR_OK; } +/** + * Issue a software reset and halt to an ARM7/9 target. The target is halted + * and then there is a wait until the processor shows the halt. This wait can + * timeout and results in an error being returned. The software reset involves + * clearing the halt, updating the debug control register, changing to ARM mode, + * reset of the program counter, and reset of all of the registers. + * + * @param target Pointer to the ARM7/9 target to be reset and halted by software + * @return Error status if any of the commands fail, otherwise ERROR_OK + */ int arm7_9_soft_reset_halt(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -961,19 +1166,19 @@ int arm7_9_soft_reset_halt(struct target_s *target) int i; int retval; - if ((retval=target_halt(target))!=ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0) break; embeddedice_read_reg(dbg_stat); - if ((retval=jtag_execute_queue())!=ERROR_OK) + if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; - if (debug_level>=3) + if (debug_level >= 3) { alive_sleep(100); } else @@ -1004,7 +1209,7 @@ int arm7_9_soft_reset_halt(struct target_s *target) /* if the target is in Thumb state, change to ARM state */ if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) { - u32 r0_thumb, pc_thumb; + uint32_t r0_thumb, pc_thumb; LOG_DEBUG("target entered debug from Thumb state, changing to ARM"); /* Entered debug from Thumb mode */ armv4_5->core_state = ARMV4_5_STATE_THUMB; @@ -1049,9 +1254,18 @@ int arm7_9_soft_reset_halt(struct target_s *target) return ERROR_OK; } +/** + * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ + * line or by programming a watchpoint to trigger on any address. It is + * considered a bug to call this function while the target is in the + * TARGET_RESET state. + * + * @param target Pointer to the ARM7/9 target to be halted + * @return Always ERROR_OK + */ int arm7_9_halt(target_t *target) { - if (target->state==TARGET_RESET) + if (target->state == TARGET_RESET) { LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()"); return ERROR_OK; @@ -1062,7 +1276,7 @@ int arm7_9_halt(target_t *target) reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; LOG_DEBUG("target->state: %s", - Jim_Nvp_value2name_simple( nvp_target_state,target->state)->name); + target_state_name(target)); if (target->state == TARGET_HALTED) { @@ -1101,13 +1315,24 @@ int arm7_9_halt(target_t *target) return ERROR_OK; } +/** + * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the + * ARM. The JTAG queue is then executed and the reason for debug entry is + * examined. Once done, the target is verified to be halted and the processor + * is forced into ARM mode. The core registers are saved for the current core + * mode and the program counter (register 15) is updated as needed. The core + * registers and CPSR and SPSR are saved for restoration later. + * + * @param target Pointer to target that is entering debug mode + * @return Error code if anything fails, otherwise ERROR_OK + */ int arm7_9_debug_entry(target_t *target) { int i; - u32 context[16]; - u32* context_p[16]; - u32 r0_thumb, pc_thumb; - u32 cpsr; + uint32_t context[16]; + uint32_t* context_p[16]; + uint32_t r0_thumb, pc_thumb; + uint32_t cpsr; int retval; /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; @@ -1157,7 +1382,7 @@ int arm7_9_debug_entry(target_t *target) /* Entered debug from Thumb mode */ armv4_5->core_state = ARMV4_5_STATE_THUMB; arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb); - LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb); + LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb); } else { @@ -1206,31 +1431,23 @@ int arm7_9_debug_entry(target_t *target) context[15] -= 3 * 4; } - if ((target->debug_reason == DBG_REASON_BREAKPOINT) - || (target->debug_reason == DBG_REASON_SINGLESTEP) - || (target->debug_reason == DBG_REASON_WATCHPOINT) - || (target->debug_reason == DBG_REASON_WPTANDBKPT) - || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0))) + if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq)) context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); - else if (target->debug_reason == DBG_REASON_DBGRQ) - context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); else - { - LOG_ERROR("unknown debug reason: %i", target->debug_reason); - } + context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2); if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=15; i++) + for (i = 0; i <= 15; i++) { - LOG_DEBUG("r%i: 0x%8.8x", i, context[i]); + LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1; } - LOG_DEBUG("entered debug state at PC 0x%x", context[15]); + LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]); if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; @@ -1238,7 +1455,7 @@ int arm7_9_debug_entry(target_t *target) /* exceptions other than USR & SYS have a saved program status register */ if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS)) { - u32 spsr; + uint32_t spsr; arm7_9->read_xpsr(target, &spsr, 1); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -1262,6 +1479,15 @@ int arm7_9_debug_entry(target_t *target) return ERROR_OK; } +/** + * Validate the full context for an ARM7/9 target in all processor modes. If + * there are any invalid registers for the target, they will all be read. This + * includes the PSR. + * + * @param target Pointer to the ARM7/9 target to capture the full context from + * @return Error if the target is not halted, has an invalid core mode, or if + * the JTAG queue fails to execute + */ int arm7_9_full_context(target_t *target) { int i; @@ -1283,10 +1509,10 @@ int arm7_9_full_context(target_t *target) /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND) * SYS shares registers with User, so we don't touch SYS */ - for(i = 0; i < 6; i++) + for (i = 0; i < 6; i++) { - u32 mask = 0; - u32* reg_p[16]; + uint32_t mask = 0; + uint32_t* reg_p[16]; int j; int valid = 1; @@ -1300,7 +1526,7 @@ int arm7_9_full_context(target_t *target) if (!valid) { - u32 tmp_cpsr; + uint32_t tmp_cpsr; /* change processor mode (and mask T bit) */ tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0; @@ -1312,7 +1538,7 @@ int arm7_9_full_context(target_t *target) { if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) { - reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value; + reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value; mask |= 1 << j; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; @@ -1326,7 +1552,7 @@ int arm7_9_full_context(target_t *target) /* check if the PSR has to be read */ if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0) { - arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1); + arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1); ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; } @@ -1343,6 +1569,18 @@ int arm7_9_full_context(target_t *target) return ERROR_OK; } +/** + * Restore the processor context on an ARM7/9 target. The full processor + * context is analyzed to see if any of the registers are dirty on this end, but + * have a valid new value. If this is the case, the processor is changed to the + * appropriate mode and the new register values are written out to the + * processor. If there happens to be a dirty register with an invalid value, an + * error will be logged. + * + * @param target Pointer to the ARM7/9 target to have its context restored + * @return Error status if the target is not halted or the core mode in the + * armv4_5 struct is invalid. + */ int arm7_9_restore_context(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1406,13 +1644,13 @@ int arm7_9_restore_context(target_t *target) if (dirty) { - u32 mask = 0x0; + uint32_t mask = 0x0; int num_regs = 0; - u32 regs[16]; + uint32_t regs[16]; if (mode_change) { - u32 tmp_cpsr; + uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0; @@ -1435,7 +1673,7 @@ int arm7_9_restore_context(target_t *target) num_regs++; reg->dirty = 0; reg->valid = 1; - LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]); + LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]); } } @@ -1448,7 +1686,7 @@ int arm7_9_restore_context(target_t *target) reg_arch_info = reg->arch_info; if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY)) { - LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32)); + LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32)); arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1); } } @@ -1457,25 +1695,25 @@ int arm7_9_restore_context(target_t *target) if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode)) { /* restore processor mode (mask T bit) */ - u32 tmp_cpsr; + uint32_t tmp_cpsr; tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; - LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr); + LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr)); arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); } else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1) { /* CPSR has been changed, full restore necessary (mask T bit) */ - LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); + LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32)); arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; } /* restore PC */ - LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); armv4_5->core_cache->reg_list[15].dirty = 0; @@ -1485,6 +1723,14 @@ int arm7_9_restore_context(target_t *target) return ERROR_OK; } +/** + * Restart the core of an ARM7/9 target. A RESTART command is sent to the + * instruction register and the JTAG state is set to TAP_IDLE causing a core + * restart. + * + * @param target Pointer to the ARM7/9 target to be restarted + * @return Result of executing the JTAG queue + */ int arm7_9_restart_core(struct target_s *target) { armv4_5_common_t *armv4_5 = target->arch_info; @@ -1492,17 +1738,23 @@ int arm7_9_restart_core(struct target_s *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_set_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); } arm_jtag_set_instr(jtag_info, 0x4, NULL); - jtag_add_runtest(1, TAP_RTI); + jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE)); return jtag_execute_queue(); } +/** + * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are + * iterated through and are set on the target if they aren't already set. + * + * @param target Pointer to the ARM7/9 target to enable watchpoints on + */ void arm7_9_enable_watchpoints(struct target_s *target) { watchpoint_t *watchpoint = target->watchpoints; @@ -1515,6 +1767,12 @@ void arm7_9_enable_watchpoints(struct target_s *target) } } +/** + * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are + * iterated through and are set on the target. + * + * @param target Pointer to the ARM7/9 target to enable breakpoints on + */ void arm7_9_enable_breakpoints(struct target_s *target) { breakpoint_t *breakpoint = target->breakpoints; @@ -1527,8 +1785,7 @@ void arm7_9_enable_breakpoints(struct target_s *target) } } - -int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution) +int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -1553,7 +1810,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ if (!current) buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); - u32 current_pc; + uint32_t current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); /* the front-end may request us not to handle breakpoints */ @@ -1561,19 +1818,19 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ { if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)))) { - LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id ); if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK) { return retval; } /* calculate PC of next instruction */ - u32 next_pc; + uint32_t next_pc; if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { - u32 current_opcode; + uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); return retval; } @@ -1617,9 +1874,9 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ } arm7_9_debug_entry(target); - LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); + LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); - LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address); + LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) { return retval; @@ -1688,15 +1945,15 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_ return ERROR_OK; } -void arm7_9_enable_eice_step(target_t *target, u32 next_pc) +void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - u32 current_pc; + uint32_t current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - if(next_pc != current_pc) + if (next_pc != current_pc) { /* setup an inverse breakpoint on the current PC * - comparator 1 matches the current address @@ -1705,7 +1962,7 @@ void arm7_9_enable_eice_step(target_t *target, u32 next_pc) embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE|EICE_W_CTRL_nOPC) & 0xff); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0); embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff); @@ -1742,7 +1999,7 @@ void arm7_9_disable_eice_step(target_t *target) embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]); } -int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints) +int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -1759,7 +2016,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br if (!current) buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address); - u32 current_pc; + uint32_t current_pc; current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); /* the front-end may request us not to handle breakpoints */ @@ -1773,12 +2030,12 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br target->debug_reason = DBG_REASON_SINGLESTEP; /* calculate PC of next instruction */ - u32 next_pc; + uint32_t next_pc; if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { - u32 current_opcode; + uint32_t current_opcode; target_read_u32(target, current_pc, ¤t_opcode); - LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode); + LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); return retval; } @@ -1833,13 +2090,12 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br } return err; - } int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode) { - u32* reg_p[16]; - u32 value; + uint32_t* reg_p[16]; + uint32_t value; int retval; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -1856,7 +2112,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod && (mode != armv4_5->core_mode) && (reg_mode != ARMV4_5_MODE_ANY)) { - u32 tmp_cpsr; + uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0; @@ -1900,12 +2156,11 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod } return ERROR_OK; - } -int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value) +int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value) { - u32 reg[16]; + uint32_t reg[16]; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -1920,7 +2175,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo if ((mode != ARMV4_5_MODE_ANY) && (mode != armv4_5->core_mode) && (reg_mode != ARMV4_5_MODE_ANY)) { - u32 tmp_cpsr; + uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0; @@ -1964,20 +2219,20 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo return jtag_execute_queue(); } -int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - u32 reg[16]; - int num_accesses = 0; + uint32_t reg[16]; + uint32_t num_accesses = 0; int thisrun_accesses; int i; - u32 cpsr; + uint32_t cpsr; int retval; int last_reg = 0; - LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count); if (target->state != TARGET_HALTED) { @@ -1996,14 +2251,14 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count reg[0] = address; arm7_9->write_core_regs(target, 0x1, reg); - int j=0; + int j = 0; switch (size) { case 4: while (num_accesses < count) { - u32 reg_list; + uint32_t reg_list; thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; @@ -2028,7 +2283,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count buffer += thisrun_accesses * 4; num_accesses += thisrun_accesses; - if ((j++%1024)==0) + if ((j++%1024) == 0) { keep_alive(); } @@ -2037,7 +2292,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count case 2: while (num_accesses < count) { - u32 reg_list; + uint32_t reg_list; thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; @@ -2053,7 +2308,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count retval = arm7_9_execute_fast_sys_speed(target); else retval = arm7_9_execute_sys_speed(target); - if(retval != ERROR_OK) + if (retval != ERROR_OK) { return retval; } @@ -2066,7 +2321,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count buffer += thisrun_accesses * 2; num_accesses += thisrun_accesses; - if ((j++%1024)==0) + if ((j++%1024) == 0) { keep_alive(); } @@ -2075,7 +2330,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count case 1: while (num_accesses < count) { - u32 reg_list; + uint32_t reg_list; thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; @@ -2091,7 +2346,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count retval = arm7_9_execute_fast_sys_speed(target); else retval = arm7_9_execute_sys_speed(target); - if(retval != ERROR_OK) + if (retval != ERROR_OK) { return retval; } @@ -2103,7 +2358,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count buffer += thisrun_accesses * 1; num_accesses += thisrun_accesses; - if ((j++%1024)==0) + if ((j++%1024) == 0) { keep_alive(); } @@ -2118,7 +2373,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2130,7 +2385,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT)) { - LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count); + LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0); @@ -2140,17 +2395,17 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count return ERROR_OK; } -int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; - u32 reg[16]; - int num_accesses = 0; + uint32_t reg[16]; + uint32_t num_accesses = 0; int thisrun_accesses; int i; - u32 cpsr; + uint32_t cpsr; int retval; int last_reg = 0; @@ -2184,7 +2439,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun case 4: while (num_accesses < count) { - u32 reg_list; + uint32_t reg_list; thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; @@ -2207,7 +2462,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun retval = arm7_9_execute_fast_sys_speed(target); else retval = arm7_9_execute_sys_speed(target); - if(retval != ERROR_OK) + if (retval != ERROR_OK) { return retval; } @@ -2218,7 +2473,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun case 2: while (num_accesses < count) { - u32 reg_list; + uint32_t reg_list; thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; @@ -2243,7 +2498,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun retval = arm7_9_execute_fast_sys_speed(target); else retval = arm7_9_execute_sys_speed(target); - if(retval != ERROR_OK) + if (retval != ERROR_OK) { return retval; } @@ -2255,7 +2510,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun case 1: while (num_accesses < count) { - u32 reg_list; + uint32_t reg_list; thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; @@ -2278,7 +2533,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun retval = arm7_9_execute_fast_sys_speed(target); else retval = arm7_9_execute_sys_speed(target); - if(retval != ERROR_OK) + if (retval != ERROR_OK) { return retval; } @@ -2301,7 +2556,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - for (i=0; i<=last_reg; i++) + for (i = 0; i <= last_reg; i++) ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid; arm7_9->read_xpsr(target, &cpsr, 0); @@ -2313,7 +2568,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT)) { - LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count); + LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0); @@ -2324,34 +2579,33 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun } static int dcc_count; -static u8 *dcc_buffer; - +static uint8_t *dcc_buffer; -static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info) +static int arm7_9_dcc_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - if ((retval=target_wait_state(target, TARGET_DEBUG_RUNNING, 500))!=ERROR_OK) + if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK) return retval; - int little=target->endianness==TARGET_LITTLE_ENDIAN; - int count=dcc_count; - u8 *buffer=dcc_buffer; - if (count>2) + int little = target->endianness == TARGET_LITTLE_ENDIAN; + int count = dcc_count; + uint8_t *buffer = dcc_buffer; + if (count > 2) { /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the - core function repeated. - */ + * core function repeated. */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); - buffer+=4; + buffer += 4; embeddedice_reg_t *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info; - u8 reg_addr = ice_reg->addr & 0x1f; - int chain_pos = ice_reg->jtag_info->chain_pos; + uint8_t reg_addr = ice_reg->addr & 0x1f; + jtag_tap_t *tap; + tap = ice_reg->jtag_info->tap; - embeddedice_write_dcc(chain_pos, reg_addr, buffer, little, count-2); + embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2); buffer += (count-2)*4; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little)); @@ -2365,24 +2619,22 @@ static int arm7_9_dcc_completion(struct target_s *target, u32 exit_point, int ti } } - if((retval = target_halt(target))!= ERROR_OK) + if ((retval = target_halt(target))!= ERROR_OK) { return retval; } return target_wait_state(target, TARGET_HALTED, 500); } - -static const u32 dcc_code[] = +static const uint32_t dcc_code[] = { /* MRC TST BNE MRC STR B */ 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9 }; -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)); - +int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)); -int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer) +int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -2390,18 +2642,18 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe int i; if (!arm7_9->dcc_downloads) - return target->type->write_memory(target, address, 4, count, buffer); + return target_write_memory(target, address, 4, count, buffer); /* regrab previously allocated working_area, or allocate a new one */ if (!arm7_9->dcc_working_area) { - u8 dcc_code_buf[6 * 4]; + uint8_t dcc_code_buf[6 * 4]; /* make sure we have a working area */ if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) { LOG_INFO("no working area available, falling back to memory writes"); - return target->type->write_memory(target, address, 4, count, buffer); + return target_write_memory(target, address, 4, count, buffer); } /* copy target instructions to target endianness */ @@ -2411,7 +2663,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe } /* write DCC code to working area */ - if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK) + if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK) { return retval; } @@ -2428,20 +2680,18 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe buf_set_u32(reg_params[0].value, 0, 32, address); - //armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, - // int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info)) - dcc_count=count; - dcc_buffer=buffer; + dcc_count = count; + dcc_buffer = buffer; retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, - arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address+6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); + arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion); - if (retval==ERROR_OK) + if (retval == ERROR_OK) { - u32 endaddress=buf_get_u32(reg_params[0].value, 0, 32); - if (endaddress!=(address+count*4)) + uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); + if (endaddress != (address + count*4)) { - LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress); - retval=ERROR_FAIL; + LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress); + retval = ERROR_FAIL; } } @@ -2450,14 +2700,14 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe return retval; } -int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum) +int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) { working_area_t *crc_algorithm; armv4_5_algorithm_t armv4_5_info; reg_param_t reg_params[2]; int retval; - u32 arm7_9_crc_code[] = { + uint32_t arm7_9_crc_code[] = { 0xE1A02000, /* mov r2, r0 */ 0xE3E00000, /* mov r0, #0xffffffff */ 0xE1A03001, /* mov r3, r1 */ @@ -2485,7 +2735,7 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* 0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */ }; - int i; + uint32_t i; if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK) { @@ -2493,9 +2743,9 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(u32)); i++) + for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++) { - if ((retval=target_write_u32(target, crc_algorithm->address + i*sizeof(u32), arm7_9_crc_code[i]))!=ERROR_OK) + if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK) { return retval; } @@ -2511,7 +2761,7 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* buf_set_u32(reg_params[0].value, 0, 32, address); buf_set_u32(reg_params[1].value, 0, 32, count); - if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params, + if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK) { LOG_ERROR("error executing arm7_9 crc algorithm"); @@ -2531,15 +2781,15 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* return ERROR_OK; } -int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank) +int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank) { working_area_t *erase_check_algorithm; reg_param_t reg_params[3]; armv4_5_algorithm_t armv4_5_info; int retval; - int i; + uint32_t i; - u32 erase_check_code[] = + uint32_t erase_check_code[] = { /* loop: */ 0xe4d03001, /* ldrb r3, [r0], #1 */ @@ -2557,8 +2807,8 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u } /* convert flash writing code into a buffer in target endianness */ - for (i = 0; i < (sizeof(erase_check_code)/sizeof(u32)); i++) - if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(u32), erase_check_code[i])) != ERROR_OK) + for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint32_t)); i++) + if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i])) != ERROR_OK) { return retval; } @@ -2576,7 +2826,7 @@ int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); buf_set_u32(reg_params[2].value, 0, 32, 0xff); - if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, + if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK) { destroy_reg_param(®_params[0]); @@ -2603,19 +2853,17 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands"); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); - register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register "); + register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> "); register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register "); register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, - COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); - register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)"); + COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests "); register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses "); + COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses "); register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, - COMMAND_ANY, "use DCC downloads for larger memory writes "); + COMMAND_ANY, "use DCC downloads for larger memory writes "); armv4_5_register_commands(cmd_ctx); @@ -2626,7 +2874,7 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx) int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { - u32 value; + uint32_t value; int spsr; int retval; target_t *target = get_current_target(cmd_ctx); @@ -2647,7 +2895,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm if (argc < 2) { - command_print(cmd_ctx, "usage: write_xpsr "); + command_print(cmd_ctx, "usage: write_xpsr "); return ERROR_OK; } @@ -2670,7 +2918,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { - u32 value; + uint32_t value; int rotate; int spsr; int retval; @@ -2692,7 +2940,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char if (argc < 3) { - command_print(cmd_ctx, "usage: write_xpsr_im8 "); + command_print(cmd_ctx, "usage: write_xpsr_im8 "); return ERROR_OK; } @@ -2712,8 +2960,8 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { - u32 value; - u32 mode; + uint32_t value; + uint32_t mode; int num; target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; @@ -2742,10 +2990,8 @@ int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char value = strtoul(args[2], NULL, 0); return arm7_9_write_core_reg(target, num, mode, value); - } - int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); @@ -2770,7 +3016,7 @@ int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, ch } else { - command_print(cmd_ctx, "usage: arm7_9 dbgrq "); + command_print(cmd_ctx, "usage: arm7_9 dbgrq "); } } @@ -2803,7 +3049,7 @@ int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, } else { - command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); + command_print(cmd_ctx, "usage: arm7_9 fast_memory_access "); } } @@ -2836,7 +3082,7 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char } else { - command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); + command_print(cmd_ctx, "usage: arm7_9 dcc_downloads "); } } @@ -2852,7 +3098,7 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) arm7_9->common_magic = ARM7_9_COMMON_MAGIC; - if((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) + if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK) { return retval; } @@ -2885,12 +3131,12 @@ int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9) armv4_5->write_core_reg = arm7_9_write_core_reg; armv4_5->full_context = arm7_9_full_context; - if((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) + if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK) { return retval; } - if((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) + if ((retval = target_register_timer_callback(arm7_9_handle_target_request, 1, 1, target)) != ERROR_OK) { return retval; }