X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm7_9_common.h;h=811f9c593e959c1e135b0c91afc72029dad4c147;hp=b3c3c583366ede154533feb05ba825dbe83d4462;hb=47b8cf84202bf792cf66fbfa01169e9592236b8a;hpb=c993d75d1febddc96286b0d41b682ab81bf28684 diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index b3c3c58336..811f9c593e 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -22,31 +22,29 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ -#ifndef ARM7_9_COMMON_H -#define ARM7_9_COMMON_H -#include "breakpoints.h" -#include "etm.h" +#ifndef OPENOCD_TARGET_ARM7_9_COMMON_H +#define OPENOCD_TARGET_ARM7_9_COMMON_H + +#include "arm.h" +#include "arm_jtag.h" #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */ /** * Structure for items that are common between both ARM7 and ARM9 targets. */ -typedef struct arm7_9_common_s -{ +struct arm7_9_common { + struct arm arm; uint32_t common_magic; - arm_jtag_t jtag_info; /**< JTAG information for target */ - reg_cache_t *eice_cache; /**< Embedded ICE register cache */ + struct arm_jtag jtag_info; /**< JTAG information for target */ + struct reg_cache *eice_cache; /**< Embedded ICE register cache */ uint32_t arm_bkpt; /**< ARM breakpoint instruction */ uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */ - bool force_hw_bkpts; int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */ int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */ @@ -69,89 +67,129 @@ typedef struct arm7_9_common_s bool fast_memory_access; bool dcc_downloads; - etm_context_t *etm_ctx; - - struct working_area_s *dcc_working_area; - - int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */ - - void (*change_to_arm)(target_t *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */ - - void (*read_core_regs)(target_t *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */ - void (*read_core_regs_target_buffer)(target_t *target, uint32_t mask, void *buffer, int size); - void (*read_xpsr)(target_t *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */ + struct working_area *dcc_working_area; - void (*write_xpsr)(target_t *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */ - void (*write_xpsr_im8)(target_t *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */ - void (*write_core_regs)(target_t *target, uint32_t mask, uint32_t core_regs[16]); + int (*examine_debug_reason)(struct target *target); + /**< Function for determining why debug state was entered */ - void (*load_word_regs)(target_t *target, uint32_t mask); - void (*load_hword_reg)(target_t *target, int num); - void (*load_byte_reg)(target_t *target, int num); + void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); + /**< Function for changing from Thumb to ARM mode */ - void (*store_word_regs)(target_t *target, uint32_t mask); - void (*store_hword_reg)(target_t *target, int num); - void (*store_byte_reg)(target_t *target, int num); + void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); + /**< Function for reading the core registers */ - void (*write_pc)(target_t *target, uint32_t pc); /**< Function for writing to the program counter */ - void (*branch_resume)(target_t *target); - void (*branch_resume_thumb)(target_t *target); + void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, + void *buffer, int size); + void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); + /**< Function for reading CPSR or SPSR */ - void (*enable_single_step)(target_t *target, uint32_t next_pc); - void (*disable_single_step)(target_t *target); + void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); + /**< Function for writing to CPSR or SPSR */ - void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */ + void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); + /**< Function for writing an immediate value to CPSR or SPSR */ - void (*pre_debug_entry)(target_t *target); /**< Callback function called before entering debug mode */ - void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */ + void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]); - void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */ - void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */ + void (*load_word_regs)(struct target *target, uint32_t mask); + void (*load_hword_reg)(struct target *target, int num); + void (*load_byte_reg)(struct target *target, int num); - armv4_5_common_t armv4_5_common; - void *arch_info; + void (*store_word_regs)(struct target *target, uint32_t mask); + void (*store_hword_reg)(struct target *target, int num); + void (*store_byte_reg)(struct target *target, int num); -} arm7_9_common_t; + void (*write_pc)(struct target *target, uint32_t pc); + /**< Function for writing to the program counter */ -int arm7_9_register_commands(struct command_context_s *cmd_ctx); + void (*branch_resume)(struct target *target); + void (*branch_resume_thumb)(struct target *target); -int arm7_9_poll(target_t *target); + void (*enable_single_step)(struct target *target, uint32_t next_pc); + void (*disable_single_step)(struct target *target); -int arm7_9_target_request_data(target_t *target, uint32_t size, uint8_t *buffer); + void (*set_special_dbgrq)(struct target *target); + /**< Function for setting DBGRQ if the normal way won't work */ -int arm7_9_setup(target_t *target); -int arm7_9_assert_reset(target_t *target); -int arm7_9_deassert_reset(target_t *target); -int arm7_9_reset_request_halt(target_t *target); -int arm7_9_early_halt(target_t *target); -int arm7_9_soft_reset_halt(struct target_s *target); -int arm7_9_prepare_reset_halt(struct target_s *target); + int (*post_debug_entry)(struct target *target); + /**< Callback function called after entering debug mode */ -int arm7_9_halt(target_t *target); -int arm7_9_full_context(target_t *target); -int arm7_9_restore_context(target_t *target); -int arm7_9_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution); -int arm7_9_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints); -int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode); -int arm7_9_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm7_9_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm7_9_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer); -int arm7_9_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum); -int arm7_9_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank); + void (*pre_restore_context)(struct target *target); + /**< Callback function called before restoring the processor context */ -int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, uint32_t entry_point, void *arch_info); + /** + * Variant specific memory write function that does not dispatch to bulk_write_memory. + * Used as a fallback when bulk writes are unavailable, or for writing data needed to + * do the bulk writes. + */ + int (*write_memory)(struct target *target, target_addr_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); + /** + * Write target memory in multiples of 4 bytes, optimized for + * writing large quantities of data. + */ + int (*bulk_write_memory)(struct target *target, target_addr_t address, + uint32_t count, const uint8_t *buffer); +}; -int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint); -int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint); -int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint); - -void arm7_9_enable_eice_step(target_t *target, uint32_t next_pc); -void arm7_9_disable_eice_step(target_t *target); - -int arm7_9_execute_sys_speed(struct target_s *target); - -int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9); -int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p); +static inline struct arm7_9_common *target_to_arm7_9(struct target *target) +{ + return container_of(target->arch_info, struct arm7_9_common, arm); +} -#endif /* ARM7_9_COMMON_H */ +static inline bool is_arm7_9(struct arm7_9_common *arm7_9) +{ + return arm7_9->common_magic == ARM7_9_COMMON_MAGIC; +} + +extern const struct command_registration arm7_9_command_handlers[]; + +int arm7_9_poll(struct target *target); + +int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer); + +int arm7_9_assert_reset(struct target *target); +int arm7_9_deassert_reset(struct target *target); +int arm7_9_reset_request_halt(struct target *target); +int arm7_9_early_halt(struct target *target); +int arm7_9_soft_reset_halt(struct target *target); + +int arm7_9_halt(struct target *target); +int arm7_9_resume(struct target *target, int current, target_addr_t address, + int handle_breakpoints, int debug_execution); +int arm7_9_step(struct target *target, int current, target_addr_t address, + int handle_breakpoints); +int arm7_9_read_memory(struct target *target, target_addr_t address, + uint32_t size, uint32_t count, uint8_t *buffer); +int arm7_9_write_memory(struct target *target, target_addr_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); +int arm7_9_write_memory_opt(struct target *target, target_addr_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); +int arm7_9_write_memory_no_opt(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer); +int arm7_9_bulk_write_memory(struct target *target, target_addr_t address, + uint32_t count, const uint8_t *buffer); + +int arm7_9_run_algorithm(struct target *target, int num_mem_params, + struct mem_param *mem_params, int num_reg_prams, + struct reg_param *reg_param, uint32_t entry_point, void *arch_info); + +int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint); +int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint); +int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint); +int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint); + +void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc); +void arm7_9_disable_eice_step(struct target *target); + +int arm7_9_execute_sys_speed(struct target *target); + +int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9); +int arm7_9_examine(struct target *target); +int arm7_9_check_reset(struct target *target); + +int arm7_9_endianness_callback(jtag_callback_data_t pu8_in, + jtag_callback_data_t i_size, jtag_callback_data_t i_be, + jtag_callback_data_t i_flip); + +#endif /* OPENOCD_TARGET_ARM7_9_COMMON_H */