X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=03aa233df6f5eee4a210a3ec8fbd4354937a8ec2;hp=2531d9b66e49b576e640dfb50e0c680cb35c7dd7;hb=20724e33250c48aa8f1e9332d1704dd8d58cda9b;hpb=1e5daf5886999a8ff01a4957e17c1466d76e022d diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 2531d9b66e..03aa233df6 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -22,115 +22,103 @@ #endif #include "arm920t.h" -#include "time_support.h" +#include #include "target_type.h" - +#include "register.h" +#include "arm_opcodes.h" + + +/* + * For information about the ARM920T, see ARM DDI 0151C especially + * Chapter 9 about debug support, which shows how to manipulate each + * of the different scan chains: + * + * 0 ... ARM920 signals, e.g. to rest of SOC (unused here) + * 1 ... debugging; watchpoint and breakpoint status, etc; also + * MMU and cache access in conjunction with scan chain 15 + * 2 ... EmbeddedICE + * 3 ... external boundary scan (SoC-specific, unused here) + * 4 ... access to cache tag RAM + * 6 ... ETM9 + * 15 ... access coprocessor 15, "physical" or "interpreted" modes + * "interpreted" works with a few actual MRC/MCR instructions + * "physical" provides register-like behaviors. Section 9.6.7 + * covers these details. + * + * The ARM922T is similar, but with smaller caches (8K each, vs 16K). + */ #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); - -int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm920t_target_create(struct target_s *target, Jim_Interp *interp); -int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm920t_quit(void); - +/* Table 9-8 shows scan chain 15 format during physical access mode, using a + * dedicated 6-bit address space (encoded in bits 33:38). Writes use one + * JTAG scan, while reads use two. + * + * Table 9-9 lists the thirteen registers which support physical access. + * ARM920T_CP15_PHYS_ADDR() constructs the 6-bit reg_addr parameter passed + * to arm920t_read_cp15_physical() and arm920t_write_cp15_physical(). + * + * x == bit[38] + * y == bits[37:34] + * z == bit[33] + */ #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z)) -target_type_t arm920t_target = +/* Registers supporting physical Read access (from table 9-9) */ +#define CP15PHYS_CACHETYPE ARM920T_CP15_PHYS_ADDR(0, 0x0, 1) +#define CP15PHYS_ICACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xd, 1) +#define CP15PHYS_DCACHE_IDX ARM920T_CP15_PHYS_ADDR(1, 0xe, 1) +/* NOTE: several more registers support only physical read access */ + +/* Registers supporting physical Read/Write access (from table 9-9) */ +#define CP15PHYS_CTRL ARM920T_CP15_PHYS_ADDR(0, 0x1, 0) +#define CP15PHYS_PID ARM920T_CP15_PHYS_ADDR(0, 0xd, 0) +#define CP15PHYS_TESTSTATE ARM920T_CP15_PHYS_ADDR(0, 0xf, 0) +#define CP15PHYS_ICACHE ARM920T_CP15_PHYS_ADDR(1, 0x1, 1) +#define CP15PHYS_DCACHE ARM920T_CP15_PHYS_ADDR(1, 0x2, 1) + +static int arm920t_read_cp15_physical(struct target *target, + int reg_addr, uint32_t *value) { - .name = "arm920t", - - .poll = arm7_9_poll, - .arch_state = arm920t_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm920t_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm920t_read_memory, - .write_memory = arm920t_write_memory, - .read_phys_memory = arm920t_read_phys_memory, - .write_phys_memory = arm920t_write_phys_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm920t_register_commands, - .target_create = arm920t_target_create, - .init_target = arm920t_init_target, - .examine = arm9tdmi_examine, - .quit = arm920t_quit -}; - -int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[4]; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm_jtag *jtag_info; + struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + jtag_info = &arm920t->arm7_9_common.jtag_info; + + arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); fields[1].in_value = (uint8_t *)value; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); - #ifdef _DEBUG_INSTRUCTION_EXECUTION_ +#ifdef _DEBUG_INSTRUCTION_EXECUTION_ jtag_execute_queue(); LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value); #endif @@ -138,44 +126,41 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) return ERROR_OK; } -int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value) +static int arm920t_write_cp15_physical(struct target *target, + int reg_addr, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[4]; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm_jtag *jtag_info; + struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 1; uint8_t value_buf[4]; + jtag_info = &arm920t->arm7_9_common.jtag_info; + buf_set_u32(value_buf, 0, 32, value); - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = value_buf; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value); @@ -184,45 +169,49 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value) return ERROR_OK; } -int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode) +/* See table 9-10 for scan chain 15 format during interpreted access mode. + * If the TESTSTATE register is set for interpreted access, certain CP15 + * MRC and MCR instructions may be executed through scan chain 15. + * + * Tables 9-11, 9-12, and 9-13 show which MRC and MCR instructions can be + * executed using scan chain 15 interpreted mode. + */ +static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, + uint32_t arm_opcode) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[4]; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm_jtag *jtag_info; + struct scan_field fields[4]; uint8_t access_type_buf = 0; /* interpreted access */ uint8_t reg_addr_buf = 0x0; uint8_t nr_w_buf = 0; uint8_t cp15_opcode_buf[4]; - jtag_set_end_state(TAP_IDLE); - arm_jtag_scann(jtag_info, 0xf); - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + jtag_info = &arm920t->arm7_9_common.jtag_info; + + arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &access_type_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = cp15_opcode_buf; fields[1].in_value = NULL; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 6; fields[2].out_value = ®_addr_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); @@ -232,19 +221,21 @@ int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_op if ((retval = jtag_execute_queue()) != ERROR_OK) { - LOG_ERROR("failed executing JTAG queue, exiting"); + LOG_ERROR("failed executing JTAG queue"); return retval; } return ERROR_OK; } -int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) +static int arm920t_read_cp15_interpreted(struct target *target, + uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target_to_arm(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; + struct reg *r = armv4_5->core_cache->reg_list; /* load address into R1 */ regs[1] = address; @@ -252,17 +243,17 @@ int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32 /* read-modify-write CP15 test state register * to enable interpreted access mode */ - arm920t_read_cp15_physical(target, 0x1e, &cp15c15); + arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15); jtag_execute_queue(); cp15c15 |= 1; /* set interpret mode */ - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* execute CP15 instruction and ARM load (reading from coprocessor) */ arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1)); /* disable interpreted access mode */ cp15c15 &= ~1U; /* clear interpret mode */ - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* retrieve value from R0 */ regs_p[0] = value; @@ -270,23 +261,27 @@ int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32 jtag_execute_queue(); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); + LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", + cp15_opcode, address, *value); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } -int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) +static +int arm920t_write_cp15_interpreted(struct target *target, + uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target_to_arm(target); uint32_t regs[2]; + struct reg *r = armv4_5->core_cache->reg_list; /* load value, address into R0, R1 */ regs[0] = value; @@ -295,48 +290,54 @@ int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint3 /* read-modify-write CP15 test state register * to enable interpreted access mode */ - arm920t_read_cp15_physical(target, 0x1e, &cp15c15); + arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15); jtag_execute_queue(); cp15c15 |= 1; /* set interpret mode */ - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* execute CP15 instruction and ARM store (writing to coprocessor) */ arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1)); /* disable interpreted access mode */ cp15c15 &= ~1U; /* set interpret mode */ - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ - LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address); + LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", + cp15_opcode, value, address); #endif - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; + r[0].dirty = 1; + r[1].dirty = 1; return ERROR_OK; } -uint32_t arm920t_get_ttb(target_t *target) +// EXPORTED to FA256 +uint32_t arm920t_get_ttb(struct target *target) { int retval; uint32_t ttb = 0x0; - if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK) + if ((retval = arm920t_read_cp15_interpreted(target, + /* FIXME use opcode macro */ + 0xeebf0f51, 0x0, &ttb)) != ERROR_OK) return retval; return ttb; } -void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +// EXPORTED to FA256 +void arm920t_disable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { uint32_t cp15_control; /* read cp15 control register */ - arm920t_read_cp15_physical(target, 0x2, &cp15_control); + arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); jtag_execute_queue(); if (mmu) @@ -348,15 +349,17 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ if (i_cache) cp15_control &= ~0x1000U; - arm920t_write_cp15_physical(target, 0x2, cp15_control); + arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); } -void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +// EXPORTED to FA256 +void arm920t_enable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { uint32_t cp15_control; /* read cp15 control register */ - arm920t_read_cp15_physical(target, 0x2, &cp15_control); + arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control); jtag_execute_queue(); if (mmu) @@ -368,62 +371,68 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c if (i_cache) cp15_control |= 0x1000U; - arm920t_write_cp15_physical(target, 0x2, cp15_control); + arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control); } -void arm920t_post_debug_entry(target_t *target) +// EXPORTED to FA256 +void arm920t_post_debug_entry(struct target *target) { uint32_t cp15c15; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); /* examine cp15 control reg */ - arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg); + arm920t_read_cp15_physical(target, + CP15PHYS_CTRL, &arm920t->cp15_control_reg); jtag_execute_queue(); - LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg); + LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg); if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1) { uint32_t cache_type_reg; /* identify caches */ - arm920t_read_cp15_physical(target, 0x1, &cache_type_reg); + arm920t_read_cp15_physical(target, + CP15PHYS_CACHETYPE, &cache_type_reg); jtag_execute_queue(); - armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache); + armv4_5_identify_cache(cache_type_reg, + &arm920t->armv4_5_mmu.armv4_5_cache); } - arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0; - arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0; - arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0; + arm920t->armv4_5_mmu.mmu_enabled = + (arm920t->cp15_control_reg & 0x1U) ? 1 : 0; + arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = + (arm920t->cp15_control_reg & 0x4U) ? 1 : 0; + arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = + (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0; /* save i/d fault status and address register */ + /* FIXME use opcode macros */ arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr); arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr); arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far); arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far); - LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "", + LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 + ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32, arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far); if (arm920t->preserve_cache) { /* read-modify-write CP15 test state register * to disable I/D-cache linefills */ - arm920t_read_cp15_physical(target, 0x1e, &cp15c15); + arm920t_read_cp15_physical(target, + CP15PHYS_TESTSTATE, &cp15c15); jtag_execute_queue(); cp15c15 |= 0x600; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); } } -void arm920t_pre_restore_context(target_t *target) +// EXPORTED to FA256 +void arm920t_pre_restore_context(struct target *target) { uint32_t cp15c15; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); /* restore i/d fault status and address register */ arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0); @@ -435,85 +444,92 @@ void arm920t_pre_restore_context(target_t *target) * to reenable I/D-cache linefills */ if (arm920t->preserve_cache) { - arm920t_read_cp15_physical(target, 0x1e, &cp15c15); + arm920t_read_cp15_physical(target, + CP15PHYS_TESTSTATE, &cp15c15); jtag_execute_queue(); cp15c15 &= ~0x600U; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); } } -int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; +static const char arm920_not[] = "target is not an ARM920"; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; +static int arm920t_verify_pointer(struct command_context *cmd_ctx, + struct arm920t_common *arm920t) +{ + if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { + command_print(cmd_ctx, arm920_not); + return ERROR_TARGET_INVALID; } - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } + return ERROR_OK; +} - arm9tdmi = arm7_9->arch_info; - if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) +/** Logs summary of ARM920 state for a halted target. */ +int arm920t_arch_state(struct target *target) +{ + static const char *state[] = { - return -1; - } + "disabled", "enabled" + }; + + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm *armv4_5; - arm920t = arm9tdmi->arch_info; if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { - return -1; + LOG_ERROR("BUG: %s", arm920_not); + return ERROR_TARGET_INVALID; } - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm9tdmi_p = arm9tdmi; - *arm920t_p = arm920t; + armv4_5 = &arm920t->arm7_9_common.armv4_5_common; + + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", + state[arm920t->armv4_5_mmu.mmu_enabled], + state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], + state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); return ERROR_OK; } -int arm920t_arch_state(struct target_s *target) +static int arm920_mmu(struct target *target, int *enabled) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + if (target->state != TARGET_HALTED) { + LOG_ERROR("%s: target not halted", __func__); + return ERROR_TARGET_INVALID; + } - char *state[] = - { - "disabled", "enabled" - }; + *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled; + return ERROR_OK; +} - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) +static int arm920_virt2phys(struct target *target, + uint32_t virt, uint32_t *phys) +{ + int type; + uint32_t cb; + int domain; + uint32_t ap; + struct arm920t_common *arm920t = target_to_arm920(target); + + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, + &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap, &ret); + if (retval != ERROR_OK) + return retval; + if (type == -1) { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + return ret; } - - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), - state[arm920t->armv4_5_mmu.mmu_enabled], - state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], - state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); - + *phys = ret; return ERROR_OK; } -int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +/** Reads a buffer, in the specified word size, with current MMU settings. */ +int arm920t_read_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -523,72 +539,189 @@ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size } -int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm920t_read_phys_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); - return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer); + return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, + address, size, count, buffer); } -int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +static int arm920t_write_phys_memory(struct target *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); - return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer); + return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, + address, size, count, buffer); } -int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) +/** Writes a buffer, in the specified word size, with current MMU settings. */ +int arm920t_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; - - if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) - return retval; - - if (((size == 4) || (size == 2)) && (count == 1)) + const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */ + struct arm920t_common *arm920t = target_to_arm920(target); + + /* FIX!!!! this should be cleaned up and made much more general. The + * plan is to write up and test on arm920t specifically and + * then generalize and clean up afterwards. + * + * Also it should be moved to the callbacks that handle breakpoints + * specifically and not the generic memory write fn's. See XScale code. + */ + if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && + ((size==2) || (size==4))) { + /* special case the handling of single word writes to + * bypass MMU, to allow implementation of breakpoints + * in memory marked read only + * by MMU + */ + int type; + uint32_t cb; + int domain; + uint32_t ap; + uint32_t pa; + + /* + * We need physical address and cb + */ + retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, + address, &type, &cb, &domain, &ap, &pa); + if (retval != ERROR_OK) + return retval; + if (type == -1) + return pa; + if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { - LOG_DEBUG("D-Cache enabled, writing through to main memory"); - uint32_t pa, cb, ap; - int type, domain; + if (cb & 0x1) + { + LOG_DEBUG("D-Cache buffered, " + "drain write buffer"); + /* + * Buffered ? + * Drain write buffer - MCR p15,0,Rd,c7,c10,4 + */ + + retval = arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(15, 0, 0, 7, 10, 4), + 0x0, 0); + if (retval != ERROR_OK) + return retval; + } - pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap); - if (type == -1) - return ERROR_OK; - /* cacheable & bufferable means write-back region */ - if (cb == 3) - armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer); + if (cb == 0x3) + { + /* + * Write back memory ? -> clean cache + * + * There is no way to clean cache lines using + * cp15 scan chain, so copy the full cache + * line from cache to physical memory. + */ + uint8_t data[32]; + + LOG_DEBUG("D-Cache in 'write back' mode, " + "flush cache line"); + + retval = target_read_memory(target, + address & cache_mask, 1, + sizeof(data), &data[0]); + if (retval != ERROR_OK) + return retval; + + retval = armv4_5_mmu_write_physical(target, + &arm920t->armv4_5_mmu, + pa & cache_mask, 1, + sizeof(data), &data[0]); + if (retval != ERROR_OK) + return retval; + } + + /* Cached ? */ + if (cb & 0x2) + { + /* + * Cached ? -> Invalidate data cache using MVA + * + * MCR p15,0,Rd,c7,c6,1 + */ + LOG_DEBUG("D-Cache enabled, " + "invalidate cache line"); + + retval = arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0, + address & cache_mask); + if (retval != ERROR_OK) + return retval; + } } - if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + /* write directly to physical memory, + * bypassing any read only MMU bits, etc. + */ + retval = armv4_5_mmu_write_physical(target, + &arm920t->armv4_5_mmu, pa, size, + count, buffer); + if (retval != ERROR_OK) + return retval; + } else + { + if ((retval = arm7_9_write_memory(target, address, + size, count, buffer)) != ERROR_OK) + return retval; + } + + /* If ICache is enabled, we have to invalidate affected ICache lines + * the DCache is forced to write-through, + * so we don't have to clean it here + */ + if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + { + if (count <= 1) + { + /* invalidate ICache single entry with MVA + * mcr 15, 0, r0, cr7, cr5, {1} + */ + LOG_DEBUG("I-Cache enabled, " + "invalidating affected I-Cache line"); + retval = arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(15, 0, 0, 7, 5, 1), + 0x0, address & cache_mask); + if (retval != ERROR_OK) + return retval; + } + else { - LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line"); - arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address); + /* invalidate ICache + * mcr 15, 0, r0, cr7, cr5, {0} + */ + retval = arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(15, 0, 0, 7, 5, 0), + 0x0, 0x0); + if (retval != ERROR_OK) + return retval; } } return retval; } -int arm920t_soft_reset_halt(struct target_s *target) +// EXPORTED to FA256 +int arm920t_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) { @@ -599,7 +732,8 @@ int arm920t_soft_reset_halt(struct target_s *target) int timeout; while (!(timeout = ((timeval_ms()-then) > 1000))) { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) + == 0) { embeddedice_read_reg(dbg_stat); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -628,53 +762,48 @@ int arm920t_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; - /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; + /* start fetching from 0x0 */ + buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); + armv4_5->pc->dirty = 1; + armv4_5->pc->valid = 1; arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; - if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK) - { - return retval; - } - - return ERROR_OK; + return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } -int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +/* FIXME remove forward decls */ +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value); +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value); + +static int arm920t_init_arch_info(struct target *target, + struct arm920t_common *arm920t, struct jtag_tap *tap) { - arm9tdmi_init_target(cmd_ctx, target); + struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; - return ERROR_OK; -} + arm7_9->armv4_5_common.mrc = arm920t_mrc; + arm7_9->armv4_5_common.mcr = arm920t_mcr; -int arm920t_quit(void) -{ - return ERROR_OK; -} + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); -int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap) -{ - arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; - - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); - - arm9tdmi->arch_info = arm920t; arm920t->common_magic = ARM920T_COMMON_MAGIC; arm7_9->post_debug_entry = arm920t_post_debug_entry; @@ -701,44 +830,21 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap return ERROR_OK; } -int arm920t_target_create(struct target_s *target, Jim_Interp *interp) -{ - arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t)); - - arm920t_init_arch_info(target, arm920t, target->tap); - - return ERROR_OK; -} - -int arm920t_register_commands(struct command_context_s *cmd_ctx) +static int arm920t_target_create(struct target *target, Jim_Interp *interp) { - int retval; - command_t *arm920t_cmd; - - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands"); + struct arm920t_common *arm920t; - register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) [value] [address]"); - register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); - - register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content"); - register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content"); - - return retval; + arm920t = calloc(1,sizeof(struct arm920t_common)); + return arm920t_init_arch_info(target, arm920t, target->tap); } -int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_read_cache_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -746,16 +852,21 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c uint32_t C15_C_D_Ind, C15_C_I_Ind; int i; FILE *output; - arm920t_cache_line_t d_cache[8][64], i_cache[8][64]; + struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; int segment, index; + struct reg *r; - if (argc != 1) + retval = arm920t_verify_pointer(CMD_CTX, arm920t); + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_cache "); + command_print(CMD_CTX, "usage: arm920t read_cache "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening cache content file"); return ERROR_OK; @@ -764,33 +875,28 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c for (i = 0; i < 16; i++) regs_p[i] = ®s[i]; - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - /* disable MMU and Caches */ - arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); + arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } cp15_ctrl_saved = cp15_ctrl; - cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl); + cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED + | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); + arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl); /* read CP15 test state register */ - arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15); + arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15); jtag_execute_queue(); /* read DCache content */ fprintf(output, "DCache:\n"); /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ - for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++) + for (segment = 0; + segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; + segment++) { fprintf(output, "\nsegment: %i\n----------", segment); @@ -800,40 +906,53 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* D CAM Read, loads current victim into C15.C.D.Ind */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0)); /* read current victim */ - arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind); + arm920t_read_cp15_physical(target, + CP15PHYS_DCACHE_IDX, &C15_C_D_Ind); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); for (index = 0; index < 64; index++) { - /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ + /* Ra: + * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) + */ regs[0] = 0x0 | (segment << 5) | (index << 26); arm9tdmi_write_core_regs(target, 0x1, regs); /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write DCache victim */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); /* Read D RAM */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,2,0,15,10,2), + ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); /* Read D CAM */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,2,0,15,6,2), + ARMV4_5_LDR(9, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* read D RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); @@ -846,12 +965,16 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* mask LFSR[6] */ regs[9] &= 0xfffffffe; - fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); + fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" + PRIx32 ", content (%s):\n", + segment, index, regs[9], + (regs[9] & 0x10) ? "valid" : "invalid"); for (i = 1; i < 9; i++) { d_cache[segment][index].data[i] = regs[i]; - fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]); + fprintf(output, "%i: 0x%8.8" PRIx32 "\n", + i-1, regs[i]); } } @@ -862,21 +985,26 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write DCache victim */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); } /* read ICache content */ fprintf(output, "ICache:\n"); /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ - for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++) + for (segment = 0; + segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; + segment++) { fprintf(output, "segment: %i\n----------", segment); @@ -886,40 +1014,53 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* I CAM Read, loads current victim into C15.C.I.Ind */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0)); /* read current victim */ - arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind); + arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX, + &C15_C_I_Ind); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); for (index = 0; index < 64; index++) { - /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ + /* Ra: + * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) + */ regs[0] = 0x0 | (segment << 5) | (index << 26); arm9tdmi_write_core_regs(target, 0x1, regs); /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write ICache victim */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); /* Read I RAM */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,2,0,15,9,2), + ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); /* Read I CAM */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,2,0,15,5,2), + ARMV4_5_LDR(9, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* read I RAM and CAM content */ arm9tdmi_read_core_regs(target, 0x3fe, regs_p); @@ -932,12 +1073,16 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* mask LFSR[6] */ regs[9] &= 0xfffffffe; - fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); + fprintf(output, "\nsegment: %i, index: %i, " + "CAM: 0x%8.8" PRIx32 ", content (%s):\n", + segment, index, regs[9], + (regs[9] & 0x10) ? "valid" : "invalid"); for (i = 1; i < 9; i++) { i_cache[segment][index].data[i] = regs[i]; - fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]); + fprintf(output, "%i: 0x%8.8" PRIx32 "\n", + i-1, regs[i]); } } @@ -947,50 +1092,57 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write ICache victim */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); } /* restore CP15 MMU and Cache settings */ - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); + arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved); - command_print(cmd_ctx, "cache content successfully output to %s", args[0]); + command_print(CMD_CTX, "cache content successfully output to %s", + CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty. */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } -int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_read_mmu_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -998,16 +1150,21 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd int i; FILE *output; uint32_t Dlockdown, Ilockdown; - arm920t_tlb_entry_t d_tlb[64], i_tlb[64]; + struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; + struct reg *r; + + retval = arm920t_verify_pointer(CMD_CTX, arm920t); + if (retval != ERROR_OK) + return retval; - if (argc != 1) + if (CMD_ARGC != 1) { - command_print(cmd_ctx, "usage: arm920t read_mmu "); + command_print(CMD_CTX, "usage: arm920t read_mmu "); return ERROR_OK; } - if ((output = fopen(args[0], "w")) == NULL) + if ((output = fopen(CMD_ARGV[0], "w")) == NULL) { LOG_DEBUG("error opening mmu content file"); return ERROR_OK; @@ -1016,26 +1173,19 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd for (i = 0; i < 16; i++) regs_p[i] = ®s[i]; - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - /* disable MMU and Caches */ - arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); + arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } cp15_ctrl_saved = cp15_ctrl; - cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl); + cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED + | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); + arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl); /* read CP15 test state register */ - arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15); + arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; @@ -1046,14 +1196,15 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* Read D TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* read D TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); @@ -1066,23 +1217,30 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd for (victim = 0; victim < 64; victim += 8) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] - * base remains unchanged, victim goes through entries 0 to 63 */ + * base remains unchanged, victim goes through entries 0 to 63 + */ regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write D TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,10,0,0), + ARMV4_5_STR(1, 0)); /* Read D TLB CAM */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,4,0,15,6,4), + ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* read D TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); @@ -1098,26 +1256,32 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd for (victim = 0; victim < 64; victim++) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] - * base remains unchanged, victim goes through entries 0 to 63 */ + * base remains unchanged, victim goes through entries 0 to 63 + */ regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write D TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); /* Read D TLB RAM1 */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0)); /* Read D TLB RAM2 */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* read D TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); @@ -1135,21 +1299,23 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd arm9tdmi_write_core_regs(target, 0x2, regs); /* Write D TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); /* prepare reading I TLB content * */ /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* Read I TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15); /* read I TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); @@ -1162,23 +1328,30 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd for (victim = 0; victim < 64; victim += 8) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] - * base remains unchanged, victim goes through entries 0 to 63 */ + * base remains unchanged, victim goes through entries 0 to 63 + */ regs[1] = (Ilockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write I TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,10,0,1), + ARMV4_5_STR(1, 0)); /* Read I TLB CAM */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,4,0,15,5,4), + ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* read I TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); @@ -1194,26 +1367,32 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd for (victim = 0; victim < 64; victim++) { /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] - * base remains unchanged, victim goes through entries 0 to 63 */ + * base remains unchanged, victim goes through entries 0 to 63 + */ regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); /* set interpret mode */ cp15c15 |= 0x1; - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* Write I TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); /* Read I TLB RAM1 */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0)); /* Read I TLB RAM2 */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0)); /* clear interpret mode */ cp15c15 &= ~0x1; - arm920t_write_cp15_physical(target, 0x1e, cp15c15); + arm920t_write_cp15_physical(target, + CP15PHYS_TESTSTATE, cp15c15); /* read I TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); @@ -1231,80 +1410,92 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd arm9tdmi_write_core_regs(target, 0x2, regs); /* Write I TLB lockdown */ - arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); + arm920t_execute_cp15(target, + ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); /* restore CP15 MMU and Cache settings */ - arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); + arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved); /* output data to file */ fprintf(output, "D TLB content:\n"); for (i = 0; i < 64; i++) { - fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); + fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 + " 0x%8.8" PRIx32 " %s\n", + i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, + (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); } fprintf(output, "\n\nI TLB content:\n"); for (i = 0; i < 64; i++) { - fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); + fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 + " 0x%8.8" PRIx32 " %s\n", + i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, + (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); } - command_print(cmd_ctx, "mmu content successfully output to %s", args[0]); + command_print(CMD_CTX, "mmu content successfully output to %s", + CMD_ARGV[0]); fclose(output); - if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) + if (!is_arm_mode(armv4_5->core_mode)) return ERROR_FAIL; - /* mark registers dirty */ - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; + /* force writeback of the valid data */ + r = armv4_5->core_cache->reg_list; + r[0].dirty = r[0].valid; + r[1].dirty = r[1].valid; + r[2].dirty = r[2].valid; + r[3].dirty = r[3].valid; + r[4].dirty = r[4].valid; + r[5].dirty = r[5].valid; + r[6].dirty = r[6].valid; + r[7].dirty = r[7].valid; + + r = arm_reg_current(armv4_5, 8); + r->dirty = r->valid; + + r = arm_reg_current(armv4_5, 9); + r->dirty = r->valid; return ERROR_OK; } -int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) + +COMMAND_HANDLER(arm920t_handle_cp15_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; - - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); - jtag_info = &arm7_9->jtag_info; + retval = arm920t_verify_pointer(CMD_CTX, arm920t); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(CMD_CTX, "target must be stopped for " + "\"%s\" command", CMD_NAME); return ERROR_OK; } - /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + /* one argument, read a register. + * two arguments, write it. + */ + if (CMD_ARGC >= 1) { - int address = strtoul(args[0], NULL, 0); + int address; + COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK) + if ((retval = arm920t_read_cp15_physical(target, + address, &value)) != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, + "couldn't access reg %i", address); return ERROR_OK; } if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1312,106 +1503,261 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch return retval; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32, + address, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { - uint32_t value = strtoul(args[1], NULL, 0); - if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK) + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + retval = arm920t_write_cp15_physical(target, + address, value); + if (retval != ERROR_OK) { - command_print(cmd_ctx, "couldn't access reg %i", address); + command_print(CMD_CTX, + "couldn't access reg %i", address); + /* REVISIT why lie? "return retval"? */ return ERROR_OK; } - command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value); + command_print(CMD_CTX, "%i: %8.8" PRIx32, + address, value); } } return ERROR_OK; } -int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_cp15i_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; - - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); + + retval = arm920t_verify_pointer(CMD_CTX, arm920t); + if (retval != ERROR_OK) + return retval; - jtag_info = &arm7_9->jtag_info; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(CMD_CTX, "target must be stopped for " + "\"%s\" command", CMD_NAME); return ERROR_OK; } - /* one or more argument, access a single register (write if second argument is given */ - if (argc >= 1) + /* one argument, read a register. + * two arguments, write it. + */ + if (CMD_ARGC >= 1) { - uint32_t opcode = strtoul(args[0], NULL, 0); + uint32_t opcode; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode); - if (argc == 1) + if (CMD_ARGC == 1) { uint32_t value; - if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK) + retval = arm920t_read_cp15_interpreted(target, + opcode, 0x0, &value); + if (retval != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, + "couldn't execute %8.8" PRIx32, + opcode); + /* REVISIT why lie? "return retval"? */ return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32, + opcode, value); } - else if (argc == 2) + else if (CMD_ARGC == 2) { - uint32_t value = strtoul(args[1], NULL, 0); - if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK) + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + retval = arm920t_write_cp15_interpreted(target, + opcode, value, 0); + if (retval != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, + "couldn't execute %8.8" PRIx32, + opcode); + /* REVISIT why lie? "return retval"? */ return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32, + opcode, value); } - else if (argc == 3) + else if (CMD_ARGC == 3) { - uint32_t value = strtoul(args[1], NULL, 0); - uint32_t address = strtoul(args[2], NULL, 0); - if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK) + uint32_t value; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + uint32_t address; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address); + retval = arm920t_write_cp15_interpreted(target, + opcode, value, address); + if (retval != ERROR_OK) { - command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); + command_print(CMD_CTX, + "couldn't execute %8.8" PRIx32, opcode); + /* REVISIT why lie? "return retval"? */ return ERROR_OK; } - command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address); + command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 + " %8.8" PRIx32, opcode, value, address); } } else { - command_print(cmd_ctx, "usage: arm920t cp15i [value] [address]"); + command_print(CMD_CTX, + "usage: arm920t cp15i [value] [address]"); } return ERROR_OK; } -int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_cache_info_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; + int retval; + struct target *target = get_current_target(CMD_CTX); + struct arm920t_common *arm920t = target_to_arm920(target); - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) + retval = arm920t_verify_pointer(CMD_CTX, arm920t); + if (retval != ERROR_OK) + return retval; + + return armv4_5_handle_cache_info_command(CMD_CTX, + &arm920t->armv4_5_mmu.armv4_5_cache); +} + + +static int arm920t_mrc(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t *value) +{ + if (cpnum!=15) { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + + /* read "to" r0 */ + return arm920t_read_cp15_interpreted(target, + ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2), + 0, value); +} + +static int arm920t_mcr(struct target *target, int cpnum, + uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, + uint32_t value) +{ + if (cpnum!=15) + { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; } - return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); + /* write "from" r0 */ + return arm920t_write_cp15_interpreted(target, + ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2), + 0, value); } + +static const struct command_registration arm920t_exec_command_handlers[] = { + { + .name = "cp15", + .handler = arm920t_handle_cp15_command, + .mode = COMMAND_EXEC, + .help = "display/modify cp15 register", + .usage = "regnum [value]", + }, + { + .name = "cp15i", + .handler = arm920t_handle_cp15i_command, + .mode = COMMAND_EXEC, + /* prefer using less error-prone "arm mcr" or "arm mrc" */ + .help = "display/modify cp15 register using ARM opcode" + " (DEPRECATED)", + .usage = "instruction [value [address]]", + }, + { + .name = "cache_info", + .handler = arm920t_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", + }, + { + .name = "read_cache", + .handler = arm920t_handle_read_cache_command, + .mode = COMMAND_EXEC, + .help = "dump I/D cache content to file", + .usage = "filename", + }, + { + .name = "read_mmu", + .handler = arm920t_handle_read_mmu_command, + .mode = COMMAND_EXEC, + .help = "dump I/D mmu content to file", + .usage = "filename", + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm920t_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm920t", + .mode = COMMAND_ANY, + .help = "arm920t command group", + .chain = arm920t_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; + +/** Holds methods for ARM920 targets. */ +struct target_type arm920t_target = +{ + .name = "arm920t", + + .poll = arm7_9_poll, + .arch_state = arm920t_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm920t_soft_reset_halt, + + .get_gdb_reg_list = arm_get_gdb_reg_list, + + .read_memory = arm920t_read_memory, + .write_memory = arm920t_write_memory, + .read_phys_memory = arm920t_read_phys_memory, + .write_phys_memory = arm920t_write_phys_memory, + .mmu = arm920_mmu, + .virt2phys = arm920_virt2phys, + + .bulk_write_memory = arm7_9_bulk_write_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .commands = arm920t_command_handlers, + .target_create = arm920t_target_create, + .init_target = arm9tdmi_init_target, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, +};