X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=03aa233df6f5eee4a210a3ec8fbd4354937a8ec2;hp=6a005d6d8ca76d5b7b497be13598f3c6ffec2f0d;hb=20724e33250c48aa8f1e9332d1704dd8d58cda9b;hpb=7b0314c377cc7c6a90db34d6d3e9e723d6d2b94a

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 6a005d6d8c..03aa233df6 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -25,6 +25,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
@@ -41,7 +42,8 @@
  *   6 ... ETM9
  *   15 ... access coprocessor 15, "physical" or "interpreted" modes
  *	"interpreted" works with a few actual MRC/MCR instructions
- *	"physical" provides register-like behaviors.
+ *	"physical" provides register-like behaviors.  Section 9.6.7
+ *	covers these details.
  *
  * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
  */
@@ -50,8 +52,33 @@
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
+/* Table 9-8 shows scan chain 15 format during physical access mode, using a
+ * dedicated 6-bit address space (encoded in bits 33:38).  Writes use one
+ * JTAG scan, while reads use two.
+ *
+ * Table 9-9 lists the thirteen registers which support physical access.
+ * ARM920T_CP15_PHYS_ADDR() constructs the 6-bit reg_addr parameter passed
+ * to arm920t_read_cp15_physical() and arm920t_write_cp15_physical().
+ *
+ *  x == bit[38]
+ *  y == bits[37:34]
+ *  z == bit[33]
+ */
 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
 
+/* Registers supporting physical Read access (from table 9-9) */
+#define CP15PHYS_CACHETYPE	ARM920T_CP15_PHYS_ADDR(0, 0x0, 1)
+#define CP15PHYS_ICACHE_IDX	ARM920T_CP15_PHYS_ADDR(1, 0xd, 1)
+#define CP15PHYS_DCACHE_IDX	ARM920T_CP15_PHYS_ADDR(1, 0xe, 1)
+/* NOTE: several more registers support only physical read access */
+
+/* Registers supporting physical Read/Write access (from table 9-9) */
+#define CP15PHYS_CTRL		ARM920T_CP15_PHYS_ADDR(0, 0x1, 0)
+#define CP15PHYS_PID		ARM920T_CP15_PHYS_ADDR(0, 0xd, 0)
+#define CP15PHYS_TESTSTATE	ARM920T_CP15_PHYS_ADDR(0, 0xf, 0)
+#define CP15PHYS_ICACHE		ARM920T_CP15_PHYS_ADDR(1, 0x1, 1)
+#define CP15PHYS_DCACHE		ARM920T_CP15_PHYS_ADDR(1, 0x2, 1)
+
 static int arm920t_read_cp15_physical(struct target *target,
 		int reg_addr, uint32_t *value)
 {
@@ -64,35 +91,30 @@ static int arm920t_read_cp15_physical(struct target *target,
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 6;
 	fields[2].out_value = &reg_addr_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	fields[1].in_value = (uint8_t *)value;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
@@ -119,31 +141,26 @@ static int arm920t_write_cp15_physical(struct target *target,
 
 	buf_set_u32(value_buf, 0, 32, value);
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = value_buf;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 6;
 	fields[2].out_value = &reg_addr_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
@@ -152,6 +169,13 @@ static int arm920t_write_cp15_physical(struct target *target,
 	return ERROR_OK;
 }
 
+/* See table 9-10 for scan chain 15 format during interpreted access mode.
+ * If the TESTSTATE register is set for interpreted access, certain CP15
+ * MRC and MCR instructions may be executed through scan chain 15.
+ *
+ * Tables 9-11, 9-12, and 9-13 show which MRC and MCR instructions can be
+ * executed using scan chain 15 interpreted mode.
+ */
 static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 		uint32_t arm_opcode)
 {
@@ -166,33 +190,28 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = cp15_opcode_buf;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 6;
 	fields[2].out_value = &reg_addr_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
@@ -224,17 +243,17 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 
 	/* read-modify-write CP15 test state register
 	* to enable interpreted access mode */
-	arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	jtag_execute_queue();
 	cp15c15 |= 1;	/* set interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* execute CP15 instruction and ARM load (reading from coprocessor) */
 	arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 
 	/* disable interpreted access mode */
 	cp15c15 &= ~1U;	/* clear interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* retrieve value from R0 */
 	regs_p[0] = value;
@@ -242,7 +261,8 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 	jtag_execute_queue();
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-	LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
+	LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x",
+			cp15_opcode, address, *value);
 #endif
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -270,20 +290,21 @@ int arm920t_write_cp15_interpreted(struct target *target,
 
 	/* read-modify-write CP15 test state register
 	* to enable interpreted access mode */
-	arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	jtag_execute_queue();
 	cp15c15 |= 1;	/* set interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* execute CP15 instruction and ARM store (writing to coprocessor) */
 	arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 
 	/* disable interpreted access mode */
 	cp15c15 &= ~1U;	/* set interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-	LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
+	LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x",
+			cp15_opcode, value, address);
 #endif
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -301,19 +322,22 @@ uint32_t arm920t_get_ttb(struct target *target)
 	int retval;
 	uint32_t ttb = 0x0;
 
-	if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
+	if ((retval = arm920t_read_cp15_interpreted(target,
+			/* FIXME use opcode macro */
+			0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 		return retval;
 
 	return ttb;
 }
 
 // EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
+void arm920t_disable_mmu_caches(struct target *target, int mmu,
+		int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
 
 	/* read cp15 control register */
-	arm920t_read_cp15_physical(target, 0x2, &cp15_control);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
 	jtag_execute_queue();
 
 	if (mmu)
@@ -325,16 +349,17 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, i
 	if (i_cache)
 		cp15_control &= ~0x1000U;
 
-	arm920t_write_cp15_physical(target, 0x2, cp15_control);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
 }
 
 // EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
+void arm920t_enable_mmu_caches(struct target *target, int mmu,
+		int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
 
 	/* read cp15 control register */
-	arm920t_read_cp15_physical(target, 0x2, &cp15_control);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
 	jtag_execute_queue();
 
 	if (mmu)
@@ -346,7 +371,7 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, in
 	if (i_cache)
 		cp15_control |= 0x1000U;
 
-	arm920t_write_cp15_physical(target, 0x2, cp15_control);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
 }
 
 // EXPORTED to FA256
@@ -356,40 +381,50 @@ void arm920t_post_debug_entry(struct target *target)
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
 	/* examine cp15 control reg */
-	arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
+	arm920t_read_cp15_physical(target,
+			CP15PHYS_CTRL, &arm920t->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
 
 	if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
 		uint32_t cache_type_reg;
 		/* identify caches */
-		arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_CACHETYPE, &cache_type_reg);
 		jtag_execute_queue();
-		armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
+		armv4_5_identify_cache(cache_type_reg,
+				&arm920t->armv4_5_mmu.armv4_5_cache);
 	}
 
-	arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
-	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
-	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
+	arm920t->armv4_5_mmu.mmu_enabled =
+			(arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+			(arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
+	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
+			(arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 
 	/* save i/d fault status and address register */
+			/* FIXME use opcode macros */
 	arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 	arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 	arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 	arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 
-	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
+	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
+		", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
 		arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 
 	if (arm920t->preserve_cache)
 	{
 		/* read-modify-write CP15 test state register
 		 * to disable I/D-cache linefills */
-		arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_TESTSTATE, &cp15c15);
 		jtag_execute_queue();
 		cp15c15 |= 0x600;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 }
 
@@ -409,10 +444,12 @@ void arm920t_pre_restore_context(struct target *target)
 	* to reenable I/D-cache linefills */
 	if (arm920t->preserve_cache)
 	{
-		arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_TESTSTATE, &cp15c15);
 		jtag_execute_queue();
 		cp15c15 &= ~0x600U;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 }
 
@@ -448,17 +485,11 @@ int arm920t_arch_state(struct target *target)
 
 	armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
-			 state[arm920t->armv4_5_mmu.mmu_enabled],
-			 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
-			 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+		 state[arm920t->armv4_5_mmu.mmu_enabled],
+		 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
+		 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 
 	return ERROR_OK;
 }
@@ -477,13 +508,28 @@ static int arm920_mmu(struct target *target, int *enabled)
 static int arm920_virt2phys(struct target *target,
 		uint32_t virt, uint32_t *phys)
 {
-	/** @todo Implement this!  */
-	LOG_ERROR("%s: not implemented", __func__);
-	return ERROR_FAIL;
+	int type;
+	uint32_t cb;
+	int domain;
+	uint32_t ap;
+	struct arm920t_common *arm920t = target_to_arm920(target);
+
+	uint32_t ret;
+	int retval = armv4_5_mmu_translate_va(target,
+			&arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap, &ret);
+	if (retval != ERROR_OK)
+		return retval;
+	if (type == -1)
+	{
+		return ret;
+	}
+	*phys = ret;
+	return ERROR_OK;
 }
 
 /** Reads a buffer, in the specified word size, with current MMU settings. */
-int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm920t_read_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 
@@ -515,34 +561,151 @@ static int arm920t_write_phys_memory(struct target *target,
 
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm920t_write_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
+	const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
+	struct arm920t_common *arm920t = target_to_arm920(target);
 
-	if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
-		return retval;
-
-	/* This fn is used to write breakpoints, so we need to make sure
-	 * that the data cache is flushed and the instruction cache is
-	 * invalidated
+	/* FIX!!!! this should be cleaned up and made much more general. The
+	 * plan is to write up and test on arm920t specifically and
+	 * then generalize and clean up afterwards.
+	 *
+	 * Also it should be moved to the callbacks that handle breakpoints
+	 * specifically and not the generic memory write fn's. See XScale code.
 	 */
-	if (((size == 4) || (size == 2)) && (count == 1))
+	if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) &&
+			((size==2) || (size==4)))
 	{
-		struct arm920t_common *arm920t = target_to_arm920(target);
+		/* special case the handling of single word writes to
+		 * bypass MMU, to allow implementation of breakpoints
+		 * in memory marked read only
+		 * by MMU
+		 */
+		int type;
+		uint32_t cb;
+		int domain;
+		uint32_t ap;
+		uint32_t pa;
+
+		/*
+		 * We need physical address and cb
+		 */
+		retval = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
+				address, &type, &cb, &domain, &ap, &pa);
+		if (retval != ERROR_OK)
+			return retval;
+		if (type == -1)
+			return pa;
 
 		if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 		{
-			LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
-			/* MCR p15,0,Rd,c7,c10,2 */
-			retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
+			if (cb & 0x1)
+			{
+				LOG_DEBUG("D-Cache buffered, "
+						"drain write buffer");
+				/*
+				 * Buffered ?
+				 * Drain write buffer - MCR p15,0,Rd,c7,c10,4
+				 */
+
+				retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 10, 4),
+					0x0, 0);
+				if (retval != ERROR_OK)
+					return retval;
+			}
+
+			if (cb == 0x3)
+			{
+				/*
+				 * Write back memory ? -> clean cache
+				 *
+				 * There is no way to clean cache lines using
+				 * cp15 scan chain, so copy the full cache
+				 * line from cache to physical memory.
+				 */
+				uint8_t data[32];
+
+				LOG_DEBUG("D-Cache in 'write back' mode, "
+						"flush cache line");
+
+				retval = target_read_memory(target,
+						address & cache_mask, 1,
+						sizeof(data), &data[0]);
+				if (retval != ERROR_OK)
+					return retval;
+
+				retval = armv4_5_mmu_write_physical(target,
+						&arm920t->armv4_5_mmu,
+						pa & cache_mask, 1,
+						sizeof(data), &data[0]);
+				if (retval != ERROR_OK)
+					return retval;
+			}
+
+			/* Cached ? */
+			if (cb & 0x2)
+			{
+				/*
+				 * Cached ? -> Invalidate data cache using MVA
+				 *
+				 * MCR p15,0,Rd,c7,c6,1
+				 */
+				LOG_DEBUG("D-Cache enabled, "
+					"invalidate cache line");
+
+				retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0,
+					address & cache_mask);
+				if (retval != ERROR_OK)
+					return retval;
+			}
+		}
+
+		/* write directly to physical memory,
+		 * bypassing any read only MMU bits, etc.
+		 */
+		retval = armv4_5_mmu_write_physical(target,
+				&arm920t->armv4_5_mmu, pa, size,
+				count, buffer);
+		if (retval != ERROR_OK)
+			return retval;
+	} else
+	{
+		if ((retval = arm7_9_write_memory(target, address,
+					size, count, buffer)) != ERROR_OK)
+			return retval;
+	}
+
+	/* If ICache is enabled, we have to invalidate affected ICache lines
+	 * the DCache is forced to write-through,
+	 * so we don't have to clean it here
+	 */
+	if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+	{
+		if (count <= 1)
+		{
+			/* invalidate ICache single entry with MVA
+			 *   mcr	15, 0, r0, cr7, cr5, {1}
+			 */
+			LOG_DEBUG("I-Cache enabled, "
+				"invalidating affected I-Cache line");
+			retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
+					0x0, address & cache_mask);
 			if (retval != ERROR_OK)
 				return retval;
 		}
-
-		if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+		else
 		{
-			LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
-			retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
+			/* invalidate ICache
+			 *  mcr	15, 0, r0, cr7, cr5, {0}
+			 */
+			retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 0),
+					0x0, 0x0);
 			if (retval != ERROR_OK)
 				return retval;
 		}
@@ -569,7 +732,8 @@ int arm920t_soft_reset_halt(struct target *target)
 	int timeout;
 	while (!(timeout = ((timeval_ms()-then) > 1000)))
 	{
-		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)
+				== 0)
 		{
 			embeddedice_read_reg(dbg_stat);
 			if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -607,21 +771,16 @@ int arm920t_soft_reset_halt(struct target *target)
 	armv4_5->cpsr->dirty = 1;
 
 	/* start fetching from 0x0 */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-	armv4_5->core_cache->reg_list[15].valid = 1;
+	buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
+	armv4_5->pc->dirty = 1;
+	armv4_5->pc->valid = 1;
 
 	arm920t_disable_mmu_caches(target, 1, 1, 1);
 	arm920t->armv4_5_mmu.mmu_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-	if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-	{
-		return retval;
-	}
-
-	return ERROR_OK;
+	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
 
 /* FIXME remove forward decls */
@@ -634,7 +793,8 @@ static int arm920t_mcr(struct target *target, int cpnum,
 		uint32_t CRn, uint32_t CRm,
 		uint32_t value);
 
-int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
+static int arm920t_init_arch_info(struct target *target,
+		struct arm920t_common *arm920t, struct jtag_tap *tap)
 {
 	struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
 
@@ -672,8 +832,9 @@ int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t
 
 static int arm920t_target_create(struct target *target, Jim_Interp *interp)
 {
-	struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
+	struct arm920t_common *arm920t;
 
+	arm920t = calloc(1,sizeof(struct arm920t_common));
 	return arm920t_init_arch_info(target, arm920t, target->tap);
 }
 
@@ -715,24 +876,27 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 		regs_p[i] = &regs[i];
 
 	/* disable MMU and Caches */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
 	cp15_ctrl_saved = cp15_ctrl;
-	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
+	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED
+		| ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl);
 
 	/* read CP15 test state register */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	jtag_execute_queue();
 
 	/* read DCache content */
 	fprintf(output, "DCache:\n");
 
 	/* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
-	for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
+	for (segment = 0;
+		segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets;
+		segment++)
 	{
 		fprintf(output, "\nsegment: %i\n----------", segment);
 
@@ -742,40 +906,53 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* D CAM Read, loads current victim into C15.C.D.Ind */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 
 		/* read current victim */
-		arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_DCACHE_IDX, &C15_C_D_Ind);
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		for (index = 0; index < 64; index++)
 		{
-			/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
+			/* Ra:
+			 * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
+			 */
 			regs[0] = 0x0 | (segment << 5) | (index << 26);
 			arm9tdmi_write_core_regs(target, 0x1, regs);
 
 			/* set interpret mode */
 			cp15c15 |= 0x1;
-			arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* Write DCache victim */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 
 			/* Read D RAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,10,2),
+				ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 
 			/* Read D CAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,6,2),
+				ARMV4_5_LDR(9, 0));
 
 			/* clear interpret mode */
 			cp15c15 &= ~0x1;
-			arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* read D RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
@@ -788,12 +965,16 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* mask LFSR[6] */
 			regs[9] &= 0xfffffffe;
-			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
+				PRIx32 ", content (%s):\n",
+				segment, index, regs[9],
+				(regs[9] & 0x10) ? "valid" : "invalid");
 
 			for (i = 1; i < 9; i++)
 			{
 				 d_cache[segment][index].data[i] = regs[i];
-				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
+				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
+						i-1, regs[i]);
 			}
 
 		}
@@ -804,21 +985,26 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write DCache victim */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 
 	/* read ICache content */
 	fprintf(output, "ICache:\n");
 
 	/* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
-	for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
+	for (segment = 0;
+		segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets;
+		segment++)
 	{
 		fprintf(output, "segment: %i\n----------", segment);
 
@@ -828,40 +1014,53 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* I CAM Read, loads current victim into C15.C.I.Ind */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 
 		/* read current victim */
-		arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
+		arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX,
+				&C15_C_I_Ind);
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		for (index = 0; index < 64; index++)
 		{
-			/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
+			/* Ra:
+			 * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
+			 */
 			regs[0] = 0x0 | (segment << 5) | (index << 26);
 			arm9tdmi_write_core_regs(target, 0x1, regs);
 
 			/* set interpret mode */
 			cp15c15 |= 0x1;
-			arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* Write ICache victim */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 
 			/* Read I RAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,9,2),
+				ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 
 			/* Read I CAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,5,2),
+				ARMV4_5_LDR(9, 0));
 
 			/* clear interpret mode */
 			cp15c15 &= ~0x1;
-			arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* read I RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
@@ -874,12 +1073,16 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* mask LFSR[6] */
 			regs[9] &= 0xfffffffe;
-			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+			fprintf(output, "\nsegment: %i, index: %i, "
+				"CAM: 0x%8.8" PRIx32 ", content (%s):\n",
+				segment, index, regs[9],
+				(regs[9] & 0x10) ? "valid" : "invalid");
 
 			for (i = 1; i < 9; i++)
 			{
 				 i_cache[segment][index].data[i] = regs[i];
-				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
+				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
+						i-1, regs[i]);
 			}
 		}
 
@@ -889,20 +1092,24 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write ICache victim */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 
 	/* restore CP15 MMU and Cache settings */
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
 
-	command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
+	command_print(CMD_CTX, "cache content successfully output to %s",
+			CMD_ARGV[0]);
 
 	fclose(output);
 
@@ -967,17 +1174,18 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 		regs_p[i] = &regs[i];
 
 	/* disable MMU and Caches */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
 	cp15_ctrl_saved = cp15_ctrl;
-	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
+	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED
+			| ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl);
 
 	/* read CP15 test state register */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
@@ -988,14 +1196,15 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 	/* set interpret mode */
 	cp15c15 |= 0x1;
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* Read D TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
 
 	/* clear interpret mode */
 	cp15c15 &= ~0x1;
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* read D TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
@@ -1008,23 +1217,30 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim += 8)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write D TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,0,0,10,0,0),
+			ARMV4_5_STR(1, 0));
 
 		/* Read D TLB CAM */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
+		arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,4,0,15,6,4),
+			ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read D TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
@@ -1040,26 +1256,32 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim++)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write D TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
 
 		/* Read D TLB RAM1 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
 
 		/* Read D TLB RAM2 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read D TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
@@ -1077,21 +1299,23 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm9tdmi_write_core_regs(target, 0x2, regs);
 
 	/* Write D TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
 
 	/* prepare reading I TLB content
 	 * */
 
 	/* set interpret mode */
 	cp15c15 |= 0x1;
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* Read I TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
 
 	/* clear interpret mode */
 	cp15c15 &= ~0x1;
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* read I TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
@@ -1104,23 +1328,30 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim += 8)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write I TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,10,0,1),
+				ARMV4_5_STR(1, 0));
 
 		/* Read I TLB CAM */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,5,4),
+				ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read I TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
@@ -1136,26 +1367,32 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim++)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write I TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
 
 		/* Read I TLB RAM1 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
 
 		/* Read I TLB RAM2 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read I TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
@@ -1173,25 +1410,33 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm9tdmi_write_core_regs(target, 0x2, regs);
 
 	/* Write I TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
 
 	/* restore CP15 MMU and Cache settings */
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
 
 	/* output data to file */
 	fprintf(output, "D TLB content:\n");
 	for (i = 0; i < 64; i++)
 	{
-		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32
+			" 0x%8.8" PRIx32 " %s\n",
+			i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2,
+			(d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
 	fprintf(output, "\n\nI TLB content:\n");
 	for (i = 0; i < 64; i++)
 	{
-		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32
+			" 0x%8.8" PRIx32 " %s\n",
+			i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2,
+			(i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
-	command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
+	command_print(CMD_CTX, "mmu content successfully output to %s",
+			CMD_ARGV[0]);
 
 	fclose(output);
 
@@ -1230,11 +1475,14 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for "
+			"\"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	/* one or more argument, access a single register (write if second argument is given */
+	/* one argument, read a register.
+	 * two arguments, write it.
+	 */
 	if (CMD_ARGC >= 1)
 	{
 		int address;
@@ -1243,9 +1491,11 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 		if (CMD_ARGC == 1)
 		{
 			uint32_t value;
-			if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
+			if ((retval = arm920t_read_cp15_physical(target,
+					address, &value)) != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't access reg %i", address);
+				command_print(CMD_CTX,
+					"couldn't access reg %i", address);
 				return ERROR_OK;
 			}
 			if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -1253,18 +1503,24 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 				return retval;
 			}
 
-			command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
+			command_print(CMD_CTX, "%i: %8.8" PRIx32,
+					address, value);
 		}
 		else if (CMD_ARGC == 2)
 		{
 			uint32_t value;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
-			if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
+			retval = arm920t_write_cp15_physical(target,
+					address, value);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't access reg %i", address);
+				command_print(CMD_CTX,
+					"couldn't access reg %i", address);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
+			command_print(CMD_CTX, "%i: %8.8" PRIx32,
+					address, value);
 		}
 	}
 
@@ -1284,11 +1540,14 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for "
+				"\"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	/* one or more argument, access a single register (write if second argument is given */
+	/* one argument, read a register.
+	 * two arguments, write it.
+	 */
 	if (CMD_ARGC >= 1)
 	{
 		uint32_t opcode;
@@ -1297,24 +1556,36 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 		if (CMD_ARGC == 1)
 		{
 			uint32_t value;
-			if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
+			retval = arm920t_read_cp15_interpreted(target,
+					opcode, 0x0, &value);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
+				command_print(CMD_CTX,
+					"couldn't execute %8.8" PRIx32,
+					opcode);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
 
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
+			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
+					opcode, value);
 		}
 		else if (CMD_ARGC == 2)
 		{
 			uint32_t value;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
-			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
+			retval = arm920t_write_cp15_interpreted(target,
+					opcode, value, 0);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
+				command_print(CMD_CTX,
+					"couldn't execute %8.8" PRIx32,
+					opcode);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
+			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
+					opcode, value);
 		}
 		else if (CMD_ARGC == 3)
 		{
@@ -1322,17 +1593,23 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 			uint32_t address;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
-			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
+			retval = arm920t_write_cp15_interpreted(target,
+					opcode, value, address);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
+				command_print(CMD_CTX,
+					"couldn't execute %8.8" PRIx32, opcode);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
+			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32
+					" %8.8" PRIx32, opcode, value, address);
 		}
 	}
 	else
 	{
-		command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
+		command_print(CMD_CTX,
+			"usage: arm920t cp15i <opcode> [value] [address]");
 	}
 
 	return ERROR_OK;
@@ -1348,7 +1625,8 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD_CTX,
+			&arm920t->armv4_5_mmu.armv4_5_cache);
 }
 
 
@@ -1389,35 +1667,39 @@ static int arm920t_mcr(struct target *target, int cpnum,
 static const struct command_registration arm920t_exec_command_handlers[] = {
 	{
 		.name = "cp15",
-		.handler = &arm920t_handle_cp15_command,
+		.handler = arm920t_handle_cp15_command,
 		.mode = COMMAND_EXEC,
 		.help = "display/modify cp15 register",
-		.usage = "<num> [value]",
+		.usage = "regnum [value]",
 	},
 	{
 		.name = "cp15i",
-		.handler = &arm920t_handle_cp15i_command,
+		.handler = arm920t_handle_cp15i_command,
 		.mode = COMMAND_EXEC,
-		.help = "display/modify cp15 (interpreted access)",
-		.usage = "<opcode> [value] [address]",
+		/* prefer using less error-prone "arm mcr" or "arm mrc" */
+		.help = "display/modify cp15 register using ARM opcode"
+			" (DEPRECATED)",
+		.usage = "instruction [value [address]]",
 	},
 	{
 		.name = "cache_info",
-		.handler = &arm920t_handle_cache_info_command,
+		.handler = arm920t_handle_cache_info_command,
 		.mode = COMMAND_EXEC,
 		.help = "display information about target caches",
 	},
 	{
 		.name = "read_cache",
-		.handler = &arm920t_handle_read_cache_command,
+		.handler = arm920t_handle_read_cache_command,
 		.mode = COMMAND_EXEC,
-		.help = "display I/D cache content",
+		.help = "dump I/D cache content to file",
+		.usage = "filename",
 	},
 	{
 		.name = "read_mmu",
-		.handler = &arm920t_handle_read_mmu_command,
+		.handler = arm920t_handle_read_mmu_command,
 		.mode = COMMAND_EXEC,
-		.help = "display I/D mmu content",
+		.help = "dump I/D mmu content to file",
+		.usage = "filename",
 	},
 	COMMAND_REGISTRATION_DONE
 };
@@ -1452,7 +1734,7 @@ struct target_type arm920t_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm920t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm920t_read_memory,
 	.write_memory = arm920t_write_memory,
@@ -1477,4 +1759,5 @@ struct target_type arm920t_target =
 	.target_create = arm920t_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };