X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm920t.c;h=97545c5082bd8cade708f9b0afe7b02e42f7de13;hp=5ade82bc9f3586a6b74fd089f264d9dd39153637;hb=16487e70856a72f9cbe174c7d7d2fb6a1f258100;hpb=e895246966e3aa6e78f9d0816c72c6fbb9160122 diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 5ade82bc9f..97545c5082 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -26,76 +26,43 @@ #include "target_type.h" +/* + * For information about the ARM920T, see ARM DDI 0151C especially + * Chapter 9 about debug support, which shows how to manipulate each + * of the different scan chains: + * + * 0 ... ARM920 signals, e.g. to rest of SOC (unused here) + * 1 ... debugging; watchpoint and breakpoint status, etc; also + * MMU and cache access in conjunction with scan chain 15 + * 2 ... EmbeddedICE + * 3 ... external boundary scan (SoC-specific, unused here) + * 4 ... access to cache tag RAM + * 6 ... ETM9 + * 15 ... access coprocessor 15, "physical" or "interpreted" modes + * "interpreted" works with a few actual MRC/MCR instructions + * "physical" provides register-like behaviors. + * + * The ARM922T is similar, but with smaller caches (8K each, vs 16K). + */ + #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm920t_target_create(struct target_s *target, Jim_Interp *interp); -int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm920t_quit(void); - #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z)) -target_type_t arm920t_target = -{ - .name = "arm920t", - - .poll = arm7_9_poll, - .arch_state = arm920t_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm920t_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm920t_read_memory, - .write_memory = arm920t_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm920t_register_commands, - .target_create = arm920t_target_create, - .init_target = arm920t_init_target, - .examine = arm9tdmi_examine, - .quit = arm920t_quit -}; - -int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) +static int arm920t_read_cp15_physical(target_t *target, + int reg_addr, uint32_t *value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[4]; + struct arm920t_common *arm920t = target_to_arm920(target); + arm_jtag_t *jtag_info; + struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 0; + jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -128,7 +95,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); - #ifdef _DEBUG_INSTRUCTION_EXECUTION_ +#ifdef _DEBUG_INSTRUCTION_EXECUTION_ jtag_execute_queue(); LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value); #endif @@ -136,17 +103,19 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, uint32_t *value) return ERROR_OK; } -int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value) +static int arm920t_write_cp15_physical(target_t *target, + int reg_addr, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[4]; + struct arm920t_common *arm920t = target_to_arm920(target); + arm_jtag_t *jtag_info; + struct scan_field fields[4]; uint8_t access_type_buf = 1; uint8_t reg_addr_buf = reg_addr & 0x3f; uint8_t nr_w_buf = 1; uint8_t value_buf[4]; + jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + buf_set_u32(value_buf, 0, 32, value); jtag_set_end_state(TAP_IDLE); @@ -182,18 +151,20 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, uint32_t value) return ERROR_OK; } -int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_opcode) +static int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, + uint32_t arm_opcode) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - scan_field_t fields[4]; + struct arm920t_common *arm920t = target_to_arm920(target); + arm_jtag_t *jtag_info; + struct scan_field fields[4]; uint8_t access_type_buf = 0; /* interpreted access */ uint8_t reg_addr_buf = 0x0; uint8_t nr_w_buf = 0; uint8_t cp15_opcode_buf[4]; + jtag_info = &arm920t->arm9tdmi_common.arm7_9_common.jtag_info; + jtag_set_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -230,16 +201,17 @@ int arm920t_execute_cp15(target_t *target, uint32_t cp15_opcode, uint32_t arm_op if ((retval = jtag_execute_queue()) != ERROR_OK) { - LOG_ERROR("failed executing JTAG queue, exiting"); + LOG_ERROR("failed executing JTAG queue"); return retval; } return ERROR_OK; } -int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) +static int arm920t_read_cp15_interpreted(target_t *target, + uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; @@ -280,10 +252,12 @@ int arm920t_read_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32 return ERROR_OK; } -int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) +static +int arm920t_write_cp15_interpreted(target_t *target, + uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); uint32_t regs[2]; /* load value, address into R0, R1 */ @@ -318,6 +292,7 @@ int arm920t_write_cp15_interpreted(target_t *target, uint32_t cp15_opcode, uint3 return ERROR_OK; } +// EXPORTED to FA256 uint32_t arm920t_get_ttb(target_t *target) { int retval; @@ -329,6 +304,7 @@ uint32_t arm920t_get_ttb(target_t *target) return ttb; } +// EXPORTED to FA256 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -349,6 +325,7 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ arm920t_write_cp15_physical(target, 0x2, cp15_control); } +// EXPORTED to FA256 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) { uint32_t cp15_control; @@ -369,13 +346,11 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c arm920t_write_cp15_physical(target, 0x2, cp15_control); } +// EXPORTED to FA256 void arm920t_post_debug_entry(target_t *target) { uint32_t cp15c15; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); /* examine cp15 control reg */ arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg); @@ -415,13 +390,11 @@ void arm920t_post_debug_entry(target_t *target) } } +// EXPORTED to FA256 void arm920t_pre_restore_context(target_t *target) { uint32_t cp15c15; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); /* restore i/d fault status and address register */ arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0); @@ -440,62 +413,38 @@ void arm920t_pre_restore_context(target_t *target) } } -int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } - - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } - - arm9tdmi = arm7_9->arch_info; - if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) - { - return -1; - } +static const char arm920_not[] = "target is not an ARM920"; - arm920t = arm9tdmi->arch_info; - if (arm920t->common_magic != ARM920T_COMMON_MAGIC) - { - return -1; +static int arm920t_verify_pointer(struct command_context_s *cmd_ctx, + struct arm920t_common *arm920t) +{ + if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { + command_print(cmd_ctx, arm920_not); + return ERROR_TARGET_INVALID; } - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm9tdmi_p = arm9tdmi; - *arm920t_p = arm920t; - return ERROR_OK; } +/** Logs summary of ARM920 state for a halted target. */ int arm920t_arch_state(struct target_s *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; - - char *state[] = + static const char *state[] = { "disabled", "enabled" }; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) + struct arm920t_common *arm920t = target_to_arm920(target); + struct armv4_5_common_s *armv4_5; + + if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + LOG_ERROR("BUG: %s", arm920_not); + return ERROR_TARGET_INVALID; } + armv4_5 = &arm920t->arm9tdmi_common.arm7_9_common.armv4_5_common; + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s", @@ -511,6 +460,26 @@ int arm920t_arch_state(struct target_s *target) return ERROR_OK; } +static int arm920_mmu(struct target_s *target, int *enabled) +{ + if (target->state != TARGET_HALTED) { + LOG_ERROR("%s: target not halted", __func__); + return ERROR_TARGET_INVALID; + } + + *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled; + return ERROR_OK; +} + +static int arm920_virt2phys(struct target_s *target, + uint32_t virt, uint32_t *phys) +{ + /** @todo Implement this! */ + LOG_ERROR("%s: not implemented", __func__); + return ERROR_FAIL; +} + +/** Reads a buffer, in the specified word size, with current MMU settings. */ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; @@ -520,50 +489,72 @@ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size return retval; } + +static int arm920t_read_phys_memory(struct target_s *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) +{ + struct arm920t_common *arm920t = target_to_arm920(target); + + return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, + address, size, count, buffer); +} + +static int arm920t_write_phys_memory(struct target_s *target, + uint32_t address, uint32_t size, + uint32_t count, uint8_t *buffer) +{ + struct arm920t_common *arm920t = target_to_arm920(target); + + return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, + address, size, count, buffer); +} + + +/** Writes a buffer, in the specified word size, with current MMU settings. */ int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) return retval; + /* This fn is used to write breakpoints, so we need to make sure + * that the data cache is flushed and the instruction cache is + * invalidated + */ if (((size == 4) || (size == 2)) && (count == 1)) { + struct arm920t_common *arm920t = target_to_arm920(target); + if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { - LOG_DEBUG("D-Cache enabled, writing through to main memory"); - uint32_t pa, cb, ap; - int type, domain; - - pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap); - if (type == -1) - return ERROR_OK; - /* cacheable & bufferable means write-back region */ - if (cb == 3) - armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer); + LOG_DEBUG("D-Cache enabled, flush and invalidate cache line"); + /* MCR p15,0,Rd,c7,c10,2 */ + retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address); + if (retval != ERROR_OK) + return retval; } if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) { LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line"); - arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address); + retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address); + if (retval != ERROR_OK) + return retval; } } return retval; } +// EXPORTED to FA256 int arm920t_soft_reset_halt(struct target_s *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm920t_common_t *arm920t = arm9tdmi->arch_info; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) @@ -629,28 +620,15 @@ int arm920t_soft_reset_halt(struct target_s *target) return ERROR_OK; } -int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) -{ - arm9tdmi_init_target(cmd_ctx, target); - - return ERROR_OK; -} - -int arm920t_quit(void) -{ - return ERROR_OK; -} - -int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap) +int arm920t_init_arch_info(target_t *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm9tdmi->arm7_9_common; /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) */ arm9tdmi_init_arch_info(target, arm9tdmi, tap); - arm9tdmi->arch_info = arm920t; arm920t->common_magic = ARM920T_COMMON_MAGIC; arm7_9->post_debug_entry = arm920t_post_debug_entry; @@ -677,52 +655,20 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap return ERROR_OK; } -int arm920t_target_create(struct target_s *target, Jim_Interp *interp) +static int arm920t_target_create(struct target_s *target, Jim_Interp *interp) { - arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t)); + struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common)); - arm920t_init_arch_info(target, arm920t, target->tap); - - return ERROR_OK; + return arm920t_init_arch_info(target, arm920t, target->tap); } -int arm920t_register_commands(struct command_context_s *cmd_ctx) -{ - int retval; - command_t *arm920t_cmd; - - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands"); - - register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) [value] [address]"); - register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); - - register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words [count]"); - register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words [count]"); - register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes [count]"); - - register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word "); - register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word "); - register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte "); - - register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content"); - register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content"); - - return retval; -} - -int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_read_cache_command) { int retval = ERROR_OK; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -730,9 +676,13 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c uint32_t C15_C_D_Ind, C15_C_I_Ind; int i; FILE *output; - arm920t_cache_line_t d_cache[8][64], i_cache[8][64]; + struct arm920t_cache_line d_cache[8][64], i_cache[8][64]; int segment, index; + retval = arm920t_verify_pointer(cmd_ctx, arm920t); + if (retval != ERROR_OK) + return retval; + if (argc != 1) { command_print(cmd_ctx, "usage: arm920t read_cache "); @@ -748,14 +698,6 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c for (i = 0; i < 16; i++) regs_p[i] = ®s[i]; - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -966,15 +908,13 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } -int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_read_mmu_command) { int retval = ERROR_OK; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; + struct arm920t_common *arm920t = target_to_arm920(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -982,9 +922,13 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd int i; FILE *output; uint32_t Dlockdown, Ilockdown; - arm920t_tlb_entry_t d_tlb[64], i_tlb[64]; + struct arm920t_tlb_entry d_tlb[64], i_tlb[64]; int victim; + retval = arm920t_verify_pointer(cmd_ctx, arm920t); + if (retval != ERROR_OK) + return retval; + if (argc != 1) { command_print(cmd_ctx, "usage: arm920t read_mmu "); @@ -1000,14 +944,6 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd for (i = 0; i < 16; i++) regs_p[i] = ®s[i]; - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } - - jtag_info = &arm7_9->jtag_info; - /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1254,34 +1190,28 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd return ERROR_OK; } -int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) + +COMMAND_HANDLER(arm920t_handle_cp15_command) { int retval; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; - - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } + struct arm920t_common *arm920t = target_to_arm920(target); - jtag_info = &arm7_9->jtag_info; + retval = arm920t_verify_pointer(cmd_ctx, arm920t); + if (retval != ERROR_OK) + return retval; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ if (argc >= 1) { - int address = strtoul(args[0], NULL, 0); + int address; + COMMAND_PARSE_NUMBER(int, args[0], address); if (argc == 1) { @@ -1300,7 +1230,8 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch } else if (argc == 2) { - uint32_t value = strtoul(args[1], NULL, 0); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, args[1], value); if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK) { command_print(cmd_ctx, "couldn't access reg %i", address); @@ -1313,34 +1244,28 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch return ERROR_OK; } -int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_cp15i_command) { int retval; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; + struct arm920t_common *arm920t = target_to_arm920(target); - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } + retval = arm920t_verify_pointer(cmd_ctx, arm920t); + if (retval != ERROR_OK) + return retval; - jtag_info = &arm7_9->jtag_info; if (target->state != TARGET_HALTED) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); + command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); return ERROR_OK; } /* one or more argument, access a single register (write if second argument is given */ if (argc >= 1) { - uint32_t opcode = strtoul(args[0], NULL, 0); + uint32_t opcode; + COMMAND_PARSE_NUMBER(u32, args[0], opcode); if (argc == 1) { @@ -1355,7 +1280,8 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c } else if (argc == 2) { - uint32_t value = strtoul(args[1], NULL, 0); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, args[1], value); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK) { command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); @@ -1365,8 +1291,10 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c } else if (argc == 3) { - uint32_t value = strtoul(args[1], NULL, 0); - uint32_t address = strtoul(args[2], NULL, 0); + uint32_t value; + COMMAND_PARSE_NUMBER(u32, args[1], value); + uint32_t address; + COMMAND_PARSE_NUMBER(u32, args[2], address); if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK) { command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode); @@ -1383,71 +1311,116 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c return ERROR_OK; } -int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(arm920t_handle_cache_info_command) { + int retval; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; + struct arm920t_common *arm920t = target_to_arm920(target); - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } + retval = arm920t_verify_pointer(cmd_ctx, arm920t); + if (retval != ERROR_OK) + return retval; return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); } -int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) +static int arm920t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +{ + if (cpnum!=15) { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; } - jtag_info = &arm7_9->jtag_info; + return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); +} - if (target->state != TARGET_HALTED) +static int arm920t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +{ + if (cpnum!=15) { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; } - return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); + return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value); } -int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) +/** Registers commands to access coprocessor, cache, and MMU resources. */ +int arm920t_register_commands(struct command_context_s *cmd_ctx) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm920t_common_t *arm920t; - arm_jtag_t *jtag_info; - - if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM920t target"); - return ERROR_OK; - } + int retval; + command_t *arm920t_cmd; - jtag_info = &arm7_9->jtag_info; + retval = arm9tdmi_register_commands(cmd_ctx); - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", + NULL, COMMAND_ANY, + "arm920t specific commands"); + + register_command(cmd_ctx, arm920t_cmd, "cp15", + arm920t_handle_cp15_command, COMMAND_EXEC, + "display/modify cp15 register [value]"); + register_command(cmd_ctx, arm920t_cmd, "cp15i", + arm920t_handle_cp15i_command, COMMAND_EXEC, + "display/modify cp15 (interpreted access) " + " [value] [address]"); + register_command(cmd_ctx, arm920t_cmd, "cache_info", + arm920t_handle_cache_info_command, COMMAND_EXEC, + "display information about target caches"); + register_command(cmd_ctx, arm920t_cmd, "read_cache", + arm920t_handle_read_cache_command, COMMAND_EXEC, + "display I/D cache content"); + register_command(cmd_ctx, arm920t_cmd, "read_mmu", + arm920t_handle_read_mmu_command, COMMAND_EXEC, + "display I/D mmu content"); - return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); + return retval; } + +/** Holds methods for ARM920 targets. */ +target_type_t arm920t_target = +{ + .name = "arm920t", + + .poll = arm7_9_poll, + .arch_state = arm920t_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm920t_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm920t_read_memory, + .write_memory = arm920t_write_memory, + .read_phys_memory = arm920t_read_phys_memory, + .write_phys_memory = arm920t_write_phys_memory, + .mmu = arm920_mmu, + .virt2phys = arm920_virt2phys, + + .bulk_write_memory = arm7_9_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm920t_register_commands, + .target_create = arm920t_target_create, + .init_target = arm9tdmi_init_target, + .examine = arm9tdmi_examine, + .mrc = arm920t_mrc, + .mcr = arm920t_mcr, +};