X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=3f22a8a46ad7eac8ad4f73966de57fc8dc519229;hp=7c226585a732478377a93aea036774732bb19720;hb=bc1f5cabc046d36696f5e3b55319e4e1b7a385f9;hpb=86173cdbddde781b19ac630602f2d450a59b32b5 diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 7c226585a7..3f22a8a46a 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -2,6 +2,9 @@ * Copyright (C) 2007 by Dominic Rath * * Dominic.Rath@gmx.de * * * + * Copyright (C) 2007,2008,2009 by Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -13,259 +16,226 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include "arm926ejs.h" -#include "time_support.h" +#include #include "target_type.h" - +#include "register.h" +#include "arm_opcodes.h" + + +/* + * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs + * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not + * the ARM926 manual (ARM DDI 0198E). The scan chains are: + * + * 1 ... core debugging + * 2 ... EmbeddedICE + * 3 ... external boundary scan (SoC-specific, unused here) + * 6 ... ETM + * 15 ... coprocessor 15 + */ #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp); -int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target); -int arm926ejs_quit(void); -int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer); - -static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical); -static int arm926ejs_mmu(struct target_s *target, int *enabled); - -target_type_t arm926ejs_target = -{ - .name = "arm926ejs", - - .poll = arm7_9_poll, - .arch_state = arm926ejs_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm926ejs_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm926ejs_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm926ejs_register_commands, - .target_create = arm926ejs_target_create, - .init_target = arm926ejs_init_target, - .examine = arm9tdmi_examine, - .quit = arm926ejs_quit, - .virt2phys = arm926ejs_virt2phys, - .mmu = arm926ejs_mmu -}; - -int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field) -{ - /* FIX!!!! this code should be reenabled. For now it does not check - * the queue...*/ - return 0; -#if 0 - /* The ARM926EJ-S' instruction register is 4 bits wide */ - uint8_t t = *captured & 0xf; - uint8_t t2 = *field->in_check_value & 0xf; - if (t == t2) - { - return ERROR_OK; - } - else if ((t == 0x0f) || (t == 0x00)) - { - LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access"); - return ERROR_OK; - } - return ERROR_JTAG_QUEUE_FAILED;; -#endif -} - #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) -int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value) +static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t *value) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); - scan_field_t fields[4]; - uint8_t address_buf[2]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); + struct scan_field fields[4]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 0; - uint8_t access = 1; + uint8_t access_t = 1; buf_set_u32(address_buf, 0, 14, address); - jtag_set_end_state(TAP_IDLE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = (uint8_t *)value; - - fields[1].tap = jtag_info->tap; fields[1].num_bits = 1; - fields[1].out_value = &access; - fields[1].in_value = &access; + fields[1].out_value = &access_t; + fields[1].in_value = &access_t; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 14; fields[2].out_value = address_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); - /*TODO: add timeout*/ - do - { + int64_t then = timeval_ms(); + + for (;;) { /* rescan with NOP, to wait for the access to complete */ - access = 0; + access_t = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); - jtag_add_callback(arm_le_to_h_u32, (uint8_t *)value); + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; + + if (buf_get_u32(&access_t, 0, 1) == 1) + break; + + /* 10ms timeout */ + if ((timeval_ms()-then) > 10) { + LOG_ERROR("cp15 read operation timed out"); + return ERROR_FAIL; } - } while (buf_get_u32(&access, 0, 1) != 1); + } #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value); #endif - arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan); + retval = arm_jtag_set_instr(jtag_info->tap, 0xc, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } -int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value) +static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) +{ + if (cpnum != 15) { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value); +} + +static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2, + uint32_t CRn, uint32_t CRm, uint32_t value) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); - scan_field_t fields[4]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); + struct scan_field fields[4]; uint8_t value_buf[4]; - uint8_t address_buf[2]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 1; - uint8_t access = 1; + uint8_t access_t = 1; buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - jtag_set_end_state(TAP_IDLE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) - { + retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE); + if (retval != ERROR_OK) + return retval; + retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) return retval; - } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = value_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 1; - fields[1].out_value = &access; - fields[1].in_value = &access; + fields[1].out_value = &access_t; + fields[1].in_value = &access_t; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 14; fields[2].out_value = address_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); - /*TODO: add timeout*/ - do - { + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); + + int64_t then = timeval_ms(); + + for (;;) { /* rescan with NOP, to wait for the access to complete */ - access = 0; + access_t = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; + + if (buf_get_u32(&access_t, 0, 1) == 1) + break; + + /* 10ms timeout */ + if ((timeval_ms()-then) > 10) { + LOG_ERROR("cp15 write operation timed out"); + return ERROR_FAIL; } - } while (buf_get_u32(&access, 0, 1) != 1); + } #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", address, value); #endif - arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan); + retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } -int arm926ejs_examine_debug_reason(target_t *target) +static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1, + uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) +{ + if (cpnum != 15) { + LOG_ERROR("Only cp15 is supported"); + return ERROR_FAIL; + } + return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value); +} + +static int arm926ejs_examine_debug_reason(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; int debug_reason; int retval; embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; + /* Method-Of-Entry (MOE) field */ debug_reason = buf_get_u32(dbg_stat->value, 6, 4); - switch (debug_reason) - { + switch (debug_reason) { + case 0: + LOG_DEBUG("no *NEW* debug entry (?missed one?)"); + /* ... since last restart or debug reset ... */ + target->debug_reason = DBG_REASON_DBGRQ; + break; case 1: LOG_DEBUG("breakpoint from EICE unit 0"); target->debug_reason = DBG_REASON_BREAKPOINT; @@ -307,7 +277,21 @@ int arm926ejs_examine_debug_reason(target_t *target) target->debug_reason = DBG_REASON_DBGRQ; break; case 11: - LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here"); + LOG_DEBUG("debug re-entry from system speed access"); + /* This is normal when connecting to something that's + * already halted, or in some related code paths, but + * otherwise is surprising (and presumably wrong). + */ + switch (target->debug_reason) { + case DBG_REASON_DBGRQ: + break; + default: + LOG_ERROR("unexpected -- debug re-entry"); + /* FALLTHROUGH */ + case DBG_REASON_UNDEFINED: + target->debug_reason = DBG_REASON_DBGRQ; + break; + } break; case 12: /* FIX!!!! here be dragons!!! We need to fail here so @@ -317,99 +301,116 @@ int arm926ejs_examine_debug_reason(target_t *target) * openocd development mailing list if you have hardware * to donate to look into this problem.... */ - LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt."); + LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt."); target->debug_reason = DBG_REASON_DBGRQ; - retval = ERROR_TARGET_FAILURE; break; default: - LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason); + LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); + /* Oh agony! should we interpret this as a halt request or + * that the target stopped on it's own accord? + */ target->debug_reason = DBG_REASON_DBGRQ; /* if we fail here, we won't talk to the target and it will * be reported to be in the halted state */ - retval = ERROR_TARGET_FAILURE; break; } - return retval; + return ERROR_OK; } -u32 arm926ejs_get_ttb(target_t *target) +static int arm926ejs_get_ttb(struct target *target, uint32_t *result) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); int retval; - u32 ttb = 0x0; + uint32_t ttb = 0x0; - if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK) + retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb); + if (retval != ERROR_OK) return retval; - return ttb; + *result = ttb; + + return ERROR_OK; } -void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static int arm926ejs_disable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - u32 cp15_control; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; - if (mmu) - { + if (mmu) { /* invalidate TLB */ - arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); + retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); + if (retval != ERROR_OK) + return retval; cp15_control &= ~0x1U; } - if (d_u_cache) - { - u32 debug_override; + if (d_u_cache) { + uint32_t debug_override; /* read-modify-write CP15 debug override register * to enable "test and clean all" */ - arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); + retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); + if (retval != ERROR_OK) + return retval; debug_override |= 0x80000; - arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + if (retval != ERROR_OK) + return retval; /* clean and invalidate DCache */ - arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + if (retval != ERROR_OK) + return retval; /* write CP15 debug override register * to disable "test and clean all" */ debug_override &= ~0x80000; - arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + if (retval != ERROR_OK) + return retval; cp15_control &= ~0x4U; } - if (i_cache) - { + if (i_cache) { /* invalidate ICache */ - arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + if (retval != ERROR_OK) + return retval; cp15_control &= ~0x1000U; } - arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + return retval; } -void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache) +static int arm926ejs_enable_mmu_caches(struct target *target, int mmu, + int d_u_cache, int i_cache) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - u32 cp15_control; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control |= 0x1U; @@ -420,27 +421,33 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i if (i_cache) cp15_control |= 0x1000U; - arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + return retval; } -void arm926ejs_post_debug_entry(target_t *target) +static int arm926ejs_post_debug_entry(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + int retval; /* examine cp15 control reg */ - arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); - jtag_execute_queue(); - LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg); + retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; + LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg); - if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) - { - u32 cache_type_reg; + if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) { + uint32_t cache_type_reg; /* identify caches */ - arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache); } @@ -449,35 +456,41 @@ void arm926ejs_post_debug_entry(target_t *target) arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0; /* save i/d fault status and address register */ - arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); - arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); - arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); + retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); + if (retval != ERROR_OK) + return retval; + retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); + if (retval != ERROR_OK) + return retval; + retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); + if (retval != ERROR_OK) + return retval; - LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", + LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "", arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); - u32 cache_dbg_ctrl; + uint32_t cache_dbg_ctrl; /* read-modify-write CP15 cache debug control register * to disable I/D-cache linefills and force WT */ - arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); + retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); + if (retval != ERROR_OK) + return retval; cache_dbg_ctrl |= 0x7; - arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); + retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); + return retval; } -void arm926ejs_pre_restore_context(target_t *target) +static void arm926ejs_pre_restore_context(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); /* restore i/d fault status and address register */ arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr); arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr); arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far); - u32 cache_dbg_ctrl; + uint32_t cache_dbg_ctrl; /* read-modify-write CP15 cache debug control register * to reenable I/D-cache linefills and disable WT */ @@ -486,71 +499,34 @@ void arm926ejs_pre_restore_context(target_t *target) arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); } -int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } +static const char arm926_not[] = "target is not an ARM926"; - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } - - arm9tdmi = arm7_9->arch_info; - if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) - { - return -1; - } - - arm926ejs = arm9tdmi->arch_info; - if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) - { - return -1; +static int arm926ejs_verify_pointer(struct command_context *cmd_ctx, + struct arm926ejs_common *arm926) +{ + if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) { + command_print(cmd_ctx, arm926_not); + return ERROR_TARGET_INVALID; } - - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm9tdmi_p = arm9tdmi; - *arm926ejs_p = arm926ejs; - return ERROR_OK; } -int arm926ejs_arch_state(struct target_s *target) +/** Logs summary of ARM926 state for a halted target. */ +int arm926ejs_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - - char *state[] = - { + static const char *state[] = { "disabled", "enabled" }; - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - LOG_ERROR("BUG: called for a non-ARMv4/5 target"); - exit(-1); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + + if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) { + LOG_ERROR("BUG: %s", arm926_not); + return ERROR_TARGET_INVALID; } - LOG_USER( - "target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8x pc: 0x%8.8x\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[arm926ejs->armv4_5_mmu.mmu_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); @@ -558,46 +534,35 @@ int arm926ejs_arch_state(struct target_s *target) return ERROR_OK; } -int arm926ejs_soft_reset_halt(struct target_s *target) +int arm926ejs_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *arm = &arm7_9->arm; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - if ((retval = target_halt(target)) != ERROR_OK) - { + retval = target_halt(target); + if (retval != ERROR_OK) return retval; - } - long long then=timeval_ms(); + int64_t then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) - { - if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) - { + while (!(timeout = ((timeval_ms()-then) > 1000))) { + if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { embeddedice_read_reg(dbg_stat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - { + retval = jtag_execute_queue(); + if (retval != ERROR_OK) return retval; - } - } else - { + } else break; - } - if (debug_level>=1) - { + if (debug_level >= 1) { /* do not eat all CPU, time out after 1 se*/ alive_sleep(100); } else - { keep_alive(); - } } - if (timeout) - { + if (timeout) { LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } @@ -605,19 +570,22 @@ int arm926ejs_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; - /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = true; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; + /* start fetching from 0x0 */ + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = true; + arm->pc->valid = true; - arm926ejs_disable_mmu_caches(target, 1, 1, 1); + retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1); + if (retval != ERROR_OK) + return retval; arm926ejs->armv4_5_mmu.mmu_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; @@ -625,29 +593,59 @@ int arm926ejs_soft_reset_halt(struct target_s *target) return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } -int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, uint8_t *buffer) +/** Writes a buffer, in the specified word size, with current MMU settings. */ +int arm926ejs_write_memory(struct target *target, target_addr_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; - arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + + /* FIX!!!! this should be cleaned up and made much more general. The + * plan is to write up and test on arm926ejs specifically and + * then generalize and clean up afterwards. + * + * + * Also it should be moved to the callbacks that handle breakpoints + * specifically and not the generic memory write fn's. See XScale code. + **/ + if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size == 2) || (size == 4))) { + /* special case the handling of single word writes to bypass MMU + * to allow implementation of breakpoints in memory marked read only + * by MMU */ + if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) { + /* flush and invalidate data cache + * + * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address + * + */ + retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3); + if (retval != ERROR_OK) + return retval; + } - if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) - return retval; + target_addr_t pa; + retval = target->type->virt2phys(target, address, &pa); + if (retval != ERROR_OK) + return retval; + + /* write directly to physical memory bypassing any read only MMU bits, etc. */ + retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer); + if (retval != ERROR_OK) + return retval; + } else { + retval = arm7_9_write_memory(target, address, size, count, buffer); + if (retval != ERROR_OK) + return retval; + } /* If ICache is enabled, we have to invalidate affected ICache lines * the DCache is forced to write-through, so we don't have to clean it here */ - if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) - { - if (count <= 1) - { + if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) { + if (count <= 1) { /* invalidate ICache single entry with MVA */ arm926ejs->write_cp15(target, 0, 1, 7, 5, address); - } - else - { + } else { /* invalidate ICache */ arm926ejs->write_cp15(target, 0, 0, 7, 5, address); } @@ -656,32 +654,42 @@ int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 c return retval; } -int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +static int arm926ejs_write_phys_memory(struct target *target, + target_addr_t address, uint32_t size, + uint32_t count, const uint8_t *buffer) { - arm9tdmi_init_target(cmd_ctx, target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - return ERROR_OK; + return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, + address, size, count, buffer); } -int arm926ejs_quit(void) +static int arm926ejs_read_phys_memory(struct target *target, + target_addr_t address, uint32_t size, + uint32_t count, uint8_t *buffer) { - return ERROR_OK; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + + return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, + address, size, count, buffer); } -int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap) +int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, + struct jtag_tap *tap) { - arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common; - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); + arm7_9->arm.mrc = arm926ejs_mrc; + arm7_9->arm.mcr = arm926ejs_mcr; + + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); - arm9tdmi->arch_info = arm926ejs; arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; arm7_9->post_debug_entry = arm926ejs_post_debug_entry; arm7_9->pre_restore_context = arm926ejs_pre_restore_context; + arm7_9->write_memory = arm926ejs_write_memory; arm926ejs->read_cp15 = arm926ejs_cp15_read; arm926ejs->write_cp15 = arm926ejs_cp15_write; @@ -705,237 +713,121 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jt return ERROR_OK; } -int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp) +static int arm926ejs_target_create(struct target *target, Jim_Interp *interp) { - arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); + struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common)); - arm926ejs_init_arch_info(target, arm926ejs, target->tap); + /* ARM9EJ-S core always reports 0x1 in Capture-IR */ + target->tap->ir_capture_mask = 0x0f; - return ERROR_OK; + return arm926ejs_init_arch_info(target, arm926ejs, target->tap); } -int arm926ejs_register_commands(struct command_context_s *cmd_ctx) +COMMAND_HANDLER(arm926ejs_handle_cache_info_command) { int retval; - command_t *arm926ejs_cmd; + struct target *target = get_current_target(CMD_CTX); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs); + if (retval != ERROR_OK) + return retval; - retval = arm9tdmi_register_commands(cmd_ctx); - - arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands"); - - register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - - register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches"); - register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa "); - - register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words [count]"); - register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words [count]"); - register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes [count]"); - - register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word "); - register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word "); - register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte "); - - return retval; + return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache); } -int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm926ejs_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical) { - int retval; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - int opcode_1; - int opcode_2; - int CRn; - int CRm; - - if ((argc < 4) || (argc > 5)) - { - command_print(cmd_ctx, "usage: arm926ejs cp15 [value]"); - return ERROR_OK; - } - - opcode_1 = strtoul(args[0], NULL, 0); - opcode_2 = strtoul(args[1], NULL, 0); - CRn = strtoul(args[2], NULL, 0); - CRm = strtoul(args[3], NULL, 0); - - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; - } - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } - - if (argc == 4) - { - u32 value; - if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } - - command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); - } - else - { - u32 value = strtoul(args[4], NULL, 0); - if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); - } + uint32_t cb; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, + virtual, &cb, &ret); + if (retval != ERROR_OK) + return retval; + *physical = ret; return ERROR_OK; } -int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int arm926ejs_mmu(struct target *target, int *enabled) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_INVALID; } - - return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); + *enabled = arm926ejs->armv4_5_mmu.mmu_enabled; + return ERROR_OK; } -int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - arm_jtag_t *jtag_info; - - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) +static const struct command_registration arm926ejs_exec_command_handlers[] = { { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; - } + .name = "cache_info", + .handler = arm926ejs_handle_cache_info_command, + .mode = COMMAND_EXEC, + .usage = "", + .help = "display information about target caches", - jtag_info = &arm7_9->jtag_info; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm926ejs_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm926ejs", + .mode = COMMAND_ANY, + .help = "arm926ejs command group", + .usage = "", + .chain = arm926ejs_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; - return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); -} +/** Holds methods for ARM926 targets. */ +struct target_type arm926ejs_target = { + .name = "arm926ejs", -int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - arm_jtag_t *jtag_info; - - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; - } + .poll = arm7_9_poll, + .arch_state = arm926ejs_arch_state, - jtag_info = &arm7_9->jtag_info; + .target_request_data = arm7_9_target_request_data, - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, - return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); -} + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm926ejs_soft_reset_halt, -int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - arm_jtag_t *jtag_info; - - if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM926EJ-S target"); - return ERROR_OK; - } + .get_gdb_arch = arm_get_gdb_arch, + .get_gdb_reg_list = arm_get_gdb_reg_list, - jtag_info = &arm7_9->jtag_info; + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory_opt, - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); - return ERROR_OK; - } + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, - return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); -} + .run_algorithm = armv4_5_run_algorithm, -static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical) -{ - int retval; - int type; - u32 cb; - int domain; - u32 ap; - - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - arm926ejs_common_t *arm926ejs; - retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs); - if (retval != ERROR_OK) - { - return retval; - } - u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); - if (type == -1) - { - return ret; - } - *physical = ret; - return ERROR_OK; -} + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, -static int arm926ejs_mmu(struct target_s *target, int *enabled) -{ - armv4_5_common_t *armv4_5 = target->arch_info; - arm926ejs_common_t *arm926ejs = armv4_5->arch_info; + .commands = arm926ejs_command_handlers, + .target_create = arm926ejs_target_create, + .init_target = arm9tdmi_init_target, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, + .virt2phys = arm926ejs_virt2phys, + .mmu = arm926ejs_mmu, - if (target->state != TARGET_HALTED) - { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_INVALID; - } - *enabled = arm926ejs->armv4_5_mmu.mmu_enabled; - return ERROR_OK; -} + .read_phys_memory = arm926ejs_read_phys_memory, + .write_phys_memory = arm926ejs_write_phys_memory, +};