X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=3f22a8a46ad7eac8ad4f73966de57fc8dc519229;hp=d882050f8f78484d898a187acca0e464e1b628c6;hb=bc1f5cabc046d36696f5e3b55319e4e1b7a385f9;hpb=a4a2808c2a849eddd5d7d454c048ffdfd89ca9c6

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d882050f8f..3f22a8a46a 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -16,10 +16,9 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -59,64 +58,54 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	struct scan_field fields[4];
 	uint8_t address_buf[2] = {0, 0};
 	uint8_t nr_w_buf = 0;
-	uint8_t access = 1;
+	uint8_t access_t = 1;
 
 	buf_set_u32(address_buf, 0, 14, address);
 
-	jtag_set_end_state(TAP_IDLE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
-	{
+	retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
 		return retval;
-	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
 	fields[0].in_value = (uint8_t *)value;
 
-
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
-	fields[1].out_value = &access;
-	fields[1].in_value = &access;
+	fields[1].out_value = &access_t;
+	fields[1].in_value = &access_t;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
-	long long then = timeval_ms();
+	int64_t then = timeval_ms();
 
-	for (;;)
-	{
+	for (;;) {
 		/* rescan with NOP, to wait for the access to complete */
-		access = 0;
+		access_t = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
-		if ((retval = jtag_execute_queue()) != ERROR_OK)
-		{
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
 			return retval;
-		}
 
-		if (buf_get_u32(&access, 0, 1) == 1)
-		{
+		if (buf_get_u32(&access_t, 0, 1) == 1)
 			break;
-		}
 
 		/* 10ms timeout */
-		if ((timeval_ms()-then)>10)
-		{
+		if ((timeval_ms()-then) > 10) {
 			LOG_ERROR("cp15 read operation timed out");
 			return ERROR_FAIL;
 		}
@@ -126,7 +115,9 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-	arm_jtag_set_instr(jtag_info, 0xc, NULL);
+	retval = arm_jtag_set_instr(jtag_info->tap, 0xc, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	return ERROR_OK;
 }
@@ -152,61 +143,52 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	uint8_t value_buf[4];
 	uint8_t address_buf[2] = {0, 0};
 	uint8_t nr_w_buf = 1;
-	uint8_t access = 1;
+	uint8_t access_t = 1;
 
 	buf_set_u32(address_buf, 0, 14, address);
 	buf_set_u32(value_buf, 0, 32, value);
 
-	jtag_set_end_state(TAP_IDLE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
-	{
+	retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
 		return retval;
-	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 
-	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 1;
-	fields[1].out_value = &access;
-	fields[1].in_value = &access;
+	fields[1].out_value = &access_t;
+	fields[1].in_value = &access_t;
 
-	fields[2].tap = jtag_info->tap;
 	fields[2].num_bits = 14;
 	fields[2].out_value = address_buf;
 	fields[2].in_value = NULL;
 
-	fields[3].tap = jtag_info->tap;
 	fields[3].num_bits = 1;
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
-	long long then = timeval_ms();
+	int64_t then = timeval_ms();
 
-	for (;;)
-	{
+	for (;;) {
 		/* rescan with NOP, to wait for the access to complete */
-		access = 0;
+		access_t = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(4, fields, jtag_get_end_state());
-		if ((retval = jtag_execute_queue()) != ERROR_OK)
-		{
+		jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
 			return retval;
-		}
 
-		if (buf_get_u32(&access, 0, 1) == 1)
-		{
+		if (buf_get_u32(&access_t, 0, 1) == 1)
 			break;
-		}
 
 		/* 10ms timeout */
-		if ((timeval_ms()-then)>10)
-		{
+		if ((timeval_ms()-then) > 10) {
 			LOG_ERROR("cp15 write operation timed out");
 			return ERROR_FAIL;
 		}
@@ -216,7 +198,9 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-	arm_jtag_set_instr(jtag_info, 0xf, NULL);
+	retval = arm_jtag_set_instr(jtag_info->tap, 0xf, NULL, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
 
 	return ERROR_OK;
 }
@@ -239,14 +223,14 @@ static int arm926ejs_examine_debug_reason(struct target *target)
 	int retval;
 
 	embeddedice_read_reg(dbg_stat);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
 		return retval;
 
 	/* Method-Of-Entry (MOE) field */
 	debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 
-	switch (debug_reason)
-	{
+	switch (debug_reason) {
 		case 0:
 			LOG_DEBUG("no *NEW* debug entry (?missed one?)");
 			/* ... since last restart or debug reset ... */
@@ -334,76 +318,99 @@ static int arm926ejs_examine_debug_reason(struct target *target)
 	return ERROR_OK;
 }
 
-static uint32_t arm926ejs_get_ttb(struct target *target)
+static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	int retval;
 	uint32_t ttb = 0x0;
 
-	if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
+	retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb);
+	if (retval != ERROR_OK)
 		return retval;
 
-	return ttb;
+	*result = ttb;
+
+	return ERROR_OK;
 }
 
-static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-	jtag_execute_queue();
+	retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
-	if (mmu)
-	{
+	if (mmu) {
 		/* invalidate TLB */
-		arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+		retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x1U;
 	}
 
-	if (d_u_cache)
-	{
+	if (d_u_cache) {
 		uint32_t debug_override;
 		/* read-modify-write CP15 debug override register
 		 * to enable "test and clean all" */
-		arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+		retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
+		if (retval != ERROR_OK)
+			return retval;
 		debug_override |= 0x80000;
-		arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* clean and invalidate DCache */
-		arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		/* write CP15 debug override register
 		 * to disable "test and clean all" */
 		debug_override &= ~0x80000;
-		arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
+		if (retval != ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x4U;
 	}
 
-	if (i_cache)
-	{
+	if (i_cache) {
 		/* invalidate ICache */
-		arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
+		if (retval != ERROR_OK)
+			return retval;
 
 		cp15_control &= ~0x1000U;
 	}
 
-	arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	return retval;
 }
 
-static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
+static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
 		int d_u_cache, int i_cache)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	uint32_t cp15_control;
+	int retval;
 
 	/* read cp15 control register */
-	arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
-	jtag_execute_queue();
+	retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (mmu)
 		cp15_control |= 0x1U;
@@ -414,24 +421,33 @@ static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
 	if (i_cache)
 		cp15_control |= 0x1000U;
 
-	arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
+	return retval;
 }
 
-static void arm926ejs_post_debug_entry(struct target *target)
+static int arm926ejs_post_debug_entry(struct target *target)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+	int retval;
 
 	/* examine cp15 control reg */
-	arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
-	jtag_execute_queue();
+	retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
-	if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
-	{
+	if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) {
 		uint32_t cache_type_reg;
 		/* identify caches */
-		arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
-		jtag_execute_queue();
+		retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = jtag_execute_queue();
+		if (retval != ERROR_OK)
+			return retval;
 		armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 	}
 
@@ -440,9 +456,15 @@ static void arm926ejs_post_debug_entry(struct target *target)
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
 	/* save i/d fault status and address register */
-	arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
-	arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
-	arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+	retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
+	if (retval != ERROR_OK)
+		return retval;
 
 	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -451,9 +473,12 @@ static void arm926ejs_post_debug_entry(struct target *target)
 
 	/* read-modify-write CP15 cache debug control register
 	 * to disable I/D-cache linefills and force WT */
-	arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+	retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
+	if (retval != ERROR_OK)
+		return retval;
 	cache_dbg_ctrl |= 0x7;
-	arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+	retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
+	return retval;
 }
 
 static void arm926ejs_pre_restore_context(struct target *target)
@@ -489,30 +514,19 @@ static int arm926ejs_verify_pointer(struct command_context *cmd_ctx,
 /** Logs summary of ARM926 state for a halted target. */
 int arm926ejs_arch_state(struct target *target)
 {
-	static const char *state[] =
-	{
+	static const char *state[] = {
 		"disabled", "enabled"
 	};
 
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
-	struct arm *armv4_5;
 
-	if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
-	{
+	if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) {
 		LOG_ERROR("BUG: %s", arm926_not);
 		return ERROR_TARGET_INVALID;
 	}
 
-	armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
-
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm926ejs->armv4_5_mmu.mmu_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
@@ -525,40 +539,30 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	int retval = ERROR_OK;
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
-	struct arm *armv4_5 = &arm7_9->armv4_5_common;
+	struct arm *arm = &arm7_9->arm;
 	struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
-	if ((retval = target_halt(target)) != ERROR_OK)
-	{
+	retval = target_halt(target);
+	if (retval != ERROR_OK)
 		return retval;
-	}
 
-	long long then = timeval_ms();
+	int64_t then = timeval_ms();
 	int timeout;
-	while (!(timeout = ((timeval_ms()-then) > 1000)))
-	{
-		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
-		{
+	while (!(timeout = ((timeval_ms()-then) > 1000))) {
+		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
 			embeddedice_read_reg(dbg_stat);
-			if ((retval = jtag_execute_queue()) != ERROR_OK)
-			{
+			retval = jtag_execute_queue();
+			if (retval != ERROR_OK)
 				return retval;
-			}
-		}  else
-		{
+		} else
 			break;
-		}
-		if (debug_level >= 1)
-		{
+		if (debug_level >= 1) {
 			/* do not eat all CPU, time out after 1 se*/
 			alive_sleep(100);
 		} else
-		{
 			keep_alive();
-		}
 	}
-	if (timeout)
-	{
+	if (timeout) {
 		LOG_ERROR("Failed to halt CPU after 1 sec");
 		return ERROR_TARGET_TIMEOUT;
 	}
@@ -568,18 +572,20 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	/* SVC, ARM state, IRQ and FIQ disabled */
 	uint32_t cpsr;
 
-	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
+	cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
 	cpsr &= ~0xff;
 	cpsr |= 0xd3;
-	arm_set_cpsr(armv4_5, cpsr);
-	armv4_5->cpsr->dirty = 1;
+	arm_set_cpsr(arm, cpsr);
+	arm->cpsr->dirty = true;
 
 	/* start fetching from 0x0 */
-	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-	armv4_5->core_cache->reg_list[15].valid = 1;
+	buf_set_u32(arm->pc->value, 0, 32, 0x0);
+	arm->pc->dirty = true;
+	arm->pc->valid = true;
 
-	arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+	retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
+	if (retval != ERROR_OK)
+		return retval;
 	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
@@ -588,22 +594,25 @@ int arm926ejs_soft_reset_halt(struct target *target)
 }
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm926ejs_write_memory(struct target *target, uint32_t address,
-		uint32_t size, uint32_t count, uint8_t *buffer)
+int arm926ejs_write_memory(struct target *target, target_addr_t address,
+		uint32_t size, uint32_t count, const uint8_t *buffer)
 {
 	int retval;
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
 	/* FIX!!!! this should be cleaned up and made much more general. The
 	 * plan is to write up and test on arm926ejs specifically and
-	 * then generalize and clean up afterwards. */
-	if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
-	{
+	 * then generalize and clean up afterwards.
+	 *
+	 *
+	 * Also it should be moved to the callbacks that handle breakpoints
+	 * specifically and not the generic memory write fn's. See XScale code.
+	 **/
+	if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size == 2) || (size == 4))) {
 		/* special case the handling of single word writes to bypass MMU
 		 * to allow implementation of breakpoints in memory marked read only
 		 * by MMU */
-		if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-		{
+		if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
 			/* flush and invalidate data cache
 			 *
 			 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
@@ -614,7 +623,7 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 				return retval;
 		}
 
-		uint32_t pa;
+		target_addr_t pa;
 		retval = target->type->virt2phys(target, address, &pa);
 		if (retval != ERROR_OK)
 			return retval;
@@ -623,24 +632,20 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 		retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
 		if (retval != ERROR_OK)
 			return retval;
-	} else
-	{
-		if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
+	} else {
+		retval = arm7_9_write_memory(target, address, size, count, buffer);
+		if (retval != ERROR_OK)
 			return retval;
 	}
 
 	/* If ICache is enabled, we have to invalidate affected ICache lines
 	 * the DCache is forced to write-through, so we don't have to clean it here
 	 */
-	if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
-	{
-		if (count <= 1)
-		{
+	if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled) {
+		if (count <= 1) {
 			/* invalidate ICache single entry with MVA */
 			arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
-		}
-		else
-		{
+		} else {
 			/* invalidate ICache */
 			arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
 		}
@@ -650,8 +655,8 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 }
 
 static int arm926ejs_write_phys_memory(struct target *target,
-		uint32_t address, uint32_t size,
-		uint32_t count, uint8_t *buffer)
+		target_addr_t address, uint32_t size,
+		uint32_t count, const uint8_t *buffer)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
@@ -660,7 +665,7 @@ static int arm926ejs_write_phys_memory(struct target *target,
 }
 
 static int arm926ejs_read_phys_memory(struct target *target,
-		uint32_t address, uint32_t size,
+		target_addr_t address, uint32_t size,
 		uint32_t count, uint8_t *buffer)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
@@ -674,8 +679,8 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
 {
 	struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
 
-	arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
-	arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
+	arm7_9->arm.mrc = arm926ejs_mrc;
+	arm7_9->arm.mcr = arm926ejs_mcr;
 
 	/* initialize arm7/arm9 specific info (including armv4_5) */
 	arm9tdmi_init_arch_info(target, arm7_9, tap);
@@ -684,6 +689,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
 
 	arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 	arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
+	arm7_9->write_memory = arm926ejs_write_memory;
 
 	arm926ejs->read_cp15 = arm926ejs_cp15_read;
 	arm926ejs->write_cp15 = arm926ejs_cp15_write;
@@ -709,7 +715,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
 
 static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
 {
-	struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
+	struct arm926ejs_common *arm926ejs = calloc(1, sizeof(struct arm926ejs_common));
 
 	/* ARM9EJ-S core always reports 0x1 in Capture-IR */
 	target->tap->ir_capture_mask = 0x0f;
@@ -730,19 +736,16 @@ COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
 	return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 }
 
-static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical)
+static int arm926ejs_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
 {
-	int type;
 	uint32_t cb;
-	int domain;
-	uint32_t ap;
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
-	uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
-	if (type == -1)
-	{
-		return ret;
-	}
+	uint32_t ret;
+	int retval = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu,
+			virtual, &cb, &ret);
+	if (retval != ERROR_OK)
+		return retval;
 	*physical = ret;
 	return ERROR_OK;
 }
@@ -751,8 +754,7 @@ static int arm926ejs_mmu(struct target *target, int *enabled)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
-	if (target->state != TARGET_HALTED)
-	{
+	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_INVALID;
 	}
@@ -763,8 +765,9 @@ static int arm926ejs_mmu(struct target *target, int *enabled)
 static const struct command_registration arm926ejs_exec_command_handlers[] = {
 	{
 		.name = "cache_info",
-		.handler = &arm926ejs_handle_cache_info_command,
+		.handler = arm926ejs_handle_cache_info_command,
 		.mode = COMMAND_EXEC,
+		.usage = "",
 		.help = "display information about target caches",
 
 	},
@@ -778,14 +781,14 @@ const struct command_registration arm926ejs_command_handlers[] = {
 		.name = "arm926ejs",
 		.mode = COMMAND_ANY,
 		.help = "arm926ejs command group",
+		.usage = "",
 		.chain = arm926ejs_exec_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };
 
 /** Holds methods for ARM926 targets. */
-struct target_type arm926ejs_target =
-{
+struct target_type arm926ejs_target = {
 	.name = "arm926ejs",
 
 	.poll = arm7_9_poll,
@@ -801,11 +804,11 @@ struct target_type arm926ejs_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_arch = arm_get_gdb_arch,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
-	.write_memory = arm926ejs_write_memory,
-	.bulk_write_memory = arm7_9_bulk_write_memory,
+	.write_memory = arm7_9_write_memory_opt,
 
 	.checksum_memory = arm_checksum_memory,
 	.blank_check_memory = arm_blank_check_memory,
@@ -821,6 +824,7 @@ struct target_type arm926ejs_target =
 	.target_create = arm926ejs_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 	.virt2phys = arm926ejs_virt2phys,
 	.mmu = arm926ejs_mmu,