X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=4a711439472a2b249de07fa925f004ca6ead799c;hp=cef7061ed13ac3e05d4c958ee96f20afaf7d21b7;hb=d5e183c31f3e6f95f41dd72ac530e1c3dc5adc11;hpb=9eb2deee0614bb79dfde70fcb65edbaaa458b761 diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index cef7061ed1..4a71143947 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -23,6 +23,7 @@ #include "arm926ejs.h" #include "time_support.h" +#include "target_type.h" #if 0 @@ -44,9 +45,9 @@ int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *c int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp); int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm926ejs_quit(void); -int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer); +int arm926ejs_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer); -static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical); +static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical); static int arm926ejs_mmu(struct target_s *target, int *enabled); target_type_t arm926ejs_target = @@ -90,15 +91,15 @@ target_type_t arm926ejs_target = .mmu = arm926ejs_mmu }; -int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field) +int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field) { /* FIX!!!! this code should be reenabled. For now it does not check * the queue...*/ return 0; #if 0 /* The ARM926EJ-S' instruction register is 4 bits wide */ - u8 t = *captured & 0xf; - u8 t2 = *field->in_check_value & 0xf; + uint8_t t = *captured & 0xf; + uint8_t t2 = *field->in_check_value & 0xf; if (t == t2) { return ERROR_OK; @@ -114,21 +115,21 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field) #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) -int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value) +int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); + uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); scan_field_t fields[4]; - u8 address_buf[2]; - u8 nr_w_buf = 0; - u8 access = 1; + uint8_t address_buf[2]; + uint8_t nr_w_buf = 0; + uint8_t access = 1; buf_set_u32(address_buf, 0, 14, address); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -138,7 +139,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; - fields[0].in_value = (u8 *)value; + fields[0].in_value = (uint8_t *)value; fields[1].tap = jtag_info->tap; @@ -156,23 +157,36 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); - /*TODO: add timeout*/ - do + long long then = timeval_ms(); + + for (;;) { /* rescan with NOP, to wait for the access to complete */ access = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); - jtag_add_callback(arm_le_to_h_u32, (u8 *)value); + jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - } while (buf_get_u32(&access, 0, 1) != 1); + + if (buf_get_u32(&access, 0, 1) == 1) + { + break; + } + + /* 10ms timeout */ + if ((timeval_ms()-then)>10) + { + LOG_ERROR("cp15 read operation timed out"); + return ERROR_FAIL; + } + } #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value); @@ -183,23 +197,23 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 return ERROR_OK; } -int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value) +int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { int retval = ERROR_OK; armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); + uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); scan_field_t fields[4]; - u8 value_buf[4]; - u8 address_buf[2]; - u8 nr_w_buf = 1; - u8 access = 1; + uint8_t value_buf[4]; + uint8_t address_buf[2]; + uint8_t nr_w_buf = 1; + uint8_t access = 1; buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_IDLE); + jtag_set_end_state(TAP_IDLE); if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -226,19 +240,33 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, TAP_INVALID); - /*TODO: add timeout*/ - do + jtag_add_dr_scan(4, fields, jtag_get_end_state()); + + long long then = timeval_ms(); + + for (;;) { /* rescan with NOP, to wait for the access to complete */ access = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, TAP_INVALID); + jtag_add_dr_scan(4, fields, jtag_get_end_state()); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - } while (buf_get_u32(&access, 0, 1) != 1); + + if (buf_get_u32(&access, 0, 1) == 1) + { + break; + } + + /* 10ms timeout */ + if ((timeval_ms()-then)>10) + { + LOG_ERROR("cp15 write operation timed out"); + return ERROR_FAIL; + } + } #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("addr: 0x%x value: %8.8x", address, value); @@ -261,10 +289,12 @@ int arm926ejs_examine_debug_reason(target_t *target) if ((retval = jtag_execute_queue()) != ERROR_OK) return retval; + /* Method-Of-Entry (MOE) field */ debug_reason = buf_get_u32(dbg_stat->value, 6, 4); switch (debug_reason) { + /* case 0: no debug entry */ case 1: LOG_DEBUG("breakpoint from EICE unit 0"); target->debug_reason = DBG_REASON_BREAKPOINT; @@ -306,7 +336,21 @@ int arm926ejs_examine_debug_reason(target_t *target) target->debug_reason = DBG_REASON_DBGRQ; break; case 11: - LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here"); + LOG_DEBUG("debug re-entry from system speed access"); + /* This is normal when connecting to something that's + * already halted, or in some related code paths, but + * otherwise is surprising (and presumably wrong). + */ + switch (target->debug_reason) { + case DBG_REASON_DBGRQ: + break; + default: + LOG_ERROR("unexpected -- debug re-entry"); + /* FALLTHROUGH */ + case DBG_REASON_UNDEFINED: + target->debug_reason = DBG_REASON_DBGRQ; + break; + } break; case 12: /* FIX!!!! here be dragons!!! We need to fail here so @@ -316,30 +360,31 @@ int arm926ejs_examine_debug_reason(target_t *target) * openocd development mailing list if you have hardware * to donate to look into this problem.... */ - LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt."); + LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt."); target->debug_reason = DBG_REASON_DBGRQ; - retval = ERROR_TARGET_FAILURE; break; default: - LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason); + LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); + /* Oh agony! should we interpret this as a halt request or + * that the target stopped on it's own accord? + */ target->debug_reason = DBG_REASON_DBGRQ; /* if we fail here, we won't talk to the target and it will * be reported to be in the halted state */ - retval = ERROR_TARGET_FAILURE; break; } - return retval; + return ERROR_OK; } -u32 arm926ejs_get_ttb(target_t *target) +uint32_t arm926ejs_get_ttb(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; int retval; - u32 ttb = 0x0; + uint32_t ttb = 0x0; if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK) return retval; @@ -353,7 +398,7 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); @@ -369,7 +414,7 @@ void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int if (d_u_cache) { - u32 debug_override; + uint32_t debug_override; /* read-modify-write CP15 debug override register * to enable "test and clean all" */ arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); @@ -404,7 +449,7 @@ void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info; - u32 cp15_control; + uint32_t cp15_control; /* read cp15 control register */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); @@ -432,11 +477,11 @@ void arm926ejs_post_debug_entry(target_t *target) /* examine cp15 control reg */ arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); jtag_execute_queue(); - LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg); + LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg); if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) { - u32 cache_type_reg; + uint32_t cache_type_reg; /* identify caches */ arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); jtag_execute_queue(); @@ -452,10 +497,10 @@ void arm926ejs_post_debug_entry(target_t *target) arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); - LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x", + LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "", arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); - u32 cache_dbg_ctrl; + uint32_t cache_dbg_ctrl; /* read-modify-write CP15 cache debug control register * to disable I/D-cache linefills and force WT */ @@ -476,7 +521,7 @@ void arm926ejs_pre_restore_context(target_t *target) arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr); arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far); - u32 cache_dbg_ctrl; + uint32_t cache_dbg_ctrl; /* read-modify-write CP15 cache debug control register * to reenable I/D-cache linefills and disable WT */ @@ -543,10 +588,10 @@ int arm926ejs_arch_state(struct target_s *target) LOG_USER( "target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8x pc: 0x%8.8x\n" + "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" "MMU: %s, D-Cache: %s, I-Cache: %s", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name, + Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), @@ -571,9 +616,9 @@ int arm926ejs_soft_reset_halt(struct target_s *target) return retval; } - long long then=timeval_ms(); + long long then = timeval_ms(); int timeout; - while (!(timeout=((timeval_ms()-then)>1000))) + while (!(timeout = ((timeval_ms()-then) > 1000))) { if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) { @@ -586,7 +631,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target) { break; } - if (debug_level>=1) + if (debug_level >= 1) { /* do not eat all CPU, time out after 1 se*/ alive_sleep(100); @@ -624,7 +669,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target) return target_call_event_callbacks(target, TARGET_EVENT_HALTED); } -int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) +int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { int retval; armv4_5_common_t *armv4_5 = target->arch_info; @@ -777,7 +822,7 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, if (argc == 4) { - u32 value; + uint32_t value; if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK) { command_print(cmd_ctx, "couldn't access register"); @@ -788,17 +833,17 @@ int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, return retval; } - command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); + command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); } else { - u32 value = strtoul(args[4], NULL, 0); + uint32_t value = strtoul(args[4], NULL, 0); if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK) { command_print(cmd_ctx, "couldn't access register"); return ERROR_OK; } - command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value); + command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); } return ERROR_OK; @@ -899,13 +944,13 @@ int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu); } -static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical) +static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) { int retval; int type; - u32 cb; + uint32_t cb; int domain; - u32 ap; + uint32_t ap; armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -916,7 +961,7 @@ static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physic { return retval; } - u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); + uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); if (type == -1) { return ret;