X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm926ejs.c;h=873e9a033e73b7029a64b8014b7482a33b19e391;hp=77405a870105d087cbb8c42e6272547820d4afe1;hb=f6315d5e5b7b71515ef051711e5f818a42d6b3b3;hpb=a585bdf7269ce5c861c83ee3294ba1f074e9c877 diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 77405a8701..873e9a033e 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -25,8 +25,10 @@ #endif #include "arm926ejs.h" -#include "time_support.h" +#include #include "target_type.h" +#include "register.h" +#include "arm_opcodes.h" /* @@ -47,58 +49,54 @@ #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0)) -static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, +static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { int retval = ERROR_OK; - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); - scan_field_t fields[4]; - uint8_t address_buf[2]; + struct scan_field fields[4]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 0; - uint8_t access = 1; + uint8_t access_t = 1; buf_set_u32(address_buf, 0, 14, address); - jtag_set_end_state(TAP_IDLE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) { return retval; } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; fields[0].in_value = (uint8_t *)value; - - fields[1].tap = jtag_info->tap; fields[1].num_bits = 1; - fields[1].out_value = &access; - fields[1].in_value = &access; + fields[1].out_value = &access_t; + fields[1].in_value = &access_t; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 14; fields[2].out_value = address_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); long long then = timeval_ms(); for (;;) { /* rescan with NOP, to wait for the access to complete */ - access = 0; + access_t = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value); @@ -107,7 +105,7 @@ static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, return retval; } - if (buf_get_u32(&access, 0, 1) == 1) + if (buf_get_u32(&access_t, 0, 1) == 1) { break; } @@ -124,12 +122,14 @@ static int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value); #endif - arm_jtag_set_instr(jtag_info, 0xc, NULL); + retval = arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } -static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1, +static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { if (cpnum != 15) { @@ -139,65 +139,62 @@ static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1, return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value); } -static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, +static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { int retval = ERROR_OK; - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm); - scan_field_t fields[4]; + struct scan_field fields[4]; uint8_t value_buf[4]; - uint8_t address_buf[2]; + uint8_t address_buf[2] = {0, 0}; uint8_t nr_w_buf = 1; - uint8_t access = 1; + uint8_t access_t = 1; buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - jtag_set_end_state(TAP_IDLE); - if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) + if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK) { return retval; } - arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); + retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; - fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = value_buf; fields[0].in_value = NULL; - fields[1].tap = jtag_info->tap; fields[1].num_bits = 1; - fields[1].out_value = &access; - fields[1].in_value = &access; + fields[1].out_value = &access_t; + fields[1].in_value = &access_t; - fields[2].tap = jtag_info->tap; fields[2].num_bits = 14; fields[2].out_value = address_buf; fields[2].in_value = NULL; - fields[3].tap = jtag_info->tap; fields[3].num_bits = 1; fields[3].out_value = &nr_w_buf; fields[3].in_value = NULL; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); long long then = timeval_ms(); for (;;) { /* rescan with NOP, to wait for the access to complete */ - access = 0; + access_t = 0; nr_w_buf = 0; - jtag_add_dr_scan(4, fields, jtag_get_end_state()); + jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - if (buf_get_u32(&access, 0, 1) == 1) + if (buf_get_u32(&access_t, 0, 1) == 1) { break; } @@ -214,12 +211,14 @@ static int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, LOG_DEBUG("addr: 0x%x value: %8.8x", address, value); #endif - arm_jtag_set_instr(jtag_info, 0xf, NULL); + retval = arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } -static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1, +static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { if (cpnum != 15) { @@ -229,10 +228,10 @@ static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1, return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value); } -static int arm926ejs_examine_debug_reason(target_t *target) +static int arm926ejs_examine_debug_reason(struct target *target) { - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; int debug_reason; int retval; @@ -332,32 +331,41 @@ static int arm926ejs_examine_debug_reason(target_t *target) return ERROR_OK; } -static uint32_t arm926ejs_get_ttb(target_t *target) +static int arm926ejs_get_ttb(struct target *target, uint32_t *result) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); int retval; uint32_t ttb = 0x0; if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK) return retval; - return ttb; + *result = ttb; + + return ERROR_OK; } -static void arm926ejs_disable_mmu_caches(target_t *target, int mmu, +static int arm926ejs_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) { /* invalidate TLB */ - arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); + retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0); + if (retval != ERROR_OK) + return retval; cp15_control &= ~0x1U; } @@ -367,17 +375,25 @@ static void arm926ejs_disable_mmu_caches(target_t *target, int mmu, uint32_t debug_override; /* read-modify-write CP15 debug override register * to enable "test and clean all" */ - arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); + retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override); + if (retval != ERROR_OK) + return retval; debug_override |= 0x80000; - arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + if (retval != ERROR_OK) + return retval; /* clean and invalidate DCache */ - arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + if (retval != ERROR_OK) + return retval; /* write CP15 debug override register * to disable "test and clean all" */ debug_override &= ~0x80000; - arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override); + if (retval != ERROR_OK) + return retval; cp15_control &= ~0x4U; } @@ -385,23 +401,31 @@ static void arm926ejs_disable_mmu_caches(target_t *target, int mmu, if (i_cache) { /* invalidate ICache */ - arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0); + if (retval != ERROR_OK) + return retval; cp15_control &= ~0x1000U; } - arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + return retval; } -static void arm926ejs_enable_mmu_caches(target_t *target, int mmu, +static int arm926ejs_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); uint32_t cp15_control; + int retval; /* read cp15 control register */ - arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; if (mmu) cp15_control |= 0x1U; @@ -412,24 +436,34 @@ static void arm926ejs_enable_mmu_caches(target_t *target, int mmu, if (i_cache) cp15_control |= 0x1000U; - arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control); + return retval; } -static void arm926ejs_post_debug_entry(target_t *target) +static int arm926ejs_post_debug_entry(struct target *target) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + int retval; /* examine cp15 control reg */ - arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg); if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) { uint32_t cache_type_reg; /* identify caches */ - arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); - jtag_execute_queue(); + retval = arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg); + if (retval != ERROR_OK) + return retval; + retval = jtag_execute_queue(); + if (retval != ERROR_OK) + return retval; armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache); } @@ -438,9 +472,15 @@ static void arm926ejs_post_debug_entry(target_t *target) arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0; /* save i/d fault status and address register */ - arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); - arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); - arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); + retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr); + if (retval != ERROR_OK) + return retval; + retval = arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr); + if (retval != ERROR_OK) + return retval; + retval = arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far); + if (retval != ERROR_OK) + return retval; LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "", arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr); @@ -449,14 +489,17 @@ static void arm926ejs_post_debug_entry(target_t *target) /* read-modify-write CP15 cache debug control register * to disable I/D-cache linefills and force WT */ - arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); + retval = arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl); + if (retval != ERROR_OK) + return retval; cache_dbg_ctrl |= 0x7; - arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); + retval = arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl); + return retval; } -static void arm926ejs_pre_restore_context(target_t *target) +static void arm926ejs_pre_restore_context(struct target *target) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); /* restore i/d fault status and address register */ arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr); @@ -474,8 +517,8 @@ static void arm926ejs_pre_restore_context(target_t *target) static const char arm926_not[] = "target is not an ARM926"; -static int arm926ejs_verify_pointer(struct command_context_s *cmd_ctx, - struct arm926ejs_common_s *arm926) +static int arm926ejs_verify_pointer(struct command_context *cmd_ctx, + struct arm926ejs_common *arm926) { if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) { command_print(cmd_ctx, arm926_not); @@ -485,15 +528,14 @@ static int arm926ejs_verify_pointer(struct command_context_s *cmd_ctx, } /** Logs summary of ARM926 state for a halted target. */ -int arm926ejs_arch_state(struct target_s *target) +int arm926ejs_arch_state(struct target *target) { static const char *state[] = { "disabled", "enabled" }; - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); - struct armv4_5_common_s *armv4_5; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) { @@ -501,16 +543,8 @@ int arm926ejs_arch_state(struct target_s *target) return ERROR_TARGET_INVALID; } - armv4_5 = &arm926ejs->arm9tdmi_common.arm7_9_common.armv4_5_common; - - LOG_USER("target halted in %s state due to %s, current mode: %s\n" - "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n" - "MMU: %s, D-Cache: %s, I-Cache: %s", - armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, - armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], - buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), - buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), + arm_arch_state(target); + LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s", state[arm926ejs->armv4_5_mmu.mmu_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); @@ -518,13 +552,13 @@ int arm926ejs_arch_state(struct target_s *target) return ERROR_OK; } -int arm926ejs_soft_reset_halt(struct target_s *target) +int arm926ejs_soft_reset_halt(struct target *target) { int retval = ERROR_OK; - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); - struct arm7_9_common_s *arm7_9 = target_to_arm7_9(target); - struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; - reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; + struct arm926ejs_common *arm926ejs = target_to_arm926(target); + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) { @@ -564,19 +598,22 @@ int arm926ejs_soft_reset_halt(struct target_s *target) target->state = TARGET_HALTED; /* SVC, ARM state, IRQ and FIQ disabled */ - buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; - armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; + uint32_t cpsr; - /* start fetching from 0x0 */ - buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); - armv4_5->core_cache->reg_list[15].dirty = 1; - armv4_5->core_cache->reg_list[15].valid = 1; + cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr &= ~0xff; + cpsr |= 0xd3; + arm_set_cpsr(armv4_5, cpsr); + armv4_5->cpsr->dirty = 1; - armv4_5->core_mode = ARMV4_5_MODE_SVC; - armv4_5->core_state = ARMV4_5_STATE_ARM; + /* start fetching from 0x0 */ + buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); + armv4_5->pc->dirty = 1; + armv4_5->pc->valid = 1; - arm926ejs_disable_mmu_caches(target, 1, 1, 1); + retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1); + if (retval != ERROR_OK) + return retval; arm926ejs->armv4_5_mmu.mmu_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0; @@ -585,15 +622,20 @@ int arm926ejs_soft_reset_halt(struct target_s *target) } /** Writes a buffer, in the specified word size, with current MMU settings. */ -int arm926ejs_write_memory(struct target_s *target, uint32_t address, - uint32_t size, uint32_t count, uint8_t *buffer) +int arm926ejs_write_memory(struct target *target, uint32_t address, + uint32_t size, uint32_t count, const uint8_t *buffer) { int retval; - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); /* FIX!!!! this should be cleaned up and made much more general. The * plan is to write up and test on arm926ejs specifically and - * then generalize and clean up afterwards. */ + * then generalize and clean up afterwards. + * + * + * Also it should be moved to the callbacks that handle breakpoints + * specifically and not the generic memory write fn's. See XScale code. + **/ if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4))) { /* special case the handling of single word writes to bypass MMU @@ -646,35 +688,36 @@ int arm926ejs_write_memory(struct target_s *target, uint32_t address, return retval; } -static int arm926ejs_write_phys_memory(struct target_s *target, +static int arm926ejs_write_phys_memory(struct target *target, uint32_t address, uint32_t size, - uint32_t count, uint8_t *buffer) + uint32_t count, const uint8_t *buffer) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer); } -static int arm926ejs_read_phys_memory(struct target_s *target, +static int arm926ejs_read_phys_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer); } -int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, - jtag_tap_t *tap) +int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, + struct jtag_tap *tap) { - arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common; - arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; + struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common; - /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) - */ - arm9tdmi_init_arch_info(target, arm9tdmi, tap); + arm7_9->armv4_5_common.mrc = arm926ejs_mrc; + arm7_9->armv4_5_common.mcr = arm926ejs_mcr; + + /* initialize arm7/arm9 specific info (including armv4_5) */ + arm9tdmi_init_arch_info(target, arm7_9, tap); arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; @@ -703,9 +746,9 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, return ERROR_OK; } -static int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp) +static int arm926ejs_target_create(struct target *target, Jim_Interp *interp) { - arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); + struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common)); /* ARM9EJ-S core always reports 0x1 in Capture-IR */ target->tap->ir_capture_mask = 0x0f; @@ -713,100 +756,36 @@ static int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp) return arm926ejs_init_arch_info(target, arm926ejs, target->tap); } -COMMAND_HANDLER(arm926ejs_handle_cp15_command) -{ - int retval; - target_t *target = get_current_target(cmd_ctx); - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); - int opcode_1; - int opcode_2; - int CRn; - int CRm; - - if ((argc < 4) || (argc > 5)) - { - command_print(cmd_ctx, "usage: arm926ejs cp15 [value]"); - return ERROR_OK; - } - - COMMAND_PARSE_NUMBER(int, args[0], opcode_1); - COMMAND_PARSE_NUMBER(int, args[1], opcode_2); - COMMAND_PARSE_NUMBER(int, args[2], CRn); - COMMAND_PARSE_NUMBER(int, args[3], CRm); - - retval = arm926ejs_verify_pointer(cmd_ctx, arm926ejs); - if (retval != ERROR_OK) - return retval; - - if (target->state != TARGET_HALTED) - { - command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME); - return ERROR_OK; - } - - if (argc == 4) - { - uint32_t value; - if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - return retval; - } - - command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); - } - else - { - uint32_t value; - COMMAND_PARSE_NUMBER(u32, args[4], value); - if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK) - { - command_print(cmd_ctx, "couldn't access register"); - return ERROR_OK; - } - command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value); - } - - return ERROR_OK; -} - COMMAND_HANDLER(arm926ejs_handle_cache_info_command) { int retval; - target_t *target = get_current_target(cmd_ctx); - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct target *target = get_current_target(CMD_CTX); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - retval = arm926ejs_verify_pointer(cmd_ctx, arm926ejs); + retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs); if (retval != ERROR_OK) return retval; - return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache); + return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache); } -static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical) +static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical) { - int type; uint32_t cb; - int domain; - uint32_t ap; - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); - uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap); - if (type == -1) - { - return ret; - } + uint32_t ret; + int retval = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, + virtual, &cb, &ret); + if (retval != ERROR_OK) + return retval; *physical = ret; return ERROR_OK; } -static int arm926ejs_mmu(struct target_s *target, int *enabled) +static int arm926ejs_mmu(struct target *target, int *enabled) { - struct arm926ejs_common_s *arm926ejs = target_to_arm926(target); + struct arm926ejs_common *arm926ejs = target_to_arm926(target); if (target->state != TARGET_HALTED) { @@ -817,32 +796,31 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled) return ERROR_OK; } -/** Registers commands to access coprocessor, cache, and debug resources. */ -int arm926ejs_register_commands(struct command_context_s *cmd_ctx) -{ - int retval; - command_t *arm926ejs_cmd; - - retval = arm9tdmi_register_commands(cmd_ctx); - - arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", - NULL, COMMAND_ANY, - "arm926ejs specific commands"); - - register_command(cmd_ctx, arm926ejs_cmd, "cp15", - arm926ejs_handle_cp15_command, COMMAND_EXEC, - "display/modify cp15 register " - " [value]"); - - register_command(cmd_ctx, arm926ejs_cmd, "cache_info", - arm926ejs_handle_cache_info_command, COMMAND_EXEC, - "display information about target caches"); +static const struct command_registration arm926ejs_exec_command_handlers[] = { + { + .name = "cache_info", + .handler = arm926ejs_handle_cache_info_command, + .mode = COMMAND_EXEC, + .help = "display information about target caches", - return retval; -} + }, + COMMAND_REGISTRATION_DONE +}; +const struct command_registration arm926ejs_command_handlers[] = { + { + .chain = arm9tdmi_command_handlers, + }, + { + .name = "arm926ejs", + .mode = COMMAND_ANY, + .help = "arm926ejs command group", + .chain = arm926ejs_exec_command_handlers, + }, + COMMAND_REGISTRATION_DONE +}; /** Holds methods for ARM926 targets. */ -target_type_t arm926ejs_target = +struct target_type arm926ejs_target = { .name = "arm926ejs", @@ -859,13 +837,14 @@ target_type_t arm926ejs_target = .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + .get_gdb_reg_list = arm_get_gdb_reg_list, .read_memory = arm7_9_read_memory, .write_memory = arm926ejs_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, + + .checksum_memory = arm_checksum_memory, + .blank_check_memory = arm_blank_check_memory, .run_algorithm = armv4_5_run_algorithm, @@ -874,15 +853,14 @@ target_type_t arm926ejs_target = .add_watchpoint = arm7_9_add_watchpoint, .remove_watchpoint = arm7_9_remove_watchpoint, - .register_commands = arm926ejs_register_commands, + .commands = arm926ejs_command_handlers, .target_create = arm926ejs_target_create, .init_target = arm9tdmi_init_target, - .examine = arm9tdmi_examine, + .examine = arm7_9_examine, + .check_reset = arm7_9_check_reset, .virt2phys = arm926ejs_virt2phys, .mmu = arm926ejs_mmu, .read_phys_memory = arm926ejs_read_phys_memory, .write_phys_memory = arm926ejs_write_phys_memory, - .mrc = arm926ejs_mrc, - .mcr = arm926ejs_mcr, };