X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm9tdmi.c;h=fdd395a52d1097200667b485b1a6623586cab97b;hp=75ae3e8b78e2effef687c990ad061b362ba681c3;hb=22f6a4cef5b4bf6696a7ea0fa41fafc3da06c9fa;hpb=53d605e12c3765aeedabf2bfe0c5cc338dc95d5a diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 75ae3e8b78..fdd395a52d 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -31,65 +31,27 @@ #include "target_type.h" +/* + * NOTE: this holds code that's used with multiple ARM9 processors: + * - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores + * - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores + * - ARM9EJS (ARMv5TEJ) ... in ARM926 core + * + * In short, the file name is a misnomer ... it is NOT specific to + * that first generation ARM9 processor, or cores using it. + */ + #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif -/* cli handling */ -int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); - -/* forward declarations */ -int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp ); - -int arm9tdmi_quit(void); - -target_type_t arm9tdmi_target = -{ - .name = "arm9tdmi", - - .poll = arm7_9_poll, - .arch_state = armv4_5_arch_state, - - .target_request_data = arm7_9_target_request_data, - - .halt = arm7_9_halt, - .resume = arm7_9_resume, - .step = arm7_9_step, - - .assert_reset = arm7_9_assert_reset, - .deassert_reset = arm7_9_deassert_reset, - .soft_reset_halt = arm7_9_soft_reset_halt, - - .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - - .read_memory = arm7_9_read_memory, - .write_memory = arm7_9_write_memory, - .bulk_write_memory = arm7_9_bulk_write_memory, - .checksum_memory = arm7_9_checksum_memory, - .blank_check_memory = arm7_9_blank_check_memory, - - .run_algorithm = armv4_5_run_algorithm, - - .add_breakpoint = arm7_9_add_breakpoint, - .remove_breakpoint = arm7_9_remove_breakpoint, - .add_watchpoint = arm7_9_add_watchpoint, - .remove_watchpoint = arm7_9_remove_watchpoint, - - .register_commands = arm9tdmi_register_commands, - .target_create = arm9tdmi_target_create, - .init_target = arm9tdmi_init_target, - .examine = arm9tdmi_examine, - .quit = arm9tdmi_quit -}; - -arm9tdmi_vector_t arm9tdmi_vectors[] = +static const struct arm9tdmi_vector arm9tdmi_vectors[] = { {"reset", ARM9TDMI_RESET_VECTOR}, {"undef", ARM9TDMI_UNDEF_VECTOR}, {"swi", ARM9TDMI_SWI_VECTOR}, {"pabt", ARM9TDMI_PABT_VECTOR}, {"dabt", ARM9TDMI_DABT_VECTOR}, - {"reserved", ARM9TDMI_RESERVED_VECTOR}, {"irq", ARM9TDMI_IRQ_VECTOR}, {"fiq", ARM9TDMI_FIQ_VECTOR}, {0, 0}, @@ -98,15 +60,13 @@ arm9tdmi_vector_t arm9tdmi_vectors[] = int arm9tdmi_examine_debug_reason(target_t *target) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t databus[4]; uint8_t instructionbus[4]; uint8_t debug_reason; @@ -161,11 +121,14 @@ int arm9tdmi_examine_debug_reason(target_t *target) return ERROR_OK; } -/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */ -int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed) +/* put an instruction in the ARM9TDMI pipeline or write the data bus, + * and optionally read data + */ +int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr, + uint32_t out, uint32_t *in, int sysspeed) { int retval = ERROR_OK; - scan_field_t fields[3]; + struct scan_field fields[3]; uint8_t out_buf[4]; uint8_t instr_buf[4]; uint8_t sysspeed_buf = 0x0; @@ -203,7 +166,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint if (in) { - fields[0].in_value=(uint8_t *)in; + fields[0].in_value = (uint8_t *)in; jtag_add_dr_scan(3, fields, jtag_get_end_state()); jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in); @@ -235,10 +198,10 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint } /* just read data (instruction and data-out = don't care) */ -int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) +int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in) { int retval = ERROR_OK;; - scan_field_t fields[3]; + struct scan_field fields[3]; jtag_set_end_state(TAP_DRPAUSE); if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) @@ -292,21 +255,25 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in) extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip); -static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured) +static int arm9endianness(jtag_callback_data_t arg, + jtag_callback_data_t size, jtag_callback_data_t be, + jtag_callback_data_t captured) { - uint8_t *in=(uint8_t *)arg; + uint8_t *in = (uint8_t *)arg; + arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0); return ERROR_OK; } /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes - * are stored in big (be==1) or little (be==0) endianness + * are stored in big (be == 1) or little (be == 0) endianness */ -int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) +int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info, + void *in, int size, int be) { int retval = ERROR_OK; - scan_field_t fields[3]; + struct scan_field fields[3]; jtag_set_end_state(TAP_DRPAUSE); if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) @@ -358,13 +325,12 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, return ERROR_OK; } -void arm9tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) +static void arm9tdmi_change_to_arm(target_t *target, + uint32_t *r0, uint32_t *pc) { int retval = ERROR_OK; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -413,13 +379,12 @@ void arm9tdmi_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) *pc -= 0xc; } -void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) +void arm9tdmi_read_core_regs(target_t *target, + uint32_t mask, uint32_t* core_regs[16]) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -439,13 +404,12 @@ void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg } } -void arm9tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) +static void arm9tdmi_read_core_regs_target_buffer(target_t *target, + uint32_t mask, void* buffer, int size) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; uint16_t *buf_u16 = buffer; @@ -480,12 +444,10 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, uint32_t mask, void } } -void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) +static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* MRS r0, cpsr */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); @@ -504,12 +466,10 @@ void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0); } -void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) +static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -540,12 +500,11 @@ void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); } -void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) +static void arm9tdmi_write_xpsr_im8(target_t *target, + uint8_t xpsr_im, int rot, int spsr) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -566,13 +525,12 @@ void arm9tdmi_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps } } -void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) +void arm9tdmi_write_core_regs(target_t *target, + uint32_t mask, uint32_t core_regs[16]) { int i; - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -587,7 +545,7 @@ void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg for (i = 0; i <= 15; i++) { if (mask & (1 << i)) - /* nothing fetched, LDM still in EXECUTE (1+i cycle) */ + /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); } arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -595,10 +553,8 @@ void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg void arm9tdmi_load_word_regs(target_t *target, uint32_t mask) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load-multiple into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0); @@ -607,10 +563,8 @@ void arm9tdmi_load_word_regs(target_t *target, uint32_t mask) void arm9tdmi_load_hword_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load half-word into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0); @@ -619,10 +573,8 @@ void arm9tdmi_load_hword_reg(target_t *target, int num) void arm9tdmi_load_byte_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed load byte into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0); @@ -631,10 +583,8 @@ void arm9tdmi_load_byte_reg(target_t *target, int num) void arm9tdmi_store_word_regs(target_t *target, uint32_t mask) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store-multiple into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0); @@ -643,10 +593,8 @@ void arm9tdmi_store_word_regs(target_t *target, uint32_t mask) void arm9tdmi_store_hword_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store half-word into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0); @@ -655,22 +603,18 @@ void arm9tdmi_store_hword_reg(target_t *target, int num) void arm9tdmi_store_byte_reg(target_t *target, int num) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* put system-speed store byte into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); } -void arm9tdmi_write_pc(target_t *target, uint32_t pc) +static void arm9tdmi_write_pc(target_t *target, uint32_t pc) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK @@ -693,23 +637,20 @@ void arm9tdmi_write_pc(target_t *target, uint32_t pc) void arm9tdmi_branch_resume(target_t *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); } -void arm9tdmi_branch_resume_thumb(target_t *target) +static void arm9tdmi_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; - arm_jtag_t *jtag_info = &arm7_9->jtag_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* LDMIA r0-15, [r0] at debug speed @@ -764,9 +705,7 @@ void arm9tdmi_branch_resume_thumb(target_t *target) void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (arm7_9->has_single_step) { @@ -781,9 +720,7 @@ void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc) void arm9tdmi_disable_single_step(target_t *target) { - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); if (arm7_9->has_single_step) { @@ -796,11 +733,10 @@ void arm9tdmi_disable_single_step(target_t *target) } } -void arm9tdmi_build_reg_cache(target_t *target) +static void arm9tdmi_build_reg_cache(target_t *target) { - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - /* get pointers to arch-specific information */ - armv4_5_common_t *armv4_5 = target->arch_info; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); (*cache_p) = armv4_5_build_reg_cache(target, armv4_5); armv4_5->core_cache = (*cache_p); @@ -808,58 +744,52 @@ void arm9tdmi_build_reg_cache(target_t *target) int arm9tdmi_examine(struct target_s *target) { - /* get pointers to arch-specific information */ int retval; - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9 = armv4_5->arch_info; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); + if (!target_was_examined(target)) { - reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); - reg_cache_t *t; + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *t; /* one extra register (vector catch) */ - t=embeddedice_build_reg_cache(target, arm7_9); - if (t==NULL) + t = embeddedice_build_reg_cache(target, arm7_9); + if (t == NULL) return ERROR_FAIL; (*cache_p) = t; arm7_9->eice_cache = (*cache_p); - if (arm7_9->etm_ctx) + if (arm7_9->armv4_5_common.etm) { - arm_jtag_t *jtag_info = &arm7_9->jtag_info; - (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx); - arm7_9->etm_ctx->reg_cache = (*cache_p)->next; + struct arm_jtag *jtag_info = &arm7_9->jtag_info; + (*cache_p)->next = etm_build_reg_cache(target, + jtag_info, arm7_9->armv4_5_common.etm); + arm7_9->armv4_5_common.etm->reg_cache = (*cache_p)->next; } target_set_examined(target); } - if ((retval=embeddedice_setup(target)) != ERROR_OK) + if ((retval = embeddedice_setup(target)) != ERROR_OK) return retval; - if ((retval=arm7_9_setup(target)) != ERROR_OK) + if ((retval = arm7_9_setup(target)) != ERROR_OK) return retval; - if (arm7_9->etm_ctx) + if (arm7_9->armv4_5_common.etm) { - if ((retval=etm_setup(target)) != ERROR_OK) + if ((retval = etm_setup(target)) != ERROR_OK) return retval; } return ERROR_OK; } -int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) +int arm9tdmi_init_target(struct command_context_s *cmd_ctx, + struct target_s *target) { - arm9tdmi_build_reg_cache(target); - return ERROR_OK; } -int arm9tdmi_quit(void) -{ - return ERROR_OK; -} - -int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap) +int arm9tdmi_init_arch_info(target_t *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap) { armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; + struct arm7_9_common *arm7_9; arm7_9 = &arm9tdmi->arm7_9_common; armv4_5 = &arm7_9->armv4_5_common; @@ -894,7 +824,6 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_ arm7_9->enable_single_step = arm9tdmi_enable_single_step; arm7_9->disable_single_step = arm9tdmi_disable_single_step; - arm7_9->pre_debug_entry = NULL; arm7_9->post_debug_entry = NULL; arm7_9->pre_restore_context = NULL; @@ -905,10 +834,6 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_ arm7_9->thumb_bkpt = 0xdeee; arm7_9->dbgreq_adjust_pc = 3; - arm7_9->arch_info = arm9tdmi; - - arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC; - arm9tdmi->arch_info = NULL; arm7_9_init_arch_info(target, arm7_9); @@ -921,71 +846,29 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_ return ERROR_OK; } -int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p) +static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp) { - armv4_5_common_t *armv4_5 = target->arch_info; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; - - if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) - { - return -1; - } - - arm7_9 = armv4_5->arch_info; - if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) - { - return -1; - } - - arm9tdmi = arm7_9->arch_info; - if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) - { - return -1; - } - - *armv4_5_p = armv4_5; - *arm7_9_p = arm7_9; - *arm9tdmi_p = arm9tdmi; - - return ERROR_OK; -} - -int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp) -{ - arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t)); + struct arm9tdmi_common *arm9tdmi = calloc(1,sizeof(struct arm9tdmi_common)); arm9tdmi_init_arch_info(target, arm9tdmi, target->tap); + arm9tdmi->arm7_9_common.armv4_5_common.is_armv4 = true; return ERROR_OK; } -int arm9tdmi_register_commands(struct command_context_s *cmd_ctx) -{ - int retval; - command_t *arm9tdmi_cmd; - - retval = arm7_9_register_commands(cmd_ctx); - arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands"); - register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'']"); - - return retval; -} - -int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command) { target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; - arm7_9_common_t *arm7_9; - arm9tdmi_common_t *arm9tdmi; + struct arm7_9_common *arm7_9 = target_to_arm7_9(target); reg_t *vector_catch; uint32_t vector_catch_value; - int i, j; - if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK) - { - command_print(cmd_ctx, "current target isn't an ARM9TDMI based target"); - return ERROR_OK; + /* it's uncommon, but some ARM7 chips can support this */ + if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC + || !arm7_9->has_vector_catch) { + command_print(cmd_ctx, "target doesn't have EmbeddedICE " + "with vector_catch"); + return ERROR_TARGET_INVALID; } vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]; @@ -995,7 +878,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha embeddedice_read_reg(vector_catch); /* get the current setting */ - vector_catch_value = buf_get_u32(vector_catch->value, 0, 32); + vector_catch_value = buf_get_u32(vector_catch->value, 0, 8); if (argc > 0) { @@ -1010,9 +893,10 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha } else { - for (i = 0; i < argc; i++) + for (unsigned i = 0; i < argc; i++) { /* go through list of vectors */ + unsigned j; for (j = 0; arm9tdmi_vectors[j].name; j++) { if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0) @@ -1028,7 +912,9 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]); /* reread current setting */ - vector_catch_value = buf_get_u32(vector_catch->value, 0, 32); + vector_catch_value = buf_get_u32( + vector_catch->value, + 0, 8); break; } @@ -1036,19 +922,71 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha } /* store new settings */ - buf_set_u32(vector_catch->value, 0, 32, vector_catch_value); + buf_set_u32(vector_catch->value, 0, 8, vector_catch_value); embeddedice_store_reg(vector_catch); } - /* output current settings (skip RESERVED vector) */ - for (i = 0; i < 8; i++) - { - if (i != 5) - { - command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name, - (vector_catch_value & (1 << i)) ? "catch" : "don't catch"); - } + /* output current settings */ + for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) { + command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name, + (vector_catch_value & arm9tdmi_vectors[i].value) + ? "catch" : "don't catch"); } return ERROR_OK; } + +int arm9tdmi_register_commands(struct command_context_s *cmd_ctx) +{ + int retval; + command_t *arm9tdmi_cmd; + + retval = arm7_9_register_commands(cmd_ctx); + arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9", + NULL, COMMAND_ANY, + "arm9 specific commands"); + register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", + handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, + "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ..."); + + return retval; +} + +/** Holds methods for ARM9TDMI targets. */ +target_type_t arm9tdmi_target = +{ + .name = "arm9tdmi", + + .poll = arm7_9_poll, + .arch_state = armv4_5_arch_state, + + .target_request_data = arm7_9_target_request_data, + + .halt = arm7_9_halt, + .resume = arm7_9_resume, + .step = arm7_9_step, + + .assert_reset = arm7_9_assert_reset, + .deassert_reset = arm7_9_deassert_reset, + .soft_reset_halt = arm7_9_soft_reset_halt, + + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, + + .read_memory = arm7_9_read_memory, + .write_memory = arm7_9_write_memory, + .bulk_write_memory = arm7_9_bulk_write_memory, + .checksum_memory = arm7_9_checksum_memory, + .blank_check_memory = arm7_9_blank_check_memory, + + .run_algorithm = armv4_5_run_algorithm, + + .add_breakpoint = arm7_9_add_breakpoint, + .remove_breakpoint = arm7_9_remove_breakpoint, + .add_watchpoint = arm7_9_add_watchpoint, + .remove_watchpoint = arm7_9_remove_watchpoint, + + .register_commands = arm9tdmi_register_commands, + .target_create = arm9tdmi_target_create, + .init_target = arm9tdmi_init_target, + .examine = arm9tdmi_examine, +};