X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=39d8bde9092efe7174e986faebae926b1e0127cb;hp=7d6ae81d939593ba61bc663e0d67c80dfcb3e963;hb=dd890d4cad7c62a65d0efd04c5e0b700eeb5928d;hpb=db7e77237c5a8104b527aeb23a2546b4bab92d8a diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 7d6ae81d93..dfbc5ade2a 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -5,9 +5,14 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * - * Copyright (C) 2009 by Oyvind Harboe * + * Copyright (C) 2009-2010 by Oyvind Harboe * * oyvind.harboe@zylin.com * - * * + * * + * Copyright (C) 2009-2010 by David Brownell * + * * + * Copyright (C) 2013 by Andreas Fritiofson * + * andreas.fritiofson@gmail.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -19,39 +24,58 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ -/*************************************************************************** - * * - * This file implements support for the ARM Debug Interface v5 (ADI_V5) * - * * - * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A * - * * - * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A * - * Cortex-M3(tm) TRM, ARM DDI 0337C * - * * -***************************************************************************/ + +/** + * @file + * This file implements support for the ARM Debug Interface version 5 (ADIv5) + * debugging architecture. Compared with previous versions, this includes + * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message + * transport, and focusses on memory mapped resources as defined by the + * CoreSight architecture. + * + * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two + * basic components: a Debug Port (DP) transporting messages to and from a + * debugger, and an Access Port (AP) accessing resources. Three types of DP + * are defined. One uses only JTAG for communication, and is called JTAG-DP. + * One uses only SWD for communication, and is called SW-DP. The third can + * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP + * is used to access memory mapped resources and is called a MEM-AP. Also a + * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon. + * + * This programming interface allows DAP pipelined operations through a + * transaction queue. This primarily affects AP operations (such as using + * a MEM-AP to access memory or registers). If the current transaction has + * not finished by the time the next one must begin, and the ORUNDETECT bit + * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and + * further AP operations will fail. There are two basic methods to avoid + * such overrun errors. One involves polling for status instead of using + * transaction piplining. The other involves adding delays to ensure the + * AP has enough time to complete one operation before starting the next + * one. (For JTAG these delays are controlled by memaccess_tck.) + */ + +/* + * Relevant specifications from ARM include: + * + * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A + * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B + * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D + * Cortex-M3(tm) TRM, ARM DDI 0337G + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif +#include "jtag/interface.h" +#include "arm.h" #include "arm_adi_v5.h" -#include "time_support.h" - -/* - * Transaction Mode: - * swjdp->trans_mode = TRANS_MODE_COMPOSITE; - * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction - * result checking until swjdp_end_transaction() - * This must be done before using or deallocating any return variables. - * swjdp->trans_mode == TRANS_MODE_ATOMIC - * All reads and writes to the AHB bus are checked for valid completion, and return values - * are immediatley available. -*/ - +#include +#include +#include /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ @@ -61,1071 +85,1724 @@ */ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address) { - return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2; + return tar_autoincr_block - ((tar_autoincr_block - 1) & address); } /*************************************************************************** * * - * DPACC and APACC scanchain access through JTAG-DP * + * DP and MEM-AP register access through APACC and DPACC * * * ***************************************************************************/ -/* Scan out and in from target ordered uint8_t buffers */ -int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) -{ - arm_jtag_t *jtag_info = swjdp->jtag_info; - scan_field_t fields[2]; - uint8_t out_addr_buf; - - jtag_set_end_state(TAP_IDLE); - arm_jtag_set_instr(jtag_info, instr, NULL); - - /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); - - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); - fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - fields[1].out_value = outvalue; - fields[1].in_value = invalue; - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - - return ERROR_OK; -} - -/* Scan out and in from host ordered uint32_t variables */ -int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) +static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw) { - arm_jtag_t *jtag_info = swjdp->jtag_info; - scan_field_t fields[2]; - uint8_t out_value_buf[4]; - uint8_t out_addr_buf; - - jtag_set_end_state(TAP_IDLE); - arm_jtag_set_instr(jtag_info, instr, NULL); - - /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); - - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); - fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - buf_set_u32(out_value_buf, 0, 32, outvalue); - fields[1].out_value = out_value_buf; - fields[1].in_value = NULL; - - if (invalue) - { - fields[1].in_value = (uint8_t *)invalue; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - - jtag_add_callback(arm_le_to_h_u32, (uint8_t *)invalue); - } else - { + csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT | + ap->csw_default; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); + if (csw != ap->csw_value) { + /* LOG_DEBUG("DAP: Set CSW %x",csw); */ + int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw); + if (retval != ERROR_OK) + return retval; + ap->csw_value = csw; } - return ERROR_OK; } -/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -int scan_inout_check(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue) +static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar) { - adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - - if ((RnW == DPAP_READ) && (invalue != NULL)) - { - adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - } - - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ - if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - { - return swjdp_transaction_endcheck(swjdp); + if (!ap->tar_valid || tar != ap->tar_value) { + /* LOG_DEBUG("DAP: Set TAR %x",tar); */ + int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar); + if (retval != ERROR_OK) + return retval; + ap->tar_value = tar; + ap->tar_valid = true; } - return ERROR_OK; } -int scan_inout_check_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue) +static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar) { - adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - - if ((RnW==DPAP_READ) && (invalue != NULL)) - { - adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); + int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar); + if (retval != ERROR_OK) { + ap->tar_valid = false; + return retval; } - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ - if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - { - return swjdp_transaction_endcheck(swjdp); + retval = dap_run(ap->dap); + if (retval != ERROR_OK) { + ap->tar_valid = false; + return retval; } + ap->tar_value = *tar; + ap->tar_valid = true; return ERROR_OK; } -int swjdp_transaction_endcheck(swjdp_common_t *swjdp) +static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap) { - int retval; - uint32_t ctrlstat; - - /* too expensive to call keep_alive() here */ - -#if 0 - /* Danger!!!! BROKEN!!!! */ - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? - R956 introduced the check on return value here and now Michael Schwingen reports - that this code no longer works.... - - https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html - */ - if ((retval=jtag_execute_queue())!=ERROR_OK) - { - LOG_ERROR("BUG: Why does this fail the first time????"); - } - /* Why??? second time it works??? */ -#endif - - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - - swjdp->ack = swjdp->ack & 0x7; - - if (swjdp->ack != 2) - { - long long then=timeval_ms(); - while (swjdp->ack != 2) - { - if (swjdp->ack == 1) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction"); - return ERROR_JTAG_DEVICE_ERROR; - } - } - else - { - LOG_WARNING("Invalid ACK in SWJDP transaction"); - return ERROR_JTAG_DEVICE_ERROR; - } - - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - swjdp->ack = swjdp->ack & 0x7; - } - } else - { - /* common code path avoids fn to timeval_ms() */ - } - - /* Check for STICKYERR and STICKYORUN */ - if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) - { - LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat); - /* Check power to debug regions */ - if ((ctrlstat & 0xf0000000) != 0xf0000000) - { - ahbap_debugport_init(swjdp); - } - else - { - uint32_t mem_ap_csw, mem_ap_tar; - - /* Print information about last AHBAP access */ - LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); - if (ctrlstat & SSTICKYORUN) - LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); - - if (ctrlstat & SSTICKYERR) - LOG_ERROR("SWJ-DP STICKY ERROR"); - - /* Clear Sticky Error Bits */ - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - - LOG_DEBUG("swjdp: status 0x%x", ctrlstat); - - dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); - dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar); - + switch (ap->csw_value & CSW_ADDRINC_MASK) { + case CSW_ADDRINC_SINGLE: + switch (ap->csw_value & CSW_SIZE_MASK) { + case CSW_8BIT: + return 1; + case CSW_16BIT: + return 2; + case CSW_32BIT: + return 4; } - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - return ERROR_JTAG_DEVICE_ERROR; + case CSW_ADDRINC_PACKED: + return 4; } - - return ERROR_OK; + return 0; } -/*************************************************************************** - * * - * DP and MEM-AP register access through APACC and DPACC * - * * -***************************************************************************/ - -int dap_dp_write_reg(swjdp_common_t *swjdp, uint32_t value, uint8_t reg_addr) +/* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW + */ +static void mem_ap_update_tar_cache(struct adiv5_ap *ap) { - return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); -} + if (!ap->tar_valid) + return; -int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr) -{ - return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value); + uint32_t inc = mem_ap_get_tar_increment(ap); + if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value)) + ap->tar_valid = false; + else + ap->tar_value += inc; } -int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel) +/** + * Queue transactions setting up transfer parameters for the + * currently selected MEM-AP. + * + * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2 + * initiate data reads or writes using memory or peripheral addresses. + * If the CSW is configured for it, the TAR may be automatically + * incremented after each transfer. + * + * @param ap The MEM-AP. + * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this + * matches the cached value, the register is not changed. + * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this + * matches the cached address, the register is not changed. + * + * @return ERROR_OK if the transaction was properly queued, else a fault code. + */ +static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar) { - uint32_t select; - select = (apsel<<24) & 0xFF000000; - - if (select != swjdp->apsel) - { - swjdp->apsel = select; - /* Switching AP invalidates cached values */ - swjdp->dp_select_value = -1; - swjdp->ap_csw_value = -1; - swjdp->ap_tar_value = -1; - } - + int retval; + retval = mem_ap_setup_csw(ap, csw); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_setup_tar(ap, tar); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } -int dap_dp_bankselect(swjdp_common_t *swjdp,uint32_t ap_reg) +/** + * Asynchronous (queued) read of a word from memory or a system register. + * + * @param ap The MEM-AP to access. + * @param address Address of the 32-bit word to read; it must be + * readable by the currently selected MEM-AP. + * @param value points to where the word will be stored when the + * transaction queue is flushed (assuming no errors). + * + * @return ERROR_OK for success. Otherwise a fault code. + */ +int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, + uint32_t *value) { - uint32_t select; - select = (ap_reg & 0x000000F0); - - if (select != swjdp->dp_select_value) - { - dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT); - swjdp->dp_select_value = select; - } - - return ERROR_OK; -} + int retval; -int dap_ap_write_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t* out_value_buf) -{ - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + /* Use banked addressing (REG_BDx) to avoid some link traffic + * (updating TAR) when reading several consecutive addresses. + */ + retval = mem_ap_setup_transfer(ap, + CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK), + address & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; - return ERROR_OK; + return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value); } -int dap_ap_read_reg(swjdp_common_t *swjdp, uint32_t reg_addr, uint8_t *in_value_buf) -{ - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf); - - return ERROR_OK; -} -int dap_ap_write_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t value) +/** + * Synchronous read of a word from memory or a system register. + * As a side effect, this flushes any queued transactions. + * + * @param ap The MEM-AP to access. + * @param address Address of the 32-bit word to read; it must be + * readable by the currently selected MEM-AP. + * @param value points to where the result will be stored. + * + * @return ERROR_OK for success; *value holds the result. + * Otherwise a fault code. + */ +int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address, + uint32_t *value) { - uint8_t out_value_buf[4]; + int retval; - buf_set_u32(out_value_buf, 0, 32, value); - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + retval = mem_ap_read_u32(ap, address, value); + if (retval != ERROR_OK) + return retval; - return ERROR_OK; + return dap_run(ap->dap); } -int dap_ap_read_reg_u32(swjdp_common_t *swjdp, uint32_t reg_addr, uint32_t *value) +/** + * Asynchronous (queued) write of a word to memory or a system register. + * + * @param ap The MEM-AP to access. + * @param address Address to be written; it must be writable by + * the currently selected MEM-AP. + * @param value Word that will be written to the address when transaction + * queue is flushed (assuming no errors). + * + * @return ERROR_OK for success. Otherwise a fault code. + */ +int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, + uint32_t value) { - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value); - - return ERROR_OK; -} + int retval; -/*************************************************************************** - * * - * AHB-AP access to memory and system registers on AHB bus * - * * -***************************************************************************/ + /* Use banked addressing (REG_BDx) to avoid some link traffic + * (updating TAR) when writing several consecutive addresses. + */ + retval = mem_ap_setup_transfer(ap, + CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK), + address & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; -int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar) -{ - csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if (csw != swjdp->ap_csw_value) - { - /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ - dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw ); - swjdp->ap_csw_value = csw; - } - if (tar != swjdp->ap_tar_value) - { - /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ - dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar ); - swjdp->ap_tar_value = tar; - } - if (csw & CSW_ADDRINC_MASK) - { - /* Do not cache TAR value when autoincrementing */ - swjdp->ap_tar_value = -1; - } - return ERROR_OK; + return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC), + value); } -/***************************************************************************** -* * -* mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) * -* * -* Read a uint32_t value from memory or system register * -* Functionally equivalent to target_read_u32(target, address, uint32_t *value), * -* but with less overhead * -*****************************************************************************/ -int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) +/** + * Synchronous write of a word to memory or a system register. + * As a side effect, this flushes any queued transactions. + * + * @param ap The MEM-AP to access. + * @param address Address to be written; it must be writable by + * the currently selected MEM-AP. + * @param value Word that will be written. + * + * @return ERROR_OK for success; the data was written. Otherwise a fault code. + */ +int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address, + uint32_t value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + int retval = mem_ap_write_u32(ap, address, value); - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); - - return ERROR_OK; -} - -int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value) -{ - mem_ap_read_u32(swjdp, address, value); + if (retval != ERROR_OK) + return retval; - return swjdp_transaction_endcheck(swjdp); + return dap_run(ap->dap); } -/***************************************************************************** -* * -* mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) * -* * -* Write a uint32_t value to memory or memory mapped register * -* * -*****************************************************************************/ -int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) +/** + * Synchronous write of a block of memory, using a specific access size. + * + * @param ap The MEM-AP to access. + * @param buffer The data buffer to write. No particular alignment is assumed. + * @param size Which access size to use, in bytes. 1, 2 or 4. + * @param count The number of writes to do (in size units, not bytes). + * @param address Address to be written; it must be writable by the currently selected MEM-AP. + * @param addrinc Whether the target address should be increased for each write or not. This + * should normally be true, except when writing to e.g. a FIFO. + * @return ERROR_OK on success, otherwise an error code. + */ +static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, + uint32_t address, bool addrinc) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value ); + struct adiv5_dap *dap = ap->dap; + size_t nbytes = size * count; + const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; + uint32_t csw_size; + uint32_t addr_xor; + int retval = ERROR_OK; - return ERROR_OK; -} + /* TI BE-32 Quirks mode: + * Writes on big-endian TMS570 behave very strangely. Observed behavior: + * size write address bytes written in order + * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val) + * 2 TAR ^ 2 (val >> 8), (val) + * 1 TAR ^ 3 (val) + * For example, if you attempt to write a single byte to address 0, the processor + * will actually write a byte to address 3. + * + * To make writes of size < 4 work as expected, we xor a value with the address before + * setting the TAP, and we set the TAP after every transfer rather then relying on + * address increment. */ + + if (size == 4) { + csw_size = CSW_32BIT; + addr_xor = 0; + } else if (size == 2) { + csw_size = CSW_16BIT; + addr_xor = dap->ti_be_32_quirks ? 2 : 0; + } else if (size == 1) { + csw_size = CSW_8BIT; + addr_xor = dap->ti_be_32_quirks ? 3 : 0; + } else { + return ERROR_TARGET_UNALIGNED_ACCESS; + } -int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value) -{ - mem_ap_write_u32(swjdp, address, value); + if (ap->unaligned_access_bad && (address % size != 0)) + return ERROR_TARGET_UNALIGNED_ACCESS; - return swjdp_transaction_endcheck(swjdp); -} + while (nbytes > 0) { + uint32_t this_size = size; -/***************************************************************************** -* * -* mem_ap_write_buf(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) * -* * -* Write a buffer in target order (little endian) * -* * -*****************************************************************************/ -int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) -{ - int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; - uint32_t adr = address; - uint8_t* pBuffer = buffer; + /* Select packed transfer if possible */ + if (addrinc && ap->packed_transfers && nbytes >= 4 + && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { + this_size = 4; + retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED); + } else { + retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr); + } - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + if (retval != ERROR_OK) + break; - count >>= 2; - wcount = count; + retval = mem_ap_setup_tar(ap, address ^ addr_xor); + if (retval != ERROR_OK) + return retval; - /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (writecount = 0; writecount < count; writecount++) - { - int i; - uint32_t outvalue; - memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - - for (i = 0; i < 4; i++ ) - { - *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; - outvalue >>= 8; - adr++; + /* How many source bytes each transfer will consume, and their location in the DRW, + * depends on the type of transfer and alignment. See ARM document IHI0031C. */ + uint32_t outvalue = 0; + uint32_t drw_byte_idx = address; + if (dap->ti_be_32_quirks) { + switch (this_size) { + case 4: + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor); + break; + case 2: + outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor); + break; + case 1: + outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor); + break; + } + } else { + switch (this_size) { + case 4: + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); + /* fallthrough */ + case 2: + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); + /* fallthrough */ + case 1: + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3); } - pBuffer += sizeof(uint32_t); } - } - while (wcount > 0) - { - /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); - if (wcount < blocksize) - blocksize = wcount; + nbytes -= this_size; - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; + retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + mem_ap_update_tar_cache(ap); + if (addrinc) + address += this_size; + } - for (writecount = 0; writecount < blocksize; writecount++) - { - dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount ); - } + /* REVISIT: Might want to have a queued version of this function that does not run. */ + if (retval == ERROR_OK) + retval = dap_run(dap); - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) - { - wcount = wcount - blocksize; - address = address + 4 * blocksize; - buffer = buffer + 4 * blocksize; - } + if (retval != ERROR_OK) { + uint32_t tar; + if (mem_ap_read_tar(ap, &tar) == ERROR_OK) + LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar); else - { - errorcount++; - } - - if (errorcount > 1) - { - LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); - return ERROR_JTAG_DEVICE_ERROR; - } + LOG_ERROR("Failed to write memory and, additionally, failed to find out where"); } return retval; } -int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Synchronous read of a block of memory, using a specific access size. + * + * @param ap The MEM-AP to access. + * @param buffer The data buffer to receive the data. No particular alignment is assumed. + * @param size Which access size to use, in bytes. 1, 2 or 4. + * @param count The number of reads to do (in size units, not bytes). + * @param address Address to be read; it must be readable by the currently selected MEM-AP. + * @param addrinc Whether the target address should be increased after each read or not. This + * should normally be true, except when reading from e.g. a FIFO. + * @return ERROR_OK on success, otherwise an error code. + */ +static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, + uint32_t adr, bool addrinc) { + struct adiv5_dap *dap = ap->dap; + size_t nbytes = size * count; + const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; + uint32_t csw_size; + uint32_t address = adr; int retval = ERROR_OK; - int wcount, blocksize, writecount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + /* TI BE-32 Quirks mode: + * Reads on big-endian TMS570 behave strangely differently than writes. + * They read from the physical address requested, but with DRW byte-reversed. + * For example, a byte read from address 0 will place the result in the high bytes of DRW. + * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes, + * so avoid them. */ + + if (size == 4) + csw_size = CSW_32BIT; + else if (size == 2) + csw_size = CSW_16BIT; + else if (size == 1) + csw_size = CSW_8BIT; + else + return ERROR_TARGET_UNALIGNED_ACCESS; + + if (ap->unaligned_access_bad && (adr % size != 0)) + return ERROR_TARGET_UNALIGNED_ACCESS; + + /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant + * over-allocation if packed transfers are going to be used, but determining the real need at + * this point would be messy. */ + uint32_t *read_buf = calloc(count, sizeof(uint32_t)); + /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */ + uint32_t *read_ptr = read_buf; + if (read_buf == NULL) { + LOG_ERROR("Failed to allocate read buffer"); + return ERROR_FAIL; + } - wcount = count >> 1; + /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many + * useful bytes it contains, and their location in the word, depends on the type of transfer + * and alignment. */ + while (nbytes > 0) { + uint32_t this_size = size; + + /* Select packed transfer if possible */ + if (addrinc && ap->packed_transfers && nbytes >= 4 + && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { + this_size = 4; + retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED); + } else { + retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr); + } + if (retval != ERROR_OK) + break; - while (wcount > 0) - { - int nbytes; + retval = mem_ap_setup_tar(ap, address); + if (retval != ERROR_OK) + break; - /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++); + if (retval != ERROR_OK) + break; - if (wcount < blocksize) - blocksize = wcount; + nbytes -= this_size; + if (addrinc) + address += this_size; - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; + mem_ap_update_tar_cache(ap); + } - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); - writecount = blocksize; + if (retval == ERROR_OK) + retval = dap_run(dap); + + /* Restore state */ + address = adr; + nbytes = size * count; + read_ptr = read_buf; + + /* If something failed, read TAR to find out how much data was successfully read, so we can + * at least give the caller what we have. */ + if (retval != ERROR_OK) { + uint32_t tar; + if (mem_ap_read_tar(ap, &tar) == ERROR_OK) { + /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */ + LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar); + if (nbytes > tar - address) + nbytes = tar - address; + } else { + LOG_ERROR("Failed to read memory and, additionally, failed to find out where"); + nbytes = 0; + } + } - do - { - nbytes = MIN((writecount << 1), 4); + /* Replay loop to populate caller's buffer from the correct word and byte lane */ + while (nbytes > 0) { + uint32_t this_size = size; - if (nbytes < 4 ) - { - if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } + if (addrinc && ap->packed_transfers && nbytes >= 4 + && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { + this_size = 4; + } - address += nbytes >> 1; + if (dap->ti_be_32_quirks) { + switch (this_size) { + case 4: + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); + /* fallthrough */ + case 2: + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); + /* fallthrough */ + case 1: + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); } - else - { - uint32_t outvalue; - memcpy(&outvalue, buffer, sizeof(uint32_t)); - - for (i = 0; i < nbytes; i++ ) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; - outvalue >>= 8; - address++; - } - - memcpy(&outvalue, buffer, sizeof(uint32_t)); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } + } else { + switch (this_size) { + case 4: + *buffer++ = *read_ptr >> 8 * (address++ & 3); + *buffer++ = *read_ptr >> 8 * (address++ & 3); + /* fallthrough */ + case 2: + *buffer++ = *read_ptr >> 8 * (address++ & 3); + /* fallthrough */ + case 1: + *buffer++ = *read_ptr >> 8 * (address++ & 3); } + } - buffer += nbytes >> 1; - writecount -= nbytes >> 1; - - } while (writecount); - wcount -= blocksize; + read_ptr++; + nbytes -= this_size; } + free(read_buf); return retval; } -int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf(struct adiv5_ap *ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) { - int retval = ERROR_OK; - - if (count >= 4) - return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - uint16_t svalue; - memcpy(&svalue, buffer, sizeof(uint16_t)); - uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); - retval = swjdp_transaction_endcheck(swjdp); - count -= 2; - address += 2; - buffer += 2; - } - - return retval; + return mem_ap_read(ap, buffer, size, count, address, true); } -int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf(struct adiv5_ap *ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) { - int retval = ERROR_OK; - int wcount, blocksize, writecount, i; - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - wcount = count; - - while (wcount > 0) - { - int nbytes; + return mem_ap_write(ap, buffer, size, count, address, true); +} - /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); +int mem_ap_read_buf_noincr(struct adiv5_ap *ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) +{ + return mem_ap_read(ap, buffer, size, count, address, false); +} - if (wcount < blocksize) - blocksize = wcount; +int mem_ap_write_buf_noincr(struct adiv5_ap *ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) +{ + return mem_ap_write(ap, buffer, size, count, address, false); +} - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); - writecount = blocksize; +/*--------------------------------------------------------------------------*/ - do - { - nbytes = MIN(writecount, 4); - if (nbytes < 4 ) - { - if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } +#define DAP_POWER_DOMAIN_TIMEOUT (10) - address += nbytes; - } - else - { - uint32_t outvalue; - memcpy(&outvalue, buffer, sizeof(uint32_t)); - - for (i = 0; i < nbytes; i++ ) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; - outvalue >>= 8; - address++; - } - - memcpy(&outvalue, buffer, sizeof(uint32_t)); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } - } +/* FIXME don't import ... just initialize as + * part of DAP transport setup +*/ +extern const struct dap_ops jtag_dp_ops; - buffer += nbytes; - writecount -= nbytes; +/*--------------------------------------------------------------------------*/ - } while (writecount); - wcount -= blocksize; +/** + * Create a new DAP + */ +struct adiv5_dap *dap_init(void) +{ + struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap)); + int i; + /* Set up with safe defaults */ + for (i = 0; i <= 255; i++) { + dap->ap[i].dap = dap; + dap->ap[i].ap_num = i; + /* memaccess_tck max is 255 */ + dap->ap[i].memaccess_tck = 255; + /* Number of bits for tar autoincrement, impl. dep. at least 10 */ + dap->ap[i].tar_autoincr_block = (1<<10); } - - return retval; + INIT_LIST_HEAD(&dap->cmd_journal); + return dap; } -int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Invalidate cached DP select and cached TAR and CSW of all APs + */ +void dap_invalidate_cache(struct adiv5_dap *dap) { - int retval = ERROR_OK; - - if (count >= 4) - return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address); - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue ); - retval = swjdp_transaction_endcheck(swjdp); - count--; - address++; - buffer++; + dap->select = DP_SELECT_INVALID; + dap->last_read = NULL; + + int i; + for (i = 0; i <= 255; i++) { + /* force csw and tar write on the next mem-ap access */ + dap->ap[i].tar_valid = false; + dap->ap[i].csw_value = 0; } - - return retval; } -/********************************************************************************* -* * -* mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) * -* * -* Read block fast in target order (little endian) into a buffer * -* * -**********************************************************************************/ -int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Initialize a DAP. This sets up the power domains, prepares the DP + * for further use and activates overrun checking. + * + * @param dap The DAP being initialized. + */ +int dap_dp_init(struct adiv5_dap *dap) { - int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; - uint32_t adr = address; - uint8_t* pBuffer = buffer; - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + int retval; - count >>= 2; - wcount = count; + LOG_DEBUG(" "); + /* JTAG-DP or SWJ-DP, in JTAG mode + * ... for SWD mode this is patched as part + * of link switchover + * FIXME: This should already be setup by the respective transport specific DAP creation. + */ + if (!dap->ops) + dap->ops = &jtag_dp_ops; - while (wcount > 0) - { - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); - if (wcount < blocksize) - blocksize = wcount; - - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; - - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); - - /* Scan out first read */ - adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL); - for (readcount = 0; readcount < blocksize - 1; readcount++) - { - /* Scan out read instruction and scan in previous value */ - adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); - } + dap_invalidate_cache(dap); - /* Scan in last value */ - adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) - { - wcount = wcount - blocksize; - address += 4 * blocksize; - buffer += 4 * blocksize; - } - else - { - errorcount++; - } + for (size_t i = 0; i < 30; i++) { + /* DP initialization */ - if (errorcount > 1) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } + retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL); + if (retval == ERROR_OK) + break; } - /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (readcount = 0; readcount < count; readcount++) - { - int i; - uint32_t data; - memcpy(&data, pBuffer, sizeof(uint32_t)); - - for (i = 0; i < 4; i++ ) - { - *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3)); - pBuffer++; - adr++; - } - } - } + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR); + if (retval != ERROR_OK) + return retval; + + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; + + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; + + /* Check that we have debug power domains activated */ + LOG_DEBUG("DAP: wait CDBGPWRUPACK"); + retval = dap_dp_poll_register(dap, DP_CTRL_STAT, + CDBGPWRUPACK, CDBGPWRUPACK, + DAP_POWER_DOMAIN_TIMEOUT); + if (retval != ERROR_OK) + return retval; + + LOG_DEBUG("DAP: wait CSYSPWRUPACK"); + retval = dap_dp_poll_register(dap, DP_CTRL_STAT, + CSYSPWRUPACK, CSYSPWRUPACK, + DAP_POWER_DOMAIN_TIMEOUT); + if (retval != ERROR_OK) + return retval; + + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; + + /* With debug power on we can activate OVERRUN checking */ + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; + + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; return retval; } -int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Initialize a DAP. This sets up the power domains, prepares the DP + * for further use, and arranges to use AP #0 for all AP operations + * until dap_ap-select() changes that policy. + * + * @param ap The MEM-AP being initialized. + */ +int mem_ap_init(struct adiv5_ap *ap) { - uint32_t invalue; - int retval = ERROR_OK; - int wcount, blocksize, readcount, i; + /* check that we support packed transfers */ + uint32_t csw, cfg; + int retval; + struct adiv5_dap *dap = ap->dap; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + ap->tar_valid = false; + ap->csw_value = 0; /* force csw and tar write */ + retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0); + if (retval != ERROR_OK) + return retval; - wcount = count >> 1; + retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw); + if (retval != ERROR_OK) + return retval; - while (wcount > 0) - { - int nbytes; - - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); - if (wcount < blocksize) - blocksize = wcount; - - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); - - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; - readcount = blocksize; - - do - { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; - } + retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg); + if (retval != ERROR_OK) + return retval; - nbytes = MIN((readcount << 1), 4); + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - for (i = 0; i < nbytes; i++ ) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); - buffer++; - address++; - } + if (csw & CSW_ADDRINC_PACKED) + ap->packed_transfers = true; + else + ap->packed_transfers = false; - readcount -= (nbytes >> 1); - } while (readcount); - wcount -= blocksize; - } + /* Packed transfers on TI BE-32 processors do not work correctly in + * many cases. */ + if (dap->ti_be_32_quirks) + ap->packed_transfers = false; - return retval; + LOG_DEBUG("MEM_AP Packed Transfers: %s", + ap->packed_transfers ? "enabled" : "disabled"); + + /* The ARM ADI spec leaves implementation-defined whether unaligned + * memory accesses work, only work partially, or cause a sticky error. + * On TI BE-32 processors, reads seem to return garbage in some bytes + * and unaligned writes seem to cause a sticky error. + * TODO: it would be nice to have a way to detect whether unaligned + * operations are supported on other processors. */ + ap->unaligned_access_bad = dap->ti_be_32_quirks; + + LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d", + !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01)); + + return ERROR_OK; } -int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +/* CID interpretation -- see ARM IHI 0029B section 3 + * and ARM IHI 0031A table 13-3. + */ +static const char *class_description[16] = { + "Reserved", "ROM table", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", + "Reserved", "OptimoDE DESS", + "Generic IP component", "PrimeCell or System component" +}; + +static bool is_dap_cid_ok(uint32_t cid) { - uint32_t invalue, i; - int retval = ERROR_OK; + return (cid & 0xffff0fff) == 0xb105000d; +} - if (count >= 4) - return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address); +/* + * This function checks the ID for each access port to find the requested Access Port type + */ +int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out) +{ + int ap_num; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + /* Maximum AP number is 255 since the SELECT register is 8 bits */ + for (ap_num = 0; ap_num <= 255; ap_num++) { - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); - retval = swjdp_transaction_endcheck(swjdp); - if (address & 0x1) - { - for (i = 0; i < 2; i++ ) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); - buffer++; - address++; - } - } - else - { - uint16_t svalue = (invalue >> 8 * (address & 0x3)); - memcpy(buffer, &svalue, sizeof(uint16_t)); - address += 2; - buffer += 2; + /* read the IDR register of the Access Port */ + uint32_t id_val = 0; + + int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val); + if (retval != ERROR_OK) + return retval; + + retval = dap_run(dap); + + /* IDR bits: + * 31-28 : Revision + * 27-24 : JEDEC bank (0x4 for ARM) + * 23-17 : JEDEC code (0x3B for ARM) + * 16-13 : Class (0b1000=Mem-AP) + * 12-8 : Reserved + * 7-4 : AP Variant (non-zero for JTAG-AP) + * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP) + */ + + /* Reading register for a non-existant AP should not cause an error, + * but just to be sure, try to continue searching if an error does happen. + */ + if ((retval == ERROR_OK) && /* Register read success */ + ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */ + ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/ + + LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")", + (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" : + (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" : + (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" : + (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown", + ap_num, id_val); + + *ap_out = &dap->ap[ap_num]; + return ERROR_OK; } - count -= 2; } - return retval; + LOG_DEBUG("No %s found", + (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" : + (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" : + (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" : + (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown"); + return ERROR_FAIL; } -/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many - * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? - * - * The solution is to arrange for a large out/in scan in this loop and - * and convert data afterwards. - */ -int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +int dap_get_debugbase(struct adiv5_ap *ap, + uint32_t *dbgbase, uint32_t *apid) { - uint32_t invalue; - int retval = ERROR_OK; - int wcount, blocksize, readcount, i; + struct adiv5_dap *dap = ap->dap; + int retval; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(ap, AP_REG_IDR, apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - wcount = count; + return ERROR_OK; +} - while (wcount > 0) - { - int nbytes; +int dap_lookup_cs_component(struct adiv5_ap *ap, + uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx) +{ + uint32_t romentry, entry_offset = 0, component_base, devtype; + int retval; - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + *addr = 0; - if (wcount < blocksize) - blocksize = wcount; + do { + retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | + entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); - readcount = blocksize; + component_base = (dbgbase & 0xFFFFF000) + + (romentry & 0xFFFFF000); - do - { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + if (romentry & 0x1) { + uint32_t c_cid1; + retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1); + if (retval != ERROR_OK) { + LOG_ERROR("Can't read component with base address 0x%" PRIx32 + ", the corresponding core might be turned off", component_base); + return retval; + } + if (((c_cid1 >> 4) & 0x0f) == 1) { + retval = dap_lookup_cs_component(ap, component_base, + type, addr, idx); + if (retval == ERROR_OK) + break; + if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) + return retval; } - nbytes = MIN(readcount, 4); - - for (i = 0; i < nbytes; i++ ) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); - buffer++; - address++; + retval = mem_ap_read_atomic_u32(ap, + (component_base & 0xfffff000) | 0xfcc, + &devtype); + if (retval != ERROR_OK) + return retval; + if ((devtype & 0xff) == type) { + if (!*idx) { + *addr = component_base; + break; + } else + (*idx)--; } + } + entry_offset += 4; + } while (romentry > 0); - readcount -= nbytes; - } while (readcount); - wcount -= blocksize; - } + if (!*addr) + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - return retval; + return ERROR_OK; } -int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32_t address) +static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid) { - uint32_t invalue; - int retval = ERROR_OK; + assert((component_base & 0xFFF) == 0); + assert(ap != NULL && cid != NULL && pid != NULL); - if (count >= 4) - return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address); + uint32_t cid0, cid1, cid2, cid3; + uint32_t pid0, pid1, pid2, pid3, pid4; + int retval; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + /* IDs are in last 4K section */ + retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3); + if (retval != ERROR_OK) + return retval; - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue ); - retval = swjdp_transaction_endcheck(swjdp); - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); - count--; - address++; - buffer++; - } + retval = dap_run(ap->dap); + if (retval != ERROR_OK) + return retval; - return retval; + *cid = (cid3 & 0xff) << 24 + | (cid2 & 0xff) << 16 + | (cid1 & 0xff) << 8 + | (cid0 & 0xff); + *pid = (uint64_t)(pid4 & 0xff) << 32 + | (pid3 & 0xff) << 24 + | (pid2 & 0xff) << 16 + | (pid1 & 0xff) << 8 + | (pid0 & 0xff); + + return ERROR_OK; } -int ahbap_debugport_init(swjdp_common_t *swjdp) +/* The designer identity code is encoded as: + * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1. + * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent + * a legacy ASCII Identity Code. + * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7. + * JEP106 is a standard available from jedec.org + */ + +/* Part number interpretations are from Cortex + * core specs, the CoreSight components TRM + * (ARM DDI 0314H), CoreSight System Design + * Guide (ARM DGI 0012D) and ETM specs; also + * from chip observation (e.g. TI SDTI). + */ + +/* The legacy code only used the part number field to identify CoreSight peripherals. + * This meant that the same part number from two different manufacturers looked the same. + * It is desirable for all future additions to identify with both part number and JEP106. + * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries. + */ + +#define ANY_ID 0x1000 + +#define ARM_ID 0x4BB + +static const struct { + uint16_t designer_id; + uint16_t part_num; + const char *type; + const char *full; +} dap_partnums[] = { + { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", }, + { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", }, + { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", }, + { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", }, + { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", }, + { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", }, + { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", }, + { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", }, + { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", }, + { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", }, + { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", }, + { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", }, + { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", }, + { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", }, + { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", }, + { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", }, + { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", }, + { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", }, + { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", }, + { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", }, + { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", }, + { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", }, + { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", }, + { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", }, + { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", }, + { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", }, + { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", }, + { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", }, + { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", }, + { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", }, + { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", }, + { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", }, + { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", }, + { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", }, + { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", }, + { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", }, + { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", }, + { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", }, + { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", }, + { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", }, + { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", }, + { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, + { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" }, + { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" }, + { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" }, + { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" }, + { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" }, + { 0x0E5, 0x000, "SHARC+/Blackfin+", "", }, + { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, + { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", }, + { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, + { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", }, + { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", }, + { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", }, + /* legacy comment: 0x113: what? */ + { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */ + { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */ +}; + +static int dap_rom_display(struct command_context *cmd_ctx, + struct adiv5_ap *ap, uint32_t dbgbase, int depth) { - uint32_t idreg, romaddr, dummy; - uint32_t ctrlstat; - int cnt = 0; int retval; + uint64_t pid; + uint32_t cid; + char tabs[16] = ""; - LOG_DEBUG(" "); + if (depth > 16) { + command_print(cmd_ctx, "\tTables too deep"); + return ERROR_FAIL; + } - swjdp->apsel = 0; - swjdp->ap_csw_value = -1; - swjdp->ap_tar_value = -1; - swjdp->trans_mode = TRANS_MODE_ATOMIC; - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); + if (depth) + snprintf(tabs, sizeof(tabs), "[L%02d] ", depth); - swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + uint32_t base_addr = dbgbase & 0xFFFFF000; + command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr); - dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; + retval = dap_read_part_id(ap, base_addr, &cid, &pid); + if (retval != ERROR_OK) { + command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off"); + return ERROR_OK; /* Don't abort recursion */ + } - /* Check that we have debug power domains activated */ - while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) - { - LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - alive_sleep(10); + if (!is_dap_cid_ok(cid)) { + command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid); + return ERROR_OK; /* Don't abort recursion */ } - while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) - { - LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval=jtag_execute_queue())!=ERROR_OK) - return retval; - alive_sleep(10); + /* component may take multiple 4K pages */ + uint32_t size = (pid >> 36) & 0xf; + if (size > 0) + command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size)); + + command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid); + + uint8_t class = (cid >> 12) & 0xf; + uint16_t part_num = pid & 0xfff; + uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff); + + if (designer_id & 0x80) { + /* JEP106 code */ + command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s", + designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f)); + } else { + /* Legacy ASCII ID, clear invalid bits */ + designer_id &= 0x7f; + command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s", + designer_id, designer_id == 0x41 ? "ARM" : ""); } - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - /* With debug power on we can activate OVERRUN checking */ - swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; - dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); + /* default values to be overwritten upon finding a match */ + const char *type = "Unrecognized"; + const char *full = ""; - dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); - dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr); + /* search dap_partnums[] array for a match */ + for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) { - LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr); + if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID)) + continue; - return ERROR_OK; -} + if (dap_partnums[entry].part_num != part_num) + continue; + type = dap_partnums[entry].type; + full = dap_partnums[entry].full; + break; + } -char * class_description[16] ={ - "Reserved", - "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved", - "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"}; + command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full); + command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]); -int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel) -{ + if (class == 1) { /* ROM Table */ + uint32_t memtype; + retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype); + if (retval != ERROR_OK) + return retval; - uint32_t dbgbase,apid; - int romtable_present = 0; - uint8_t mem_ap; - uint32_t apselold; + if (memtype & 0x01) + command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus"); + else + command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus"); - apselold = swjdp->apsel; - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - swjdp_transaction_endcheck(swjdp); - /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0)); - command_print(cmd_ctx, "ap identification register 0x%8.8x", apid); - if (apid) - { - switch (apid&0x0F) - { + /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */ + for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) { + uint32_t romentry; + retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; + command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "", + tabs, entry_offset, romentry); + if (romentry & 0x01) { + /* Recurse */ + retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1); + if (retval != ERROR_OK) + return retval; + } else if (romentry != 0) { + command_print(cmd_ctx, "\t\tComponent not present"); + } else { + command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs); + break; + } + } + } else if (class == 9) { /* CoreSight component */ + const char *major = "Reserved", *subtype = "Reserved"; + + uint32_t devtype; + retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype); + if (retval != ERROR_OK) + return retval; + unsigned minor = (devtype >> 4) & 0x0f; + switch (devtype & 0x0f) { + case 0: + major = "Miscellaneous"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 4: + subtype = "Validation component"; + break; + } + break; + case 1: + major = "Trace Sink"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Port"; + break; + case 2: + subtype = "Buffer"; + break; + case 3: + subtype = "Router"; + break; + } + break; + case 2: + major = "Trace Link"; + switch (minor) { case 0: - command_print(cmd_ctx, "\tType is jtag-ap"); + subtype = "other"; break; case 1: - command_print(cmd_ctx, "\tType is mem-ap AHB"); + subtype = "Funnel, router"; break; case 2: - command_print(cmd_ctx, "\tType is mem-ap APB"); + subtype = "Filter"; + break; + case 3: + subtype = "FIFO, buffer"; break; - default: - command_print(cmd_ctx, "\tUnknown AP-type"); + } + break; + case 3: + major = "Trace Source"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + case 6: + subtype = "Software"; + break; + } + break; + case 4: + major = "Debug Control"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Trigger Matrix"; + break; + case 2: + subtype = "Debug Auth"; + break; + case 3: + subtype = "Power Requestor"; + break; + } + break; + case 5: + major = "Debug Logic"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + case 5: + subtype = "Memory"; + break; + } + break; + case 6: + major = "Perfomance Monitor"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + case 5: + subtype = "Memory"; + break; + } break; } - command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase); + command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s", + (uint8_t)(devtype & 0xff), + major, subtype); + /* REVISIT also show 0xfc8 DevId */ } - else - { - command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel); + + return ERROR_OK; +} + +static int dap_info_command(struct command_context *cmd_ctx, + struct adiv5_ap *ap) +{ + int retval; + uint32_t dbgbase, apid; + uint8_t mem_ap; + + /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ + retval = dap_get_debugbase(ap, &dbgbase, &apid); + if (retval != ERROR_OK) + return retval; + + command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); + if (apid == 0) { + command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num); + return ERROR_FAIL; } - romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF)); - if (romtable_present) - { - uint32_t cid0,cid1,cid2,cid3,memtype,romentry; - uint16_t entry_offset; - /* bit 16 of apid indicates a memory access port */ - if (dbgbase&0x02) - { - command_print(cmd_ctx, "\tValid ROM table present"); - } - else - { - command_print(cmd_ctx, "\tROM table in legacy format" ); - } - /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype); - swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0); - if (memtype&0x01) - { - command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); - } - else - { - command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" ); - } + switch (apid & (IDR_JEP106 | IDR_TYPE)) { + case IDR_JEP106_ARM | AP_TYPE_JTAG_AP: + command_print(cmd_ctx, "\tType is JTAG-AP"); + break; + case IDR_JEP106_ARM | AP_TYPE_AHB_AP: + command_print(cmd_ctx, "\tType is MEM-AP AHB"); + break; + case IDR_JEP106_ARM | AP_TYPE_APB_AP: + command_print(cmd_ctx, "\tType is MEM-AP APB"); + break; + case IDR_JEP106_ARM | AP_TYPE_AXI_AP: + command_print(cmd_ctx, "\tType is MEM-AP AXI"); + break; + default: + command_print(cmd_ctx, "\tUnknown AP type"); + break; + } - /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */ - entry_offset = 0; - do - { - mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry); - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry); - if (romentry&0x01) - { - uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start; - uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000)); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2); - mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4>>4); - command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start); - command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */ - command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0); - command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0); - /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */ - } + /* NOTE: a MEM-AP may have a single CoreSight component that's + * not a ROM table ... or have no such components at all. + */ + mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP; + if (mem_ap) { + command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase); + + if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) { + command_print(cmd_ctx, "\tNo ROM table present"); + } else { + if (dbgbase & 0x01) + command_print(cmd_ctx, "\tValid ROM table present"); else - { - if (romentry) - command_print(cmd_ctx, "\t\tComponent not present"); - else - command_print(cmd_ctx, "\t\tEnd of ROM table"); - } - entry_offset += 4; - } while (romentry>0); + command_print(cmd_ctx, "\tROM table in legacy format"); + + dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0); + } } - else - { - command_print(cmd_ctx, "\tNo ROM table present"); + + return ERROR_OK; +} + +int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi) +{ + struct adiv5_private_config *pc; + const char *arg; + jim_wide ap_num; + int e; + + /* check if argv[0] is for us */ + arg = Jim_GetString(goi->argv[0], NULL); + if (strcmp(arg, "-ap-num")) + return JIM_CONTINUE; + + e = Jim_GetOpt_String(goi, &arg, NULL); + if (e != JIM_OK) + return e; + + if (goi->argc == 0) { + Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ..."); + return JIM_ERR; + } + + e = Jim_GetOpt_Wide(goi, &ap_num); + if (e != JIM_OK) + return e; + + if (target->private_config == NULL) { + pc = calloc(1, sizeof(struct adiv5_private_config)); + target->private_config = pc; + pc->ap_num = ap_num; + } + + + return JIM_OK; +} + +COMMAND_HANDLER(handle_dap_info_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel; + + switch (CMD_ARGC) { + case 0: + apsel = dap->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + return dap_info_command(CMD_CTX, &dap->ap[apsel]); +} + +COMMAND_HANDLER(dap_baseaddr_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apsel, baseaddr; + int retval; + + switch (CMD_ARGC) { + case 0: + apsel = dap->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } - dap_ap_select(swjdp, apselold); + + /* NOTE: assumes we're talking to a MEM-AP, which + * has a base address. There are other kinds of AP, + * though they're not common for now. This should + * use the ID register to verify it's a MEM-AP. + */ + retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + + command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr); + + return retval; +} + +COMMAND_HANDLER(dap_memaccess_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t memaccess_tck; + + switch (CMD_ARGC) { + case 0: + memaccess_tck = dap->ap[dap->apsel].memaccess_tck; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + dap->ap[dap->apsel].memaccess_tck = memaccess_tck; + + command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck", + dap->ap[dap->apsel].memaccess_tck); return ERROR_OK; } +COMMAND_HANDLER(dap_apsel_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apsel, apid; + int retval; + + switch (CMD_ARGC) { + case 0: + apsel = dap->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + dap->apsel = apsel; + + retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + + command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, + apsel, apid); + + return retval; +} + +COMMAND_HANDLER(dap_apcsw_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0; + + switch (CMD_ARGC) { + case 0: + command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32, + (dap->apsel), apcsw); + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot); + /* AP address is in bits 31:24 of DP_SELECT */ + if (sprot > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + if (sprot) + apcsw |= CSW_SPROT; + else + apcsw &= ~CSW_SPROT; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + dap->ap[dap->apsel].csw_default = apcsw; + + return 0; +} + + + +COMMAND_HANDLER(dap_apid_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apsel, apid; + int retval; + + switch (CMD_ARGC) { + case 0: + apsel = dap->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + + command_print(CMD_CTX, "0x%8.8" PRIx32, apid); + + return retval; +} + +COMMAND_HANDLER(dap_apreg_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apsel, reg, value; + int retval; + + if (CMD_ARGC < 2 || CMD_ARGC > 3) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg); + if (reg >= 256 || (reg & 3)) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 3) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); + retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value); + } else { + retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value); + } + if (retval == ERROR_OK) + retval = dap_run(dap); + + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC == 2) + command_print(CMD_CTX, "0x%08" PRIx32, value); + + return retval; +} + +COMMAND_HANDLER(dap_ti_be_32_quirks_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t enable = dap->ti_be_32_quirks; + + switch (CMD_ARGC) { + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable); + if (enable > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + dap->ti_be_32_quirks = enable; + command_print(CMD_CTX, "TI BE-32 quirks mode %s", + enable ? "enabled" : "disabled"); + + return 0; +} + +static const struct command_registration dap_commands[] = { + { + .name = "info", + .handler = handle_dap_info_command, + .mode = COMMAND_EXEC, + .help = "display ROM table for MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "apsel", + .handler = dap_apsel_command, + .mode = COMMAND_EXEC, + .help = "Set the currently selected AP (default 0) " + "and display the result", + .usage = "[ap_num]", + }, + { + .name = "apcsw", + .handler = dap_apcsw_command, + .mode = COMMAND_EXEC, + .help = "Set csw access bit ", + .usage = "[sprot]", + }, + + { + .name = "apid", + .handler = dap_apid_command, + .mode = COMMAND_EXEC, + .help = "return ID register from AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "apreg", + .handler = dap_apreg_command, + .mode = COMMAND_EXEC, + .help = "read/write a register from AP " + "(reg is byte address of a word register, like 0 4 8...)", + .usage = "ap_num reg [value]", + }, + { + .name = "baseaddr", + .handler = dap_baseaddr_command, + .mode = COMMAND_EXEC, + .help = "return debug base address from MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "memaccess", + .handler = dap_memaccess_command, + .mode = COMMAND_EXEC, + .help = "set/get number of extra tck for MEM-AP memory " + "bus access [0-255]", + .usage = "[cycles]", + }, + { + .name = "ti_be_32_quirks", + .handler = dap_ti_be_32_quirks_command, + .mode = COMMAND_CONFIG, + .help = "set/get quirks mode for TI TMS450/TMS570 processors", + .usage = "[enable]", + }, + COMMAND_REGISTRATION_DONE +}; + +const struct command_registration dap_command_handlers[] = { + { + .name = "dap", + .mode = COMMAND_EXEC, + .help = "DAP command group", + .usage = "", + .chain = dap_commands, + }, + COMMAND_REGISTRATION_DONE +};