X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=9a98f61d5652bde9925fb5e726128f85123e11b5;hp=958844bb00bda1efde006ed27fd4dcc98c05d760;hb=7743e0fb4390d09c315ce9c6edbb2c3ba6b8c2d9;hpb=98723c4ecdbe06f90c66f3abec27b792c3b38e34 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 958844bb00..9a98f61d56 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -5,9 +5,11 @@ * Copyright (C) 2008 by Spencer Oliver * * spen@spen-soft.co.uk * * * - * Copyright (C) 2009 by Oyvind Harboe * + * Copyright (C) 2009-2010 by Oyvind Harboe * * oyvind.harboe@zylin.com * - * * + * * + * Copyright (C) 2009-2010 by David Brownell * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -23,35 +25,54 @@ * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * ***************************************************************************/ -/*************************************************************************** - * * - * This file implements support for the ARM Debug Interface v5 (ADI_V5) * - * * - * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A * - * * - * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D * - * Cortex-M3(tm) TRM, ARM DDI 0337G * - * * -***************************************************************************/ + +/** + * @file + * This file implements support for the ARM Debug Interface version 5 (ADIv5) + * debugging architecture. Compared with previous versions, this includes + * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message + * transport, and focusses on memory mapped resources as defined by the + * CoreSight architecture. + * + * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two + * basic components: a Debug Port (DP) transporting messages to and from a + * debugger, and an Access Port (AP) accessing resources. Three types of DP + * are defined. One uses only JTAG for communication, and is called JTAG-DP. + * One uses only SWD for communication, and is called SW-DP. The third can + * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP + * is used to access memory mapped resources and is called a MEM-AP. Also a + * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon. + * + * This programming interface allows DAP pipelined operations through a + * transaction queue. This primarily affects AP operations (such as using + * a MEM-AP to access memory or registers). If the current transaction has + * not finished by the time the next one must begin, and the ORUNDETECT bit + * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and + * further AP operations will fail. There are two basic methods to avoid + * such overrun errors. One involves polling for status instead of using + * transaction piplining. The other involves adding delays to ensure the + * AP has enough time to complete one operation before starting the next + * one. (For JTAG these delays are controlled by memaccess_tck.) + */ + +/* + * Relevant specifications from ARM include: + * + * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A + * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B + * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D + * Cortex-M3(tm) TRM, ARM DDI 0337G + */ #ifdef HAVE_CONFIG_H #include "config.h" #endif +#include "jtag/interface.h" +#include "arm.h" #include "arm_adi_v5.h" -#include "time_support.h" - -/* - * Transaction Mode: - * swjdp->trans_mode = TRANS_MODE_COMPOSITE; - * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction - * result checking until swjdp_end_transaction() - * This must be done before using or deallocating any return variables. - * swjdp->trans_mode == TRANS_MODE_ATOMIC - * All reads and writes to the AHB bus are checked for valid completion, and return values - * are immediatley available. -*/ - +#include /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ @@ -66,410 +87,204 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address /*************************************************************************** * * - * DPACC and APACC scanchain access through JTAG-DP * + * DP and MEM-AP register access through APACC and DPACC * * * ***************************************************************************/ -/* Scan out and in from target ordered uint8_t buffers */ -int adi_jtag_dp_scan(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue, uint8_t *ack) -{ - struct arm_jtag *jtag_info = swjdp->jtag_info; - struct scan_field fields[2]; - uint8_t out_addr_buf; - - jtag_set_end_state(TAP_IDLE); - arm_jtag_set_instr(jtag_info, instr, NULL); - - /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); - - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); - fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - fields[1].out_value = outvalue; - fields[1].in_value = invalue; - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - - return ERROR_OK; -} - -/* Scan out and in from host ordered uint32_t variables */ -int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue, uint8_t *ack) -{ - struct arm_jtag *jtag_info = swjdp->jtag_info; - struct scan_field fields[2]; - uint8_t out_value_buf[4]; - uint8_t out_addr_buf; - - jtag_set_end_state(TAP_IDLE); - arm_jtag_set_instr(jtag_info, instr, NULL); - - /* Add specified number of tck clocks before accessing memory bus */ - if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0)) - jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE)); - - fields[0].tap = jtag_info->tap; - fields[0].num_bits = 3; - buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1)); - fields[0].out_value = &out_addr_buf; - fields[0].in_value = ack; - - fields[1].tap = jtag_info->tap; - fields[1].num_bits = 32; - buf_set_u32(out_value_buf, 0, 32, outvalue); - fields[1].out_value = out_value_buf; - fields[1].in_value = NULL; - - if (invalue) - { - fields[1].in_value = (uint8_t *)invalue; - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - - jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue); - } else - { - - jtag_add_dr_scan(2, fields, jtag_get_end_state()); - } - - return ERROR_OK; -} - -/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ -int scan_inout_check(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint8_t *outvalue, uint8_t *invalue) +/** + * Select one of the APs connected to the specified DAP. The + * selection is implicitly used with future AP transactions. + * This is a NOP if the specified AP is already selected. + * + * @param dap The DAP + * @param apsel Number of the AP to (implicitly) use with further + * transactions. This normally identifies a MEM-AP. + */ +void dap_ap_select(struct adiv5_dap *dap, uint8_t ap) { - adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - - if ((RnW == DPAP_READ) && (invalue != NULL)) - { - adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - } - - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and the check CTRL_STAT */ - if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - { - return swjdp_transaction_endcheck(swjdp); + uint32_t new_ap = (ap << 24) & 0xFF000000; + + if (new_ap != dap->ap_current) { + dap->ap_current = new_ap; + /* Switching AP invalidates cached values. + * Values MUST BE UPDATED BEFORE AP ACCESS. + */ + dap->ap_bank_value = -1; + dap->ap_csw_value = -1; + dap->ap_tar_value = -1; } - - return ERROR_OK; } -int scan_inout_check_u32(struct swjdp_common *swjdp, uint8_t instr, uint8_t reg_addr, uint8_t RnW, uint32_t outvalue, uint32_t *invalue) -{ - adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL); - - if ((RnW == DPAP_READ) && (invalue != NULL)) - { - adi_jtag_dp_scan_u32(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); - } - - /* In TRANS_MODE_ATOMIC all DAP_IR_APACC transactions wait for ack = OK/FAULT and then check CTRL_STAT */ - if ((instr == DAP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) - { - return swjdp_transaction_endcheck(swjdp); - } - - return ERROR_OK; -} - -int swjdp_transaction_endcheck(struct swjdp_common *swjdp) +/** + * Queue transactions setting up transfer parameters for the + * currently selected MEM-AP. + * + * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2 + * initiate data reads or writes using memory or peripheral addresses. + * If the CSW is configured for it, the TAR may be automatically + * incremented after each transfer. + * + * @todo Rename to reflect it being specifically a MEM-AP function. + * + * @param dap The DAP connected to the MEM-AP. + * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this + * matches the cached value, the register is not changed. + * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this + * matches the cached address, the register is not changed. + * + * @return ERROR_OK if the transaction was properly queued, else a fault code. + */ +int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar) { int retval; - uint32_t ctrlstat; - - /* too expensive to call keep_alive() here */ - -#if 0 - /* Danger!!!! BROKEN!!!! */ - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? - R956 introduced the check on return value here and now Michael Schwingen reports - that this code no longer works.... - - https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html - */ - if ((retval = jtag_execute_queue()) != ERROR_OK) - { - LOG_ERROR("BUG: Why does this fail the first time????"); - } - /* Why??? second time it works??? */ -#endif - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - - swjdp->ack = swjdp->ack & 0x7; - - if (swjdp->ack != 2) - { - long long then = timeval_ms(); - while (swjdp->ack != 2) - { - if (swjdp->ack == 1) - { - if ((timeval_ms()-then) > 1000) - { - LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction"); - return ERROR_JTAG_DEVICE_ERROR; - } - } - else - { - LOG_WARNING("Invalid ACK in SWJDP transaction"); - return ERROR_JTAG_DEVICE_ERROR; - } - - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - swjdp->ack = swjdp->ack & 0x7; - } - } else - { - /* common code path avoids fn to timeval_ms() */ - } - - /* Check for STICKYERR and STICKYORUN */ - if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) - { - LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat); - /* Check power to debug regions */ - if ((ctrlstat & 0xf0000000) != 0xf0000000) - { - ahbap_debugport_init(swjdp); - } - else - { - uint32_t mem_ap_csw, mem_ap_tar; - - /* Print information about last AHBAP access */ - LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value); - if (ctrlstat & SSTICKYORUN) - LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); - - if (ctrlstat & SSTICKYERR) - LOG_ERROR("SWJ-DP STICKY ERROR"); - - /* Clear Sticky Error Bits */ - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); - scan_inout_check_u32(swjdp, DAP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - - LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat); - - dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw); - dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar); - if ((retval = jtag_execute_queue()) != ERROR_OK) - return retval; - LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar); - - } - if ((retval = jtag_execute_queue()) != ERROR_OK) + csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; + if (csw != dap->ap_csw_value) { + /* LOG_DEBUG("DAP: Set CSW %x",csw); */ + retval = dap_queue_ap_write(dap, AP_REG_CSW, csw); + if (retval != ERROR_OK) return retval; - return ERROR_JTAG_DEVICE_ERROR; + dap->ap_csw_value = csw; } - - return ERROR_OK; -} - -/*************************************************************************** - * * - * DP and MEM-AP register access through APACC and DPACC * - * * -***************************************************************************/ - -int dap_dp_write_reg(struct swjdp_common *swjdp, uint32_t value, uint8_t reg_addr) -{ - return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL); -} - -int dap_dp_read_reg(struct swjdp_common *swjdp, uint32_t *value, uint8_t reg_addr) -{ - return scan_inout_check_u32(swjdp, DAP_IR_DPACC, reg_addr, DPAP_READ, 0, value); -} - -int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel) -{ - uint32_t select; - select = (apsel << 24) & 0xFF000000; - - if (select != swjdp->apsel) - { - swjdp->apsel = select; - /* Switching AP invalidates cached values */ - swjdp->dp_select_value = -1; - swjdp->ap_csw_value = -1; - swjdp->ap_tar_value = -1; - } - - return ERROR_OK; -} - -int dap_dp_bankselect(struct swjdp_common *swjdp,uint32_t ap_reg) -{ - uint32_t select; - select = (ap_reg & 0x000000F0); - - if (select != swjdp->dp_select_value) - { - dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT); - swjdp->dp_select_value = select; + if (tar != dap->ap_tar_value) { + /* LOG_DEBUG("DAP: Set TAR %x",tar); */ + retval = dap_queue_ap_write(dap, AP_REG_TAR, tar); + if (retval != ERROR_OK) + return retval; + dap->ap_tar_value = tar; } - - return ERROR_OK; -} - -int dap_ap_write_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t* out_value_buf) -{ - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); - + /* Disable TAR cache when autoincrementing */ + if (csw & CSW_ADDRINC_MASK) + dap->ap_tar_value = -1; return ERROR_OK; } -int dap_ap_read_reg(struct swjdp_common *swjdp, uint32_t reg_addr, uint8_t *in_value_buf) -{ - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf); - - return ERROR_OK; -} -int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value) +/** + * Asynchronous (queued) read of a word from memory or a system register. + * + * @param dap The DAP connected to the MEM-AP performing the read. + * @param address Address of the 32-bit word to read; it must be + * readable by the currently selected MEM-AP. + * @param value points to where the word will be stored when the + * transaction queue is flushed (assuming no errors). + * + * @return ERROR_OK for success. Otherwise a fault code. + */ +int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t *value) { - uint8_t out_value_buf[4]; + int retval; - buf_set_u32(out_value_buf, 0, 32, value); - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check(swjdp, DAP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); + /* Use banked addressing (REG_BDx) to avoid some link traffic + * (updating TAR) when reading several consecutive addresses. + */ + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF, + address & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; - return ERROR_OK; + return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value); } -int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value) +/** + * Synchronous read of a word from memory or a system register. + * As a side effect, this flushes any queued transactions. + * + * @param dap The DAP connected to the MEM-AP performing the read. + * @param address Address of the 32-bit word to read; it must be + * readable by the currently selected MEM-AP. + * @param value points to where the result will be stored. + * + * @return ERROR_OK for success; *value holds the result. + * Otherwise a fault code. + */ +int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t *value) { - dap_dp_bankselect(swjdp, reg_addr); - scan_inout_check_u32(swjdp, DAP_IR_APACC, reg_addr, DPAP_READ, 0, value); - - return ERROR_OK; -} + int retval; -/*************************************************************************** - * * - * AHB-AP access to memory and system registers on AHB bus * - * * -***************************************************************************/ + retval = mem_ap_read_u32(dap, address, value); + if (retval != ERROR_OK) + return retval; -int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar) -{ - csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if (csw != swjdp->ap_csw_value) - { - /* LOG_DEBUG("swjdp : Set CSW %x",csw); */ - dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw); - swjdp->ap_csw_value = csw; - } - if (tar != swjdp->ap_tar_value) - { - /* LOG_DEBUG("swjdp : Set TAR %x",tar); */ - dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar); - swjdp->ap_tar_value = tar; - } - if (csw & CSW_ADDRINC_MASK) - { - /* Do not cache TAR value when autoincrementing */ - swjdp->ap_tar_value = -1; - } - return ERROR_OK; + return dap_run(dap); } -/***************************************************************************** -* * -* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) * -* * -* Read a uint32_t value from memory or system register * -* Functionally equivalent to target_read_u32(target, address, uint32_t *value), * -* but with less overhead * -*****************************************************************************/ -int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) +/** + * Asynchronous (queued) write of a word to memory or a system register. + * + * @param dap The DAP connected to the MEM-AP. + * @param address Address to be written; it must be writable by + * the currently selected MEM-AP. + * @param value Word that will be written to the address when transaction + * queue is flushed (assuming no errors). + * + * @return ERROR_OK for success. Otherwise a fault code. + */ +int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); - - return ERROR_OK; -} + int retval; -int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value) -{ - mem_ap_read_u32(swjdp, address, value); + /* Use banked addressing (REG_BDx) to avoid some link traffic + * (updating TAR) when writing several consecutive addresses. + */ + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF, + address & 0xFFFFFFF0); + if (retval != ERROR_OK) + return retval; - return swjdp_transaction_endcheck(swjdp); + return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC), + value); } -/***************************************************************************** -* * -* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) * -* * -* Write a uint32_t value to memory or memory mapped register * -* * -*****************************************************************************/ -int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) +/** + * Synchronous write of a word to memory or a system register. + * As a side effect, this flushes any queued transactions. + * + * @param dap The DAP connected to the MEM-AP. + * @param address Address to be written; it must be writable by + * the currently selected MEM-AP. + * @param value Word that will be written. + * + * @return ERROR_OK for success; the data was written. Otherwise a fault code. + */ +int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address, + uint32_t value) { - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); - dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value); - - return ERROR_OK; -} + int retval = mem_ap_write_u32(dap, address, value); -int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value) -{ - mem_ap_write_u32(swjdp, address, value); + if (retval != ERROR_OK) + return retval; - return swjdp_transaction_endcheck(swjdp); + return dap_run(dap); } /***************************************************************************** * * -* mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * +* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) * * * * Write a buffer in target order (little endian) * * * *****************************************************************************/ -int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) { int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; - uint8_t* pBuffer = buffer; - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + const uint8_t *pBuffer = buffer; count >>= 2; wcount = count; /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (writecount = 0; writecount < count; writecount++) - { + if (adr & 0x3u) { + for (writecount = 0; writecount < count; writecount++) { int i; uint32_t outvalue; memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++) - { - *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue; + for (i = 0; i < 4; i++) { + *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue; outvalue >>= 8; adr++; } @@ -477,10 +292,9 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, } } - while (wcount > 0) - { + while (wcount > 0) { /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -488,49 +302,47 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, if (blocksize == 0) blocksize = 1; - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; - for (writecount = 0; writecount < blocksize; writecount++) - { - dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount); + for (writecount = 0; writecount < blocksize; writecount++) { + retval = dap_queue_ap_write(dap, AP_REG_DRW, + *(uint32_t *) ((void *) (buffer + 4 * writecount))); + if (retval != ERROR_OK) + break; } - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) - { + retval = dap_run(dap); + if (retval == ERROR_OK) { wcount = wcount - blocksize; address = address + 4 * blocksize; buffer = buffer + 4 * blocksize; - } - else - { + } else errorcount++; - } - if (errorcount > 1) - { + if (errorcount > 1) { LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } } return retval; } -int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, + const uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count >> 1; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; @@ -539,41 +351,47 @@ int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int if (blocksize == 0) blocksize = 1; - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; writecount = blocksize; - do - { + do { nbytes = MIN((writecount << 1), 4); - if (nbytes < 4) - { - if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + if (nbytes < 4) { + retval = mem_ap_write_buf_u16(dap, buffer, + nbytes, address); + if (retval != ERROR_OK) { + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } address += nbytes >> 1; - } - else - { + } else { uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } memcpy(&outvalue, buffer, sizeof(uint32_t)); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + retval = dap_queue_ap_write(dap, + AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) { + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } } @@ -587,23 +405,28 @@ int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int return retval; } -int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; if (count >= 4) - return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address); + return mem_ap_write_buf_packed_u16(dap, buffer, count, address); - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + while (count > 0) { + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; uint16_t svalue; memcpy(&svalue, buffer, sizeof(uint16_t)); uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + count -= 2; address += 2; buffer += 2; @@ -612,60 +435,63 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, + const uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; int wcount, blocksize, writecount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; writecount = blocksize; - do - { + do { nbytes = MIN(writecount, 4); - if (nbytes < 4) - { - if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + if (nbytes < 4) { + retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address); + if (retval != ERROR_OK) { + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } address += nbytes; - } - else - { + } else { uint32_t outvalue; memcpy(&outvalue, buffer, sizeof(uint32_t)); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer + (address & 0x3)) = outvalue; + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } memcpy(&outvalue, buffer, sizeof(uint32_t)); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + retval = dap_queue_ap_write(dap, + AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) { + LOG_WARNING("Block write error address " + "0x%" PRIx32 ", count 0x%x", + address, count); + return retval; } } @@ -679,21 +505,26 @@ int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int return retval; } -int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) { int retval = ERROR_OK; if (count >= 4) - return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address); + return mem_ap_write_buf_packed_u8(dap, buffer, count, address); - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + while (count > 0) { + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); - dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue); - retval = swjdp_transaction_endcheck(swjdp); + retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + count--; address++; buffer++; @@ -702,28 +533,38 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -/********************************************************************************* -* * -* mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) * -* * -* Read block fast in target order (little endian) into a buffer * -* * -**********************************************************************************/ -int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +/* FIXME don't import ... this is a temporary workaround for the + * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific. + */ +extern int adi_jtag_dp_scan(struct adiv5_dap *dap, + uint8_t instr, uint8_t reg_addr, uint8_t RnW, + uint8_t *outvalue, uint8_t *invalue, uint8_t *ack); + +/** + * Synchronously read a block of 32-bit words into a buffer + * @param dap The DAP connected to the MEM-AP. + * @param buffer where the words will be stored (in host byte order). + * @param count How many words to read. + * @param address Memory address from which to read words; all the + * words must be readable by the currently selected MEM-AP. + */ +int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, + int count, uint32_t address) { int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; uint32_t adr = address; - uint8_t* pBuffer = buffer; - - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + uint8_t *pBuffer = buffer; count >>= 2; wcount = count; - while (wcount > 0) - { - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + while (wcount > 0) { + /* Adjust to read blocks within boundaries aligned to the + * TAR autoincrement size (at least 2^10). Autoincrement + * mode avoids an extra per-word roundtrip to update TAR. + */ + blocksize = max_tar_block_size(dap->tar_autoincr_block, + address); if (wcount < blocksize) blocksize = wcount; @@ -731,48 +572,69 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, if (blocksize == 0) blocksize = 1; - dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, + address); + if (retval != ERROR_OK) + return retval; + + /* FIXME remove these three calls to adi_jtag_dp_scan(), + * so this routine becomes transport-neutral. Be careful + * not to cause performance problems with JTAG; would it + * suffice to loop over dap_queue_ap_read(), or would that + * be slower when JTAG is the chosen transport? + */ /* Scan out first read */ - adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL); - for (readcount = 0; readcount < blocksize - 1; readcount++) - { - /* Scan out read instruction and scan in previous value */ - adi_jtag_dp_scan(swjdp, DAP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); + retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, + DPAP_READ, 0, NULL, NULL); + if (retval != ERROR_OK) + return retval; + for (readcount = 0; readcount < blocksize - 1; readcount++) { + /* Scan out next read; scan in posted value for the + * previous one. Assumes read is acked "OK/FAULT", + * and CTRL_STAT says that meant "OK". + */ + retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, + DPAP_READ, 0, buffer + 4 * readcount, + &dap->ack); + if (retval != ERROR_OK) + return retval; } - /* Scan in last value */ - adi_jtag_dp_scan(swjdp, DAP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); - if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) - { - wcount = wcount - blocksize; - address += 4 * blocksize; - buffer += 4 * blocksize; - } - else - { - errorcount++; - } + /* Scan in last posted value; RDBUFF has no other effect, + * assuming ack is OK/FAULT and CTRL_STAT says "OK". + */ + retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF, + DPAP_READ, 0, buffer + 4 * readcount, + &dap->ack); + if (retval != ERROR_OK) + return retval; - if (errorcount > 1) - { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + retval = dap_run(dap); + if (retval != ERROR_OK) { + errorcount++; + if (errorcount <= 1) { + /* try again */ + continue; + } + LOG_WARNING("Block read error address 0x%" PRIx32, address); + return retval; } + wcount = wcount - blocksize; + address += 4 * blocksize; + buffer += 4 * blocksize; } /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) - { - for (readcount = 0; readcount < count; readcount++) - { + if (adr & 0x3u) { + for (readcount = 0; readcount < count; readcount++) { int i; uint32_t data; memcpy(&data, pBuffer, sizeof(uint32_t)); - for (i = 0; i < 4; i++) - { - *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3)); + for (i = 0; i < 4; i++) { + *((uint8_t *)pBuffer) = + (data >> 8 * (adr & 0x3)); pBuffer++; adr++; } @@ -782,46 +644,46 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, return retval; } -int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, + uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count >> 1; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; /* handle unaligned data at 4k boundary */ if (blocksize == 0) blocksize = 1; readcount = blocksize; - do - { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { + do { + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } nbytes = MIN((readcount << 1), 4); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -834,32 +696,42 @@ int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp, uint8_t *buffer, int return retval; } -int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Synchronously read a block of 16-bit halfwords into a buffer + * @param dap The DAP connected to the MEM-AP. + * @param buffer where the halfwords will be stored (in host byte order). + * @param count How many halfwords to read. + * @param address Memory address from which to read words; all the + * words must be readable by the currently selected MEM-AP. + */ +int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, + int count, uint32_t address) { uint32_t invalue, i; int retval = ERROR_OK; if (count >= 4) - return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address); + return mem_ap_read_buf_packed_u16(dap, buffer, count, address); - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + while (count > 0) { + retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + break; - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - retval = swjdp_transaction_endcheck(swjdp); - if (address & 0x1) - { - for (i = 0; i < 2; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + retval = dap_run(dap); + if (retval != ERROR_OK) + break; + + if (address & 0x1) { + for (i = 0; i < 2; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } - } - else - { + } else { uint16_t svalue = (invalue >> 8 * (address & 0x3)); memcpy(buffer, &svalue, sizeof(uint16_t)); address += 2; @@ -877,43 +749,43 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, * The solution is to arrange for a large out/in scan in this loop and * and convert data afterwards. */ -int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, + uint8_t *buffer, int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; - swjdp->trans_mode = TRANS_MODE_COMPOSITE; - wcount = count; - while (wcount > 0) - { + while (wcount > 0) { int nbytes; /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address); + blocksize = max_tar_block_size(dap->tar_autoincr_block, address); if (wcount < blocksize) blocksize = wcount; - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address); + if (retval != ERROR_OK) + return retval; readcount = blocksize; - do - { - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) - { + do { + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) { LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return ERROR_JTAG_DEVICE_ERROR; + return retval; } nbytes = MIN(readcount, 4); - for (i = 0; i < nbytes; i++) - { - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + for (i = 0; i < nbytes; i++) { + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } @@ -926,22 +798,35 @@ int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp, uint8_t *buffer, int c return retval; } -int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) +/** + * Synchronously read a block of bytes into a buffer + * @param dap The DAP connected to the MEM-AP. + * @param buffer where the bytes will be stored. + * @param count How many bytes to read. + * @param address Memory address from which to read data; all the + * data must be readable by the currently selected MEM-AP. + */ +int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, + int count, uint32_t address) { uint32_t invalue; int retval = ERROR_OK; if (count >= 4) - return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address); + return mem_ap_read_buf_packed_u8(dap, buffer, count, address); - swjdp->trans_mode = TRANS_MODE_COMPOSITE; + while (count > 0) { + retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + break; - while (count > 0) - { - dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue); - retval = swjdp_transaction_endcheck(swjdp); - *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3)); + *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); count--; address++; buffer++; @@ -950,122 +835,504 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u return retval; } -int ahbap_debugport_init(struct swjdp_common *swjdp) +/*--------------------------------------------------------------------*/ +/* Wrapping function with selection of AP */ +/*--------------------------------------------------------------------*/ +int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t *value) +{ + dap_ap_select(swjdp, ap); + return mem_ap_read_u32(swjdp, address, value); +} + +int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t value) +{ + dap_ap_select(swjdp, ap); + return mem_ap_write_u32(swjdp, address, value); +} + +int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t *value) +{ + dap_ap_select(swjdp, ap); + return mem_ap_read_atomic_u32(swjdp, address, value); +} + +int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t value) +{ + dap_ap_select(swjdp, ap); + return mem_ap_write_atomic_u32(swjdp, address, value); +} + +int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap, + uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_read_buf_u8(swjdp, buffer, count, address); +} + +int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap, + uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_read_buf_u16(swjdp, buffer, count, address); +} + +int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_read_buf_u32(swjdp, buffer, count, address); +} + +int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap, + const uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_write_buf_u8(swjdp, buffer, count, address); +} + +int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap, + const uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_write_buf_u16(swjdp, buffer, count, address); +} + +int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, + const uint8_t *buffer, int count, uint32_t address) +{ + dap_ap_select(swjdp, ap); + return mem_ap_write_buf_u32(swjdp, buffer, count, address); +} + +#define MDM_REG_STAT 0x00 +#define MDM_REG_CTRL 0x04 +#define MDM_REG_ID 0xfc + +#define MDM_STAT_FMEACK (1<<0) +#define MDM_STAT_FREADY (1<<1) +#define MDM_STAT_SYSSEC (1<<2) +#define MDM_STAT_SYSRES (1<<3) +#define MDM_STAT_FMEEN (1<<5) +#define MDM_STAT_BACKDOOREN (1<<6) +#define MDM_STAT_LPEN (1<<7) +#define MDM_STAT_VLPEN (1<<8) +#define MDM_STAT_LLSMODEXIT (1<<9) +#define MDM_STAT_VLLSXMODEXIT (1<<10) +#define MDM_STAT_CORE_HALTED (1<<16) +#define MDM_STAT_CORE_SLEEPDEEP (1<<17) +#define MDM_STAT_CORESLEEPING (1<<18) + +#define MEM_CTRL_FMEIP (1<<0) +#define MEM_CTRL_DBG_DIS (1<<1) +#define MEM_CTRL_DBG_REQ (1<<2) +#define MEM_CTRL_SYS_RES_REQ (1<<3) +#define MEM_CTRL_CORE_HOLD_RES (1<<4) +#define MEM_CTRL_VLLSX_DBG_REQ (1<<5) +#define MEM_CTRL_VLLSX_DBG_ACK (1<<6) +#define MEM_CTRL_VLLSX_STAT_ACK (1<<7) + +/** + * + */ +int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) +{ + uint32_t val; + int retval; + enum reset_types jtag_reset_config = jtag_get_reset_config(); + + dap_ap_select(dap, 1); + + /* first check mdm-ap id register */ + retval = dap_queue_ap_read(dap, MDM_REG_ID, &val); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + + if (val != 0x001C0000) { + LOG_DEBUG("id doesn't match %08X != 0x001C0000", val); + dap_ap_select(dap, 0); + return ERROR_FAIL; + } + + /* read and parse status register + * it's important that the device is out of + * reset here + */ + retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + + LOG_DEBUG("MDM_REG_STAT %08X", val); + + if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) { + LOG_DEBUG("MDMAP: system is secured, masserase needed"); + + if (!(val & MDM_STAT_FMEEN)) + LOG_DEBUG("MDMAP: masserase is disabled"); + else { + /* we need to assert reset */ + if (jtag_reset_config & RESET_HAS_SRST) { + /* default to asserting srst */ + adapter_assert_reset(); + } else { + LOG_DEBUG("SRST not configured"); + dap_ap_select(dap, 0); + return ERROR_FAIL; + } + + while (1) { + retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + /* read status register and wait for ready */ + retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + LOG_DEBUG("MDM_REG_STAT %08X", val); + + if ((val & 1)) + break; + } + + while (1) { + retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + /* read status register */ + retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + LOG_DEBUG("MDM_REG_STAT %08X", val); + /* read control register and wait for ready */ + retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val); + if (retval != ERROR_OK) + return retval; + dap_run(dap); + LOG_DEBUG("MDM_REG_CTRL %08X", val); + + if (val == 0x00) + break; + } + } + } + + dap_ap_select(dap, 0); + + return ERROR_OK; +} + +/** */ +struct dap_syssec_filter { + /** */ + uint32_t idcode; + /** */ + int (*dap_init)(struct adiv5_dap *dap); +}; + +/** */ +static struct dap_syssec_filter dap_syssec_filter_data[] = { + { 0x4BA00477, dap_syssec_kinetis_mdmap } +}; + +/** + * + */ +int dap_syssec(struct adiv5_dap *dap) +{ + unsigned int i; + struct jtag_tap *tap; + + for (i = 0; i < sizeof(dap_syssec_filter_data); i++) { + tap = dap->jtag_info->tap; + + while (tap != NULL) { + if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) { + LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode); + dap_syssec_filter_data[i].dap_init(dap); + } + tap = tap->next_tap; + } + } + + return ERROR_OK; +} + +/*--------------------------------------------------------------------------*/ + + +/* FIXME don't import ... just initialize as + * part of DAP transport setup +*/ +extern const struct dap_ops jtag_dp_ops; + +/*--------------------------------------------------------------------------*/ + +/** + * Initialize a DAP. This sets up the power domains, prepares the DP + * for further use, and arranges to use AP #0 for all AP operations + * until dap_ap-select() changes that policy. + * + * @param dap The DAP being initialized. + * + * @todo Rename this. We also need an initialization scheme which account + * for SWD transports not just JTAG; that will need to address differences + * in layering. (JTAG is useful without any debug target; but not SWD.) + * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP. + */ +int ahbap_debugport_init(struct adiv5_dap *dap) { - uint32_t idreg, romaddr, dummy; uint32_t ctrlstat; int cnt = 0; int retval; LOG_DEBUG(" "); - swjdp->apsel = 0; - swjdp->ap_csw_value = -1; - swjdp->ap_tar_value = -1; - swjdp->trans_mode = TRANS_MODE_ATOMIC; - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); + /* test for initialized low level jtag hardware + * this always fails for stlink hardware + */ + if (!dap->jtag_info) { + LOG_DEBUG("No low level jtag hardware found"); + return ERROR_OK; + } - swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + /* JTAG-DP or SWJ-DP, in JTAG mode + * ... for SWD mode this is patched as part + * of link switchover + */ + if (!dap->ops) + dap->ops = &jtag_dp_ops; + + /* Default MEM-AP setup. + * + * REVISIT AP #0 may be an inappropriate default for this. + * Should we probe, or take a hint from the caller? + * Presumably we can ignore the possibility of multiple APs. + */ + dap->ap_current = !0; + dap_ap_select(dap, 0); + + /* DP initialization */ + + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; - dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval = jtag_execute_queue()) != ERROR_OK) + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR); + if (retval != ERROR_OK) + return retval; + + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; + + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; + + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; /* Check that we have debug power domains activated */ - while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) - { - LOG_DEBUG("swjdp: wait CDBGPWRUPACK"); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval = jtag_execute_queue()) != ERROR_OK) + while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { + LOG_DEBUG("DAP: wait CDBGPWRUPACK"); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; alive_sleep(10); } - while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) - { - LOG_DEBUG("swjdp: wait CSYSPWRUPACK"); - dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT); - if ((retval = jtag_execute_queue()) != ERROR_OK) + while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { + LOG_DEBUG("DAP: wait CSYSPWRUPACK"); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) return retval; alive_sleep(10); } - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; /* With debug power on we can activate OVERRUN checking */ - swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; - dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); - dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT); - - dap_ap_read_reg_u32(swjdp, 0xFC, &idreg); - dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr); + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; - LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr); + dap_syssec(dap); return ERROR_OK; } -/* CID interpretation -- see ARM IHI 0029B section 3 */ -static const char *class_description[16] ={ +/* CID interpretation -- see ARM IHI 0029B section 3 + * and ARM IHI 0031A table 13-3. + */ +static const char *class_description[16] = { "Reserved", "ROM table", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", - "Reserved", "DESS", "Generic IP component", "PrimeCell or System component" + "Reserved", "OptimoDE DESS", + "Generic IP component", "PrimeCell or System component" }; -static bool -is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) +static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) { return cid3 == 0xb1 && cid2 == 0x05 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; } -int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel) +int dap_get_debugbase(struct adiv5_dap *dap, int ap, + uint32_t *out_dbgbase, uint32_t *out_apid) { + uint32_t ap_old; + int retval; + uint32_t dbgbase, apid; + + /* AP address is in bits 31:24 of DP_SELECT */ + if (ap >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + + ap_old = dap->ap_current; + dap_ap_select(dap, ap); + + retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - uint32_t dbgbase,apid; + /* Excavate the device ID code */ + struct jtag_tap *tap = dap->jtag_info->tap; + while (tap != NULL) { + if (tap->hasidcode) + break; + tap = tap->next_tap; + } + if (tap == NULL || !tap->hasidcode) + return ERROR_OK; + + dap_ap_select(dap, ap_old); + + /* The asignment happens only here to prevent modification of these + * values before they are certain. */ + *out_dbgbase = dbgbase; + *out_apid = apid; + + return ERROR_OK; +} + +int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, + uint32_t dbgbase, uint8_t type, uint32_t *addr) +{ + uint32_t ap_old; + uint32_t romentry, entry_offset = 0, component_base, devtype; + int retval = ERROR_FAIL; + + if (ap >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; + + ap_old = dap->ap_current; + dap_ap_select(dap, ap); + + do { + retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | + entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; + + component_base = (dbgbase & 0xFFFFF000) + + (romentry & 0xFFFFF000); + + if (romentry & 0x1) { + retval = mem_ap_read_atomic_u32(dap, + (component_base & 0xfffff000) | 0xfcc, + &devtype); + if ((devtype & 0xff) == type) { + *addr = component_base; + retval = ERROR_OK; + break; + } + } + entry_offset += 4; + } while (romentry > 0); + + dap_ap_select(dap, ap_old); + + return retval; +} + +static int dap_info_command(struct command_context *cmd_ctx, + struct adiv5_dap *dap, int ap) +{ + int retval; + uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */ int romtable_present = 0; uint8_t mem_ap; - uint32_t apselold; + uint32_t ap_old; + + retval = dap_get_debugbase(dap, ap, &dbgbase, &apid); + if (retval != ERROR_OK) + return retval; + + ap_old = dap->ap_current; + dap_ap_select(dap, ap); - apselold = swjdp->apsel; - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - swjdp_transaction_endcheck(swjdp); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); - command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid); - if (apid) - { - switch (apid&0x0F) - { + command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); + if (apid) { + switch (apid&0x0F) { case 0: - command_print(cmd_ctx, "\tType is jtag-ap"); + command_print(cmd_ctx, "\tType is JTAG-AP"); break; case 1: - command_print(cmd_ctx, "\tType is mem-ap AHB"); + command_print(cmd_ctx, "\tType is MEM-AP AHB"); break; case 2: - command_print(cmd_ctx, "\tType is mem-ap APB"); + command_print(cmd_ctx, "\tType is MEM-AP APB"); break; default: - command_print(cmd_ctx, "\tUnknown AP-type"); - break; + command_print(cmd_ctx, "\tUnknown AP type"); + break; } - command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase); - } - else - { - command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel); - } + + /* NOTE: a MEM-AP may have a single CoreSight component that's + * not a ROM table ... or have no such components at all. + */ + if (mem_ap) + command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase); + } else + command_print(cmd_ctx, "No AP found at this ap 0x%x", ap); romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); - if (romtable_present) - { - uint32_t cid0,cid1,cid2,cid3,memtype,romentry; + if (romtable_present) { + uint32_t cid0, cid1, cid2, cid3, memtype, romentry; uint16_t entry_offset; /* bit 16 of apid indicates a memory access port */ @@ -1075,18 +1342,32 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp command_print(cmd_ctx, "\tROM table in legacy format"); /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); - mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); - swjdp_transaction_endcheck(swjdp); + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) - command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32 - ", CID2 0x%2.2" PRIx32 - ", CID1 0x%2.2" PRIx32 - ", CID0 0x%2.2" PRIx32, - cid3, cid2, cid1, cid0); + command_print(cmd_ctx, "\tCID3 0x%2.2x" + ", CID2 0x%2.2x" + ", CID1 0x%2.2x" + ", CID0 0x%2.2x", + (unsigned) cid3, (unsigned)cid2, + (unsigned) cid1, (unsigned) cid0); if (memtype & 0x01) command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); else @@ -1095,43 +1376,63 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ entry_offset = 0; - do - { - mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry); - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry); - if (romentry&0x01) - { + do { + retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; + command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry); + if (romentry & 0x01) { uint32_t c_cid0, c_cid1, c_cid2, c_cid3; uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; - uint32_t component_start, component_base; + uint32_t component_base; unsigned part_num; char *type, *full; - component_base = (uint32_t)((dbgbase & 0xFFFFF000) - + (int)(romentry & 0xFFFFF000)); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFE0, &c_pid0); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFE4, &c_pid1); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFE8, &c_pid2); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFEC, &c_pid3); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFD0, &c_pid4); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFF0, &c_cid0); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFF4, &c_cid1); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFF8, &c_cid2); - mem_ap_read_atomic_u32(swjdp, - (component_base & 0xFFFFF000) | 0xFFC, &c_cid3); - component_start = component_base - 0x1000*(c_pid4 >> 4); - - command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 - ", start address 0x%" PRIx32, - component_base, component_start); + component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); + + /* IDs are in last 4K section */ + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); + if (retval != ERROR_OK) + return retval; + c_pid0 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); + if (retval != ERROR_OK) + return retval; + c_pid1 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); + if (retval != ERROR_OK) + return retval; + c_pid2 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); + if (retval != ERROR_OK) + return retval; + c_pid3 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); + if (retval != ERROR_OK) + return retval; + c_pid4 &= 0xff; + + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); + if (retval != ERROR_OK) + return retval; + c_cid0 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); + if (retval != ERROR_OK) + return retval; + c_cid1 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); + if (retval != ERROR_OK) + return retval; + c_cid2 &= 0xff; + retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); + if (retval != ERROR_OK) + return retval; + c_cid3 &= 0xff; + + command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 "," + "start address 0x%" PRIx32, component_base, + /* component may take multiple 4K pages */ + component_base - 0x1000*(c_pid4 >> 4)); command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", (int) (c_cid1 >> 4) & 0xf, /* See ARM IHI 0029B Table 3-3 */ @@ -1143,9 +1444,11 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp unsigned minor; char *major = "Reserved", *subtype = "Reserved"; - mem_ap_read_atomic_u32(swjdp, + retval = mem_ap_read_atomic_u32(dap, (component_base & 0xfffff000) | 0xfcc, &devtype); + if (retval != ERROR_OK) + return retval; minor = (devtype >> 4) & 0x0f; switch (devtype & 0x0f) { case 0: @@ -1249,23 +1552,28 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp } if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) - command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32 - ", CID2 0x%2.2" PRIx32 - ", CID1 0x%2.2" PRIx32 - ", CID0 0x%2.2" PRIx32, - c_cid3, c_cid2, c_cid1, c_cid0); - command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex " - "%2.2x %2.2x %2.2x %2.2x %2.2x", - (int) c_pid4, - (int) c_pid3, (int) c_pid2, - (int) c_pid1, (int) c_pid0); + command_print(cmd_ctx, + "\t\tCID3 0%2.2x" + ", CID2 0%2.2x" + ", CID1 0%2.2x" + ", CID0 0%2.2x", + (int) c_cid3, + (int) c_cid2, + (int)c_cid1, + (int)c_cid0); + command_print(cmd_ctx, + "\t\tPeripheral ID[4..0] = hex " + "%2.2x %2.2x %2.2x %2.2x %2.2x", + (int) c_pid4, (int) c_pid3, (int) c_pid2, + (int) c_pid1, (int) c_pid0); /* Part number interpretations are from Cortex * core specs, the CoreSight components TRM - * (ARM DDI 0314H), and ETM specs; also from - * chip observation (e.g. TI SDTI). + * (ARM DDI 0314H), CoreSight System Design + * Guide (ARM DGI 0012D) and ETM specs; also + * from chip observation (e.g. TI SDTI). */ - part_num = c_pid0 & 0xff; + part_num = (c_pid0 & 0xff); part_num |= (c_pid1 & 0x0f) << 8; switch (part_num) { case 0x000: @@ -1288,7 +1596,7 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp type = "CoreSight ETM11"; full = "(Embedded Trace)"; break; - // case 0x113: what? + /* case 0x113: what? */ case 0x120: /* from OMAP3 memmap */ type = "TI SDTI"; full = "(System Debug Trace Interface)"; @@ -1297,10 +1605,6 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp type = "TI DAPCTL"; full = ""; break; - case 0x4e0: - type = "Cortex-M3 ETM"; - full = "(Embedded Trace)"; - break; case 0x906: type = "Coresight CTI"; full = "(Cross Trigger)"; @@ -1333,6 +1637,14 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp type = "Cortex-M3 TPIU"; full = "(Trace Port Interface Unit)"; break; + case 0x924: + type = "Cortex-M3 ETM"; + full = "(Embedded Trace)"; + break; + case 0x930: + type = "Cortex-R4 ETM"; + full = "(Embedded Trace)"; + break; case 0xc08: type = "Cortex-A8 Debug"; full = "(Debug Unit)"; @@ -1344,9 +1656,7 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp } command_print(cmd_ctx, "\t\tPart is %s %s", type, full); - } - else - { + } else { if (romentry) command_print(cmd_ctx, "\t\tComponent not present"); else @@ -1354,118 +1664,229 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp } entry_offset += 4; } while (romentry > 0); - } - else - { + } else command_print(cmd_ctx, "\tNo ROM table present"); - } - dap_ap_select(swjdp, apselold); + dap_ap_select(dap, ap_old); return ERROR_OK; } -DAP_COMMAND_HANDLER(dap_baseaddr_command) +COMMAND_HANDLER(handle_dap_info_command) { - uint32_t apsel, apselsave, baseaddr; + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel; + + switch (CMD_ARGC) { + case 0: + apsel = dap->apsel; + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + + return dap_info_command(CMD_CTX, dap, apsel); +} + +COMMAND_HANDLER(dap_baseaddr_command) +{ + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apsel, baseaddr; int retval; - apselsave = swjdp->apsel; - switch (argc) { + switch (CMD_ARGC) { case 0: - apsel = swjdp->apsel; + apsel = dap->apsel; break; case 1: - COMMAND_PARSE_NUMBER(u32, args[0], apsel); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - if (apselsave != apsel) - dap_ap_select(swjdp, apsel); + dap_ap_select(dap, apsel); - dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8" PRIx32, baseaddr); + /* NOTE: assumes we're talking to a MEM-AP, which + * has a base address. There are other kinds of AP, + * though they're not common for now. This should + * use the ID register to verify it's a MEM-AP. + */ + retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - if (apselsave != apsel) - dap_ap_select(swjdp, apselsave); + command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr); return retval; } -DAP_COMMAND_HANDLER(dap_memaccess_command) +COMMAND_HANDLER(dap_memaccess_command) { + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t memaccess_tck; - switch (argc) { + switch (CMD_ARGC) { case 0: - memaccess_tck = swjdp->memaccess_tck; + memaccess_tck = dap->memaccess_tck; break; case 1: - COMMAND_PARSE_NUMBER(u32, args[0], memaccess_tck); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck); break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - swjdp->memaccess_tck = memaccess_tck; + dap->memaccess_tck = memaccess_tck; - command_print(cmd_ctx, "memory bus access delay set to %" PRIi32 " tck", - swjdp->memaccess_tck); + command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck", + dap->memaccess_tck); return ERROR_OK; } -DAP_COMMAND_HANDLER(dap_apsel_command) +COMMAND_HANDLER(dap_apsel_command) { + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + uint32_t apsel, apid; int retval; - switch (argc) { + switch (CMD_ARGC) { case 0: apsel = 0; break; case 1: - COMMAND_PARSE_NUMBER(u32, args[0], apsel); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, + dap->apsel = apsel; + dap_ap_select(dap, apsel); + + retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; + + command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, apsel, apid); return retval; } -DAP_COMMAND_HANDLER(dap_apid_command) +COMMAND_HANDLER(dap_apid_command) { - uint32_t apsel, apselsave, apid; + struct target *target = get_current_target(CMD_CTX); + struct arm *arm = target_to_arm(target); + struct adiv5_dap *dap = arm->dap; + + uint32_t apsel, apid; int retval; - apselsave = swjdp->apsel; - switch (argc) { + switch (CMD_ARGC) { case 0: - apsel = swjdp->apsel; + apsel = dap->apsel; break; case 1: - COMMAND_PARSE_NUMBER(u32, args[0], apsel); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel >= 256) + return ERROR_COMMAND_SYNTAX_ERROR; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - if (apselsave != apsel) - dap_ap_select(swjdp, apsel); + dap_ap_select(dap, apsel); + + retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8" PRIx32, apid); - if (apselsave != apsel) - dap_ap_select(swjdp, apselsave); + command_print(CMD_CTX, "0x%8.8" PRIx32, apid); return retval; } + +static const struct command_registration dap_commands[] = { + { + .name = "info", + .handler = handle_dap_info_command, + .mode = COMMAND_EXEC, + .help = "display ROM table for MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "apsel", + .handler = dap_apsel_command, + .mode = COMMAND_EXEC, + .help = "Set the currently selected AP (default 0) " + "and display the result", + .usage = "[ap_num]", + }, + { + .name = "apid", + .handler = dap_apid_command, + .mode = COMMAND_EXEC, + .help = "return ID register from AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "baseaddr", + .handler = dap_baseaddr_command, + .mode = COMMAND_EXEC, + .help = "return debug base address from MEM-AP " + "(default currently selected AP)", + .usage = "[ap_num]", + }, + { + .name = "memaccess", + .handler = dap_memaccess_command, + .mode = COMMAND_EXEC, + .help = "set/get number of extra tck for MEM-AP memory " + "bus access [0-255]", + .usage = "[cycles]", + }, + COMMAND_REGISTRATION_DONE +}; + +const struct command_registration dap_command_handlers[] = { + { + .name = "dap", + .mode = COMMAND_EXEC, + .help = "DAP command group", + .usage = "", + .chain = dap_commands, + }, + COMMAND_REGISTRATION_DONE +};