X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.c;h=d9f3bd74f86e209520f9bd864095ee110306cf51;hp=fd3a92ce3f45c0a3946bff69dfc3241eb16b8e0f;hb=8c67115c7b02a10668c9b05cd4fd95a8a7d01c88;hpb=ec5e4bae251e01d2b7681e370a6c5e82a81e5962 diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index fd3a92ce3f..d9f3bd74f8 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -10,6 +10,9 @@ * * * Copyright (C) 2009-2010 by David Brownell * * * + * Copyright (C) 2013 by Andreas Fritiofson * + * andreas.fritiofson@gmail.com * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -21,9 +24,7 @@ * GNU General Public License for more details. * * * * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * along with this program. If not, see . * ***************************************************************************/ /** @@ -72,7 +73,10 @@ #include "jtag/interface.h" #include "arm.h" #include "arm_adi_v5.h" +#include #include +#include +#include /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */ @@ -82,7 +86,7 @@ */ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address) { - return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2; + return tar_autoincr_block - ((tar_autoincr_block - 1) & address); } /*************************************************************************** @@ -91,42 +95,100 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address * * ***************************************************************************/ -/** - * Select one of the APs connected to the specified DAP. The - * selection is implicitly used with future AP transactions. - * This is a NOP if the specified AP is already selected. - * - * @param dap The DAP - * @param apsel Number of the AP to (implicitly) use with further - * transactions. This normally identifies a MEM-AP. - */ -void dap_ap_select(struct adiv5_dap *dap, uint8_t ap) +static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw) { - uint32_t new_ap = (ap << 24) & 0xFF000000; + csw |= ap->csw_default; - if (new_ap != dap->ap_current) { - dap->ap_current = new_ap; - /* Switching AP invalidates cached values. - * Values MUST BE UPDATED BEFORE AP ACCESS. - */ - dap->ap_bank_value = -1; - dap->ap_csw_value = -1; - dap->ap_tar_value = -1; + if (csw != ap->csw_value) { + /* LOG_DEBUG("DAP: Set CSW %x",csw); */ + int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw); + if (retval != ERROR_OK) { + ap->csw_value = 0; + return retval; + } + ap->csw_value = csw; + } + return ERROR_OK; +} + +static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar) +{ + if (!ap->tar_valid || tar != ap->tar_value) { + /* LOG_DEBUG("DAP: Set TAR %x",tar); */ + int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar); + if (retval != ERROR_OK) { + ap->tar_valid = false; + return retval; + } + ap->tar_value = tar; + ap->tar_valid = true; + } + return ERROR_OK; +} + +static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar) +{ + int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar); + if (retval != ERROR_OK) { + ap->tar_valid = false; + return retval; + } + + retval = dap_run(ap->dap); + if (retval != ERROR_OK) { + ap->tar_valid = false; + return retval; + } + + ap->tar_value = *tar; + ap->tar_valid = true; + return ERROR_OK; +} + +static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap) +{ + switch (ap->csw_value & CSW_ADDRINC_MASK) { + case CSW_ADDRINC_SINGLE: + switch (ap->csw_value & CSW_SIZE_MASK) { + case CSW_8BIT: + return 1; + case CSW_16BIT: + return 2; + case CSW_32BIT: + return 4; + default: + return 0; + } + case CSW_ADDRINC_PACKED: + return 4; } + return 0; +} + +/* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW + */ +static void mem_ap_update_tar_cache(struct adiv5_ap *ap) +{ + if (!ap->tar_valid) + return; + + uint32_t inc = mem_ap_get_tar_increment(ap); + if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value)) + ap->tar_valid = false; + else + ap->tar_value += inc; } /** * Queue transactions setting up transfer parameters for the * currently selected MEM-AP. * - * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2 + * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2 * initiate data reads or writes using memory or peripheral addresses. * If the CSW is configured for it, the TAR may be automatically * incremented after each transfer. * - * @todo Rename to reflect it being specifically a MEM-AP function. - * - * @param dap The DAP connected to the MEM-AP. + * @param ap The MEM-AP. * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this * matches the cached value, the register is not changed. * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this @@ -134,35 +196,22 @@ void dap_ap_select(struct adiv5_dap *dap, uint8_t ap) * * @return ERROR_OK if the transaction was properly queued, else a fault code. */ -int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar) +static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar) { int retval; - - csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT; - if (csw != dap->ap_csw_value) { - /* LOG_DEBUG("DAP: Set CSW %x",csw); */ - retval = dap_queue_ap_write(dap, AP_REG_CSW, csw); - if (retval != ERROR_OK) - return retval; - dap->ap_csw_value = csw; - } - if (tar != dap->ap_tar_value) { - /* LOG_DEBUG("DAP: Set TAR %x",tar); */ - retval = dap_queue_ap_write(dap, AP_REG_TAR, tar); - if (retval != ERROR_OK) - return retval; - dap->ap_tar_value = tar; - } - /* Disable TAR cache when autoincrementing */ - if (csw & CSW_ADDRINC_MASK) - dap->ap_tar_value = -1; + retval = mem_ap_setup_csw(ap, csw); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_setup_tar(ap, tar); + if (retval != ERROR_OK) + return retval; return ERROR_OK; } /** * Asynchronous (queued) read of a word from memory or a system register. * - * @param dap The DAP connected to the MEM-AP performing the read. + * @param ap The MEM-AP to access. * @param address Address of the 32-bit word to read; it must be * readable by the currently selected MEM-AP. * @param value points to where the word will be stored when the @@ -170,7 +219,7 @@ int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar) * * @return ERROR_OK for success. Otherwise a fault code. */ -int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address, +int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address, uint32_t *value) { int retval; @@ -178,19 +227,20 @@ int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address, /* Use banked addressing (REG_BDx) to avoid some link traffic * (updating TAR) when reading several consecutive addresses. */ - retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF, + retval = mem_ap_setup_transfer(ap, + CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK), address & 0xFFFFFFF0); if (retval != ERROR_OK) return retval; - return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value); + return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value); } /** * Synchronous read of a word from memory or a system register. * As a side effect, this flushes any queued transactions. * - * @param dap The DAP connected to the MEM-AP performing the read. + * @param ap The MEM-AP to access. * @param address Address of the 32-bit word to read; it must be * readable by the currently selected MEM-AP. * @param value points to where the result will be stored. @@ -198,22 +248,22 @@ int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address, * @return ERROR_OK for success; *value holds the result. * Otherwise a fault code. */ -int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address, +int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address, uint32_t *value) { int retval; - retval = mem_ap_read_u32(dap, address, value); + retval = mem_ap_read_u32(ap, address, value); if (retval != ERROR_OK) return retval; - return dap_run(dap); + return dap_run(ap->dap); } /** * Asynchronous (queued) write of a word to memory or a system register. * - * @param dap The DAP connected to the MEM-AP. + * @param ap The MEM-AP to access. * @param address Address to be written; it must be writable by * the currently selected MEM-AP. * @param value Word that will be written to the address when transaction @@ -221,7 +271,7 @@ int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address, * * @return ERROR_OK for success. Otherwise a fault code. */ -int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address, +int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address, uint32_t value) { int retval; @@ -229,12 +279,13 @@ int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address, /* Use banked addressing (REG_BDx) to avoid some link traffic * (updating TAR) when writing several consecutive addresses. */ - retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF, + retval = mem_ap_setup_transfer(ap, + CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK), address & 0xFFFFFFF0); if (retval != ERROR_OK) return retval; - return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC), + return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC), value); } @@ -242,1432 +293,1252 @@ int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address, * Synchronous write of a word to memory or a system register. * As a side effect, this flushes any queued transactions. * - * @param dap The DAP connected to the MEM-AP. + * @param ap The MEM-AP to access. * @param address Address to be written; it must be writable by * the currently selected MEM-AP. * @param value Word that will be written. * * @return ERROR_OK for success; the data was written. Otherwise a fault code. */ -int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address, +int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address, uint32_t value) { - int retval = mem_ap_write_u32(dap, address, value); + int retval = mem_ap_write_u32(ap, address, value); if (retval != ERROR_OK) return retval; - return dap_run(dap); + return dap_run(ap->dap); } -/***************************************************************************** -* * -* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) * -* * -* Write a buffer in target order (little endian) * -* * -*****************************************************************************/ -int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) +/** + * Synchronous write of a block of memory, using a specific access size. + * + * @param ap The MEM-AP to access. + * @param buffer The data buffer to write. No particular alignment is assumed. + * @param size Which access size to use, in bytes. 1, 2 or 4. + * @param count The number of writes to do (in size units, not bytes). + * @param address Address to be written; it must be writable by the currently selected MEM-AP. + * @param addrinc Whether the target address should be increased for each write or not. This + * should normally be true, except when writing to e.g. a FIFO. + * @return ERROR_OK on success, otherwise an error code. + */ +static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count, + uint32_t address, bool addrinc) { - int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; - uint32_t adr = address; - const uint8_t *pBuffer = buffer; - - count >>= 2; - wcount = count; - - /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) { - for (writecount = 0; writecount < count; writecount++) { - int i; - uint32_t outvalue; - memcpy(&outvalue, pBuffer, sizeof(uint32_t)); - - for (i = 0; i < 4; i++) { - *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue; - outvalue >>= 8; - adr++; - } - pBuffer += sizeof(uint32_t); - } + struct adiv5_dap *dap = ap->dap; + size_t nbytes = size * count; + const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; + uint32_t csw_size; + uint32_t addr_xor; + int retval = ERROR_OK; + + /* TI BE-32 Quirks mode: + * Writes on big-endian TMS570 behave very strangely. Observed behavior: + * size write address bytes written in order + * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val) + * 2 TAR ^ 2 (val >> 8), (val) + * 1 TAR ^ 3 (val) + * For example, if you attempt to write a single byte to address 0, the processor + * will actually write a byte to address 3. + * + * To make writes of size < 4 work as expected, we xor a value with the address before + * setting the TAP, and we set the TAP after every transfer rather then relying on + * address increment. */ + + if (size == 4) { + csw_size = CSW_32BIT; + addr_xor = 0; + } else if (size == 2) { + csw_size = CSW_16BIT; + addr_xor = dap->ti_be_32_quirks ? 2 : 0; + } else if (size == 1) { + csw_size = CSW_8BIT; + addr_xor = dap->ti_be_32_quirks ? 3 : 0; + } else { + return ERROR_TARGET_UNALIGNED_ACCESS; } - while (wcount > 0) { - /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(dap->tar_autoincr_block, address); - if (wcount < blocksize) - blocksize = wcount; + if (ap->unaligned_access_bad && (address % size != 0)) + return ERROR_TARGET_UNALIGNED_ACCESS; + + while (nbytes > 0) { + uint32_t this_size = size; + + /* Select packed transfer if possible */ + if (addrinc && ap->packed_transfers && nbytes >= 4 + && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { + this_size = 4; + retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED); + } else { + retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr); + } - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; + if (retval != ERROR_OK) + break; - retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address); + retval = mem_ap_setup_tar(ap, address ^ addr_xor); if (retval != ERROR_OK) return retval; - for (writecount = 0; writecount < blocksize; writecount++) { - retval = dap_queue_ap_write(dap, AP_REG_DRW, - *(uint32_t *) ((void *) (buffer + 4 * writecount))); - if (retval != ERROR_OK) + /* How many source bytes each transfer will consume, and their location in the DRW, + * depends on the type of transfer and alignment. See ARM document IHI0031C. */ + uint32_t outvalue = 0; + uint32_t drw_byte_idx = address; + if (dap->ti_be_32_quirks) { + switch (this_size) { + case 4: + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor); + break; + case 2: + outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor); + outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor); + break; + case 1: + outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor); break; + } + } else { + switch (this_size) { + case 4: + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); + /* fallthrough */ + case 2: + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3); + /* fallthrough */ + case 1: + outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3); + } } + nbytes -= this_size; + + retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue); + if (retval != ERROR_OK) + break; + + mem_ap_update_tar_cache(ap); + if (addrinc) + address += this_size; + } + + /* REVISIT: Might want to have a queued version of this function that does not run. */ + if (retval == ERROR_OK) retval = dap_run(dap); - if (retval == ERROR_OK) { - wcount = wcount - blocksize; - address = address + 4 * blocksize; - buffer = buffer + 4 * blocksize; - } else - errorcount++; - - if (errorcount > 1) { - LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount); - return retval; - } + + if (retval != ERROR_OK) { + uint32_t tar; + if (mem_ap_read_tar(ap, &tar) == ERROR_OK) + LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar); + else + LOG_ERROR("Failed to write memory and, additionally, failed to find out where"); } return retval; } -static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap, - const uint8_t *buffer, int count, uint32_t address) +/** + * Synchronous read of a block of memory, using a specific access size. + * + * @param ap The MEM-AP to access. + * @param buffer The data buffer to receive the data. No particular alignment is assumed. + * @param size Which access size to use, in bytes. 1, 2 or 4. + * @param count The number of reads to do (in size units, not bytes). + * @param address Address to be read; it must be readable by the currently selected MEM-AP. + * @param addrinc Whether the target address should be increased after each read or not. This + * should normally be true, except when reading from e.g. a FIFO. + * @return ERROR_OK on success, otherwise an error code. + */ +static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count, + uint32_t adr, bool addrinc) { + struct adiv5_dap *dap = ap->dap; + size_t nbytes = size * count; + const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF; + uint32_t csw_size; + uint32_t address = adr; int retval = ERROR_OK; - int wcount, blocksize, writecount, i; - wcount = count >> 1; + /* TI BE-32 Quirks mode: + * Reads on big-endian TMS570 behave strangely differently than writes. + * They read from the physical address requested, but with DRW byte-reversed. + * For example, a byte read from address 0 will place the result in the high bytes of DRW. + * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes, + * so avoid them. */ + + if (size == 4) + csw_size = CSW_32BIT; + else if (size == 2) + csw_size = CSW_16BIT; + else if (size == 1) + csw_size = CSW_8BIT; + else + return ERROR_TARGET_UNALIGNED_ACCESS; + + if (ap->unaligned_access_bad && (adr % size != 0)) + return ERROR_TARGET_UNALIGNED_ACCESS; + + /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant + * over-allocation if packed transfers are going to be used, but determining the real need at + * this point would be messy. */ + uint32_t *read_buf = calloc(count, sizeof(uint32_t)); + /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */ + uint32_t *read_ptr = read_buf; + if (read_buf == NULL) { + LOG_ERROR("Failed to allocate read buffer"); + return ERROR_FAIL; + } + + /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many + * useful bytes it contains, and their location in the word, depends on the type of transfer + * and alignment. */ + while (nbytes > 0) { + uint32_t this_size = size; + + /* Select packed transfer if possible */ + if (addrinc && ap->packed_transfers && nbytes >= 4 + && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { + this_size = 4; + retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED); + } else { + retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr); + } + if (retval != ERROR_OK) + break; - while (wcount > 0) { - int nbytes; + retval = mem_ap_setup_tar(ap, address); + if (retval != ERROR_OK) + break; - /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(dap->tar_autoincr_block, address); + retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++); + if (retval != ERROR_OK) + break; - if (wcount < blocksize) - blocksize = wcount; + nbytes -= this_size; + if (addrinc) + address += this_size; - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; + mem_ap_update_tar_cache(ap); + } - retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address); - if (retval != ERROR_OK) - return retval; - writecount = blocksize; - - do { - nbytes = MIN((writecount << 1), 4); - - if (nbytes < 4) { - retval = mem_ap_write_buf_u16(dap, buffer, - nbytes, address); - if (retval != ERROR_OK) { - LOG_WARNING("Block write error address " - "0x%" PRIx32 ", count 0x%x", - address, count); - return retval; - } + if (retval == ERROR_OK) + retval = dap_run(dap); - address += nbytes >> 1; - } else { - uint32_t outvalue; - memcpy(&outvalue, buffer, sizeof(uint32_t)); + /* Restore state */ + address = adr; + nbytes = size * count; + read_ptr = read_buf; + + /* If something failed, read TAR to find out how much data was successfully read, so we can + * at least give the caller what we have. */ + if (retval != ERROR_OK) { + uint32_t tar; + if (mem_ap_read_tar(ap, &tar) == ERROR_OK) { + /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */ + LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar); + if (nbytes > tar - address) + nbytes = tar - address; + } else { + LOG_ERROR("Failed to read memory and, additionally, failed to find out where"); + nbytes = 0; + } + } - for (i = 0; i < nbytes; i++) { - *((uint8_t *)buffer + (address & 0x3)) = outvalue; - outvalue >>= 8; - address++; - } + /* Replay loop to populate caller's buffer from the correct word and byte lane */ + while (nbytes > 0) { + uint32_t this_size = size; - memcpy(&outvalue, buffer, sizeof(uint32_t)); - retval = dap_queue_ap_write(dap, - AP_REG_DRW, outvalue); - if (retval != ERROR_OK) - break; + if (addrinc && ap->packed_transfers && nbytes >= 4 + && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) { + this_size = 4; + } - retval = dap_run(dap); - if (retval != ERROR_OK) { - LOG_WARNING("Block write error address " - "0x%" PRIx32 ", count 0x%x", - address, count); - return retval; - } + if (dap->ti_be_32_quirks) { + switch (this_size) { + case 4: + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); + /* fallthrough */ + case 2: + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); + /* fallthrough */ + case 1: + *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3)); } + } else { + switch (this_size) { + case 4: + *buffer++ = *read_ptr >> 8 * (address++ & 3); + *buffer++ = *read_ptr >> 8 * (address++ & 3); + /* fallthrough */ + case 2: + *buffer++ = *read_ptr >> 8 * (address++ & 3); + /* fallthrough */ + case 1: + *buffer++ = *read_ptr >> 8 * (address++ & 3); + } + } - buffer += nbytes >> 1; - writecount -= nbytes >> 1; - - } while (writecount); - wcount -= blocksize; + read_ptr++; + nbytes -= this_size; } + free(read_buf); return retval; } -int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) +int mem_ap_read_buf(struct adiv5_ap *ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) { - int retval = ERROR_OK; + return mem_ap_read(ap, buffer, size, count, address, true); +} + +int mem_ap_write_buf(struct adiv5_ap *ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) +{ + return mem_ap_write(ap, buffer, size, count, address, true); +} - if (count >= 4) - return mem_ap_write_buf_packed_u16(dap, buffer, count, address); +int mem_ap_read_buf_noincr(struct adiv5_ap *ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) +{ + return mem_ap_read(ap, buffer, size, count, address, false); +} - while (count > 0) { - retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); - if (retval != ERROR_OK) - return retval; - uint16_t svalue; - memcpy(&svalue, buffer, sizeof(uint16_t)); - uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3); - retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); - if (retval != ERROR_OK) - break; +int mem_ap_write_buf_noincr(struct adiv5_ap *ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address) +{ + return mem_ap_write(ap, buffer, size, count, address, false); +} - retval = dap_run(dap); - if (retval != ERROR_OK) - break; +/*--------------------------------------------------------------------------*/ - count -= 2; - address += 2; - buffer += 2; - } - return retval; -} +#define DAP_POWER_DOMAIN_TIMEOUT (10) -static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap, - const uint8_t *buffer, int count, uint32_t address) +/*--------------------------------------------------------------------------*/ + +/** + * Invalidate cached DP select and cached TAR and CSW of all APs + */ +void dap_invalidate_cache(struct adiv5_dap *dap) { - int retval = ERROR_OK; - int wcount, blocksize, writecount, i; + dap->select = DP_SELECT_INVALID; + dap->last_read = NULL; + + int i; + for (i = 0; i <= 255; i++) { + /* force csw and tar write on the next mem-ap access */ + dap->ap[i].tar_valid = false; + dap->ap[i].csw_value = 0; + } +} - wcount = count; +/** + * Initialize a DAP. This sets up the power domains, prepares the DP + * for further use and activates overrun checking. + * + * @param dap The DAP being initialized. + */ +int dap_dp_init(struct adiv5_dap *dap) +{ + int retval; - while (wcount > 0) { - int nbytes; + LOG_DEBUG("%s", adiv5_dap_name(dap)); - /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(dap->tar_autoincr_block, address); + dap_invalidate_cache(dap); - if (wcount < blocksize) - blocksize = wcount; + for (size_t i = 0; i < 30; i++) { + /* DP initialization */ - retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address); - if (retval != ERROR_OK) - return retval; - writecount = blocksize; + retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL); + if (retval == ERROR_OK) + break; + } - do { - nbytes = MIN(writecount, 4); + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR); + if (retval != ERROR_OK) + return retval; - if (nbytes < 4) { - retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address); - if (retval != ERROR_OK) { - LOG_WARNING("Block write error address " - "0x%" PRIx32 ", count 0x%x", - address, count); - return retval; - } + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; - address += nbytes; - } else { - uint32_t outvalue; - memcpy(&outvalue, buffer, sizeof(uint32_t)); + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; - for (i = 0; i < nbytes; i++) { - *((uint8_t *)buffer + (address & 0x3)) = outvalue; - outvalue >>= 8; - address++; - } + /* Check that we have debug power domains activated */ + LOG_DEBUG("DAP: wait CDBGPWRUPACK"); + retval = dap_dp_poll_register(dap, DP_CTRL_STAT, + CDBGPWRUPACK, CDBGPWRUPACK, + DAP_POWER_DOMAIN_TIMEOUT); + if (retval != ERROR_OK) + return retval; - memcpy(&outvalue, buffer, sizeof(uint32_t)); - retval = dap_queue_ap_write(dap, - AP_REG_DRW, outvalue); - if (retval != ERROR_OK) - break; + if (!dap->ignore_syspwrupack) { + LOG_DEBUG("DAP: wait CSYSPWRUPACK"); + retval = dap_dp_poll_register(dap, DP_CTRL_STAT, + CSYSPWRUPACK, CSYSPWRUPACK, + DAP_POWER_DOMAIN_TIMEOUT); + if (retval != ERROR_OK) + return retval; + } - retval = dap_run(dap); - if (retval != ERROR_OK) { - LOG_WARNING("Block write error address " - "0x%" PRIx32 ", count 0x%x", - address, count); - return retval; - } - } + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; - buffer += nbytes; - writecount -= nbytes; + /* With debug power on we can activate OVERRUN checking */ + dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; + retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + if (retval != ERROR_OK) + return retval; - } while (writecount); - wcount -= blocksize; - } + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; return retval; } -int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address) +/** + * Initialize a DAP. This sets up the power domains, prepares the DP + * for further use, and arranges to use AP #0 for all AP operations + * until dap_ap-select() changes that policy. + * + * @param ap The MEM-AP being initialized. + */ +int mem_ap_init(struct adiv5_ap *ap) { - int retval = ERROR_OK; + /* check that we support packed transfers */ + uint32_t csw, cfg; + int retval; + struct adiv5_dap *dap = ap->dap; - if (count >= 4) - return mem_ap_write_buf_packed_u8(dap, buffer, count, address); + ap->tar_valid = false; + ap->csw_value = 0; /* force csw and tar write */ + retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0); + if (retval != ERROR_OK) + return retval; - while (count > 0) { - retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - if (retval != ERROR_OK) - return retval; - uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3); - retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue); - if (retval != ERROR_OK) - break; + retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw); + if (retval != ERROR_OK) + return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - break; + retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg); + if (retval != ERROR_OK) + return retval; - count--; - address++; - buffer++; - } + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - return retval; + if (csw & CSW_ADDRINC_PACKED) + ap->packed_transfers = true; + else + ap->packed_transfers = false; + + /* Packed transfers on TI BE-32 processors do not work correctly in + * many cases. */ + if (dap->ti_be_32_quirks) + ap->packed_transfers = false; + + LOG_DEBUG("MEM_AP Packed Transfers: %s", + ap->packed_transfers ? "enabled" : "disabled"); + + /* The ARM ADI spec leaves implementation-defined whether unaligned + * memory accesses work, only work partially, or cause a sticky error. + * On TI BE-32 processors, reads seem to return garbage in some bytes + * and unaligned writes seem to cause a sticky error. + * TODO: it would be nice to have a way to detect whether unaligned + * operations are supported on other processors. */ + ap->unaligned_access_bad = dap->ti_be_32_quirks; + + LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d", + !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01)); + + return ERROR_OK; } -/* FIXME don't import ... this is a temporary workaround for the - * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific. +/* CID interpretation -- see ARM IHI 0029B section 3 + * and ARM IHI 0031A table 13-3. */ -extern int adi_jtag_dp_scan(struct adiv5_dap *dap, - uint8_t instr, uint8_t reg_addr, uint8_t RnW, - uint8_t *outvalue, uint8_t *invalue, uint8_t *ack); +static const char *class_description[16] = { + "Reserved", "ROM table", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", + "Reserved", "OptimoDE DESS", + "Generic IP component", "PrimeCell or System component" +}; -/** - * Synchronously read a block of 32-bit words into a buffer - * @param dap The DAP connected to the MEM-AP. - * @param buffer where the words will be stored (in host byte order). - * @param count How many words to read. - * @param address Memory address from which to read words; all the - * words must be readable by the currently selected MEM-AP. - */ -int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, - int count, uint32_t address) +static bool is_dap_cid_ok(uint32_t cid) { - int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; - uint32_t adr = address; - uint8_t *pBuffer = buffer; + return (cid & 0xffff0fff) == 0xb105000d; +} - count >>= 2; - wcount = count; +/* + * This function checks the ID for each access port to find the requested Access Port type + */ +int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out) +{ + int ap_num; - while (wcount > 0) { - /* Adjust to read blocks within boundaries aligned to the - * TAR autoincrement size (at least 2^10). Autoincrement - * mode avoids an extra per-word roundtrip to update TAR. - */ - blocksize = max_tar_block_size(dap->tar_autoincr_block, - address); - if (wcount < blocksize) - blocksize = wcount; + /* Maximum AP number is 255 since the SELECT register is 8 bits */ + for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) { - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; + /* read the IDR register of the Access Port */ + uint32_t id_val = 0; - retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, - address); + int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val); if (retval != ERROR_OK) return retval; - /* FIXME remove these three calls to adi_jtag_dp_scan(), - * so this routine becomes transport-neutral. Be careful - * not to cause performance problems with JTAG; would it - * suffice to loop over dap_queue_ap_read(), or would that - * be slower when JTAG is the chosen transport? + retval = dap_run(dap); + + /* IDR bits: + * 31-28 : Revision + * 27-24 : JEDEC bank (0x4 for ARM) + * 23-17 : JEDEC code (0x3B for ARM) + * 16-13 : Class (0b1000=Mem-AP) + * 12-8 : Reserved + * 7-4 : AP Variant (non-zero for JTAG-AP) + * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP) */ - /* Scan out first read */ - retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, - DPAP_READ, 0, NULL, NULL); - if (retval != ERROR_OK) - return retval; - for (readcount = 0; readcount < blocksize - 1; readcount++) { - /* Scan out next read; scan in posted value for the - * previous one. Assumes read is acked "OK/FAULT", - * and CTRL_STAT says that meant "OK". - */ - retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW, - DPAP_READ, 0, buffer + 4 * readcount, - &dap->ack); - if (retval != ERROR_OK) - return retval; - } - - /* Scan in last posted value; RDBUFF has no other effect, - * assuming ack is OK/FAULT and CTRL_STAT says "OK". + /* Reading register for a non-existant AP should not cause an error, + * but just to be sure, try to continue searching if an error does happen. */ - retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF, - DPAP_READ, 0, buffer + 4 * readcount, - &dap->ack); - if (retval != ERROR_OK) - return retval; - - retval = dap_run(dap); - if (retval != ERROR_OK) { - errorcount++; - if (errorcount <= 1) { - /* try again */ - continue; - } - LOG_WARNING("Block read error address 0x%" PRIx32, address); - return retval; - } - wcount = wcount - blocksize; - address += 4 * blocksize; - buffer += 4 * blocksize; - } - - /* if we have an unaligned access - reorder data */ - if (adr & 0x3u) { - for (readcount = 0; readcount < count; readcount++) { - int i; - uint32_t data; - memcpy(&data, pBuffer, sizeof(uint32_t)); - - for (i = 0; i < 4; i++) { - *((uint8_t *)pBuffer) = - (data >> 8 * (adr & 0x3)); - pBuffer++; - adr++; - } + if ((retval == ERROR_OK) && /* Register read success */ + ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */ + ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/ + + LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")", + (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" : + (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" : + (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" : + (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown", + ap_num, id_val); + + *ap_out = &dap->ap[ap_num]; + return ERROR_OK; } } - return retval; + LOG_DEBUG("No %s found", + (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" : + (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" : + (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" : + (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown"); + return ERROR_FAIL; } -static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap, - uint8_t *buffer, int count, uint32_t address) +int dap_get_debugbase(struct adiv5_ap *ap, + uint32_t *dbgbase, uint32_t *apid) { - uint32_t invalue; - int retval = ERROR_OK; - int wcount, blocksize, readcount, i; - - wcount = count >> 1; - - while (wcount > 0) { - int nbytes; - - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(dap->tar_autoincr_block, address); - if (wcount < blocksize) - blocksize = wcount; - - retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address); - if (retval != ERROR_OK) - return retval; - - /* handle unaligned data at 4k boundary */ - if (blocksize == 0) - blocksize = 1; - readcount = blocksize; - - do { - retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); - return retval; - } - - nbytes = MIN((readcount << 1), 4); - - for (i = 0; i < nbytes; i++) { - *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); - buffer++; - address++; - } + struct adiv5_dap *dap = ap->dap; + int retval; - readcount -= (nbytes >> 1); - } while (readcount); - wcount -= blocksize; - } + retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase); + if (retval != ERROR_OK) + return retval; + retval = dap_queue_ap_read(ap, AP_REG_IDR, apid); + if (retval != ERROR_OK) + return retval; + retval = dap_run(dap); + if (retval != ERROR_OK) + return retval; - return retval; + return ERROR_OK; } -/** - * Synchronously read a block of 16-bit halfwords into a buffer - * @param dap The DAP connected to the MEM-AP. - * @param buffer where the halfwords will be stored (in host byte order). - * @param count How many halfwords to read. - * @param address Memory address from which to read words; all the - * words must be readable by the currently selected MEM-AP. - */ -int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, - int count, uint32_t address) +int dap_lookup_cs_component(struct adiv5_ap *ap, + uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx) { - uint32_t invalue, i; - int retval = ERROR_OK; + uint32_t romentry, entry_offset = 0, component_base, devtype; + int retval; - if (count >= 4) - return mem_ap_read_buf_packed_u16(dap, buffer, count, address); + *addr = 0; - while (count > 0) { - retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address); + do { + retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | + entry_offset, &romentry); if (retval != ERROR_OK) return retval; - retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); - if (retval != ERROR_OK) - break; - - retval = dap_run(dap); - if (retval != ERROR_OK) - break; - - if (address & 0x1) { - for (i = 0; i < 2; i++) { - *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); - buffer++; - address++; - } - } else { - uint16_t svalue = (invalue >> 8 * (address & 0x3)); - memcpy(buffer, &svalue, sizeof(uint16_t)); - address += 2; - buffer += 2; - } - count -= 2; - } - - return retval; -} - -/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many - * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s? - * - * The solution is to arrange for a large out/in scan in this loop and - * and convert data afterwards. - */ -static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap, - uint8_t *buffer, int count, uint32_t address) -{ - uint32_t invalue; - int retval = ERROR_OK; - int wcount, blocksize, readcount, i; - - wcount = count; - - while (wcount > 0) { - int nbytes; - - /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/ - blocksize = max_tar_block_size(dap->tar_autoincr_block, address); - if (wcount < blocksize) - blocksize = wcount; - - retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address); - if (retval != ERROR_OK) - return retval; - readcount = blocksize; + component_base = (dbgbase & 0xFFFFF000) + + (romentry & 0xFFFFF000); - do { - retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); + if (romentry & 0x1) { + uint32_t c_cid1; + retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1); if (retval != ERROR_OK) { - LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count); + LOG_ERROR("Can't read component with base address 0x%" PRIx32 + ", the corresponding core might be turned off", component_base); return retval; } - - nbytes = MIN(readcount, 4); - - for (i = 0; i < nbytes; i++) { - *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); - buffer++; - address++; - } - - readcount -= nbytes; - } while (readcount); - wcount -= blocksize; - } - - return retval; -} - -/** - * Synchronously read a block of bytes into a buffer - * @param dap The DAP connected to the MEM-AP. - * @param buffer where the bytes will be stored. - * @param count How many bytes to read. - * @param address Memory address from which to read data; all the - * data must be readable by the currently selected MEM-AP. - */ -int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, - int count, uint32_t address) -{ - uint32_t invalue; - int retval = ERROR_OK; - - if (count >= 4) - return mem_ap_read_buf_packed_u8(dap, buffer, count, address); - - while (count > 0) { - retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - break; - - *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3)); - count--; - address++; - buffer++; - } - - return retval; -} - -/*--------------------------------------------------------------------*/ -/* Wrapping function with selection of AP */ -/*--------------------------------------------------------------------*/ -int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap, - uint32_t address, uint32_t *value) -{ - dap_ap_select(swjdp, ap); - return mem_ap_read_u32(swjdp, address, value); -} - -int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap, - uint32_t address, uint32_t value) -{ - dap_ap_select(swjdp, ap); - return mem_ap_write_u32(swjdp, address, value); -} - -int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, - uint32_t address, uint32_t *value) -{ - dap_ap_select(swjdp, ap); - return mem_ap_read_atomic_u32(swjdp, address, value); -} - -int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, - uint32_t address, uint32_t value) -{ - dap_ap_select(swjdp, ap); - return mem_ap_write_atomic_u32(swjdp, address, value); -} - -int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap, - uint8_t *buffer, int count, uint32_t address) -{ - dap_ap_select(swjdp, ap); - return mem_ap_read_buf_u8(swjdp, buffer, count, address); -} - -int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap, - uint8_t *buffer, int count, uint32_t address) -{ - dap_ap_select(swjdp, ap); - return mem_ap_read_buf_u16(swjdp, buffer, count, address); -} - -int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, - uint8_t *buffer, int count, uint32_t address) -{ - dap_ap_select(swjdp, ap); - return mem_ap_read_buf_u32(swjdp, buffer, count, address); -} - -int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap, - const uint8_t *buffer, int count, uint32_t address) -{ - dap_ap_select(swjdp, ap); - return mem_ap_write_buf_u8(swjdp, buffer, count, address); -} - -int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap, - const uint8_t *buffer, int count, uint32_t address) -{ - dap_ap_select(swjdp, ap); - return mem_ap_write_buf_u16(swjdp, buffer, count, address); -} - -int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap, - const uint8_t *buffer, int count, uint32_t address) -{ - dap_ap_select(swjdp, ap); - return mem_ap_write_buf_u32(swjdp, buffer, count, address); -} - -#define MDM_REG_STAT 0x00 -#define MDM_REG_CTRL 0x04 -#define MDM_REG_ID 0xfc - -#define MDM_STAT_FMEACK (1<<0) -#define MDM_STAT_FREADY (1<<1) -#define MDM_STAT_SYSSEC (1<<2) -#define MDM_STAT_SYSRES (1<<3) -#define MDM_STAT_FMEEN (1<<5) -#define MDM_STAT_BACKDOOREN (1<<6) -#define MDM_STAT_LPEN (1<<7) -#define MDM_STAT_VLPEN (1<<8) -#define MDM_STAT_LLSMODEXIT (1<<9) -#define MDM_STAT_VLLSXMODEXIT (1<<10) -#define MDM_STAT_CORE_HALTED (1<<16) -#define MDM_STAT_CORE_SLEEPDEEP (1<<17) -#define MDM_STAT_CORESLEEPING (1<<18) - -#define MEM_CTRL_FMEIP (1<<0) -#define MEM_CTRL_DBG_DIS (1<<1) -#define MEM_CTRL_DBG_REQ (1<<2) -#define MEM_CTRL_SYS_RES_REQ (1<<3) -#define MEM_CTRL_CORE_HOLD_RES (1<<4) -#define MEM_CTRL_VLLSX_DBG_REQ (1<<5) -#define MEM_CTRL_VLLSX_DBG_ACK (1<<6) -#define MEM_CTRL_VLLSX_STAT_ACK (1<<7) - -/** - * - */ -int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap) -{ - uint32_t val; - int retval; - enum reset_types jtag_reset_config = jtag_get_reset_config(); - - dap_ap_select(dap, 1); - - /* first check mdm-ap id register */ - retval = dap_queue_ap_read(dap, MDM_REG_ID, &val); - if (retval != ERROR_OK) - return retval; - dap_run(dap); - - if (val != 0x001C0000) { - LOG_DEBUG("id doesn't match %08X != 0x001C0000", val); - dap_ap_select(dap, 0); - return ERROR_FAIL; - } - - /* read and parse status register - * it's important that the device is out of - * reset here - */ - retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val); - if (retval != ERROR_OK) - return retval; - dap_run(dap); - - LOG_DEBUG("MDM_REG_STAT %08X", val); - - if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) { - LOG_DEBUG("MDMAP: system is secured, masserase needed"); - - if (!(val & MDM_STAT_FMEEN)) - LOG_DEBUG("MDMAP: masserase is disabled"); - else { - /* we need to assert reset */ - if (jtag_reset_config & RESET_HAS_SRST) { - /* default to asserting srst */ - adapter_assert_reset(); - } else { - LOG_DEBUG("SRST not configured"); - dap_ap_select(dap, 0); - return ERROR_FAIL; - } - - while (1) { - retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP); - if (retval != ERROR_OK) - return retval; - dap_run(dap); - /* read status register and wait for ready */ - retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val); - if (retval != ERROR_OK) - return retval; - dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X", val); - - if ((val & 1)) + if (((c_cid1 >> 4) & 0x0f) == 1) { + retval = dap_lookup_cs_component(ap, component_base, + type, addr, idx); + if (retval == ERROR_OK) break; - } - - while (1) { - retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0); - if (retval != ERROR_OK) - return retval; - dap_run(dap); - /* read status register */ - retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val); - if (retval != ERROR_OK) - return retval; - dap_run(dap); - LOG_DEBUG("MDM_REG_STAT %08X", val); - /* read control register and wait for ready */ - retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val); - if (retval != ERROR_OK) + if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) return retval; - dap_run(dap); - LOG_DEBUG("MDM_REG_CTRL %08X", val); + } - if (val == 0x00) + retval = mem_ap_read_atomic_u32(ap, + (component_base & 0xfffff000) | 0xfcc, + &devtype); + if (retval != ERROR_OK) + return retval; + if ((devtype & 0xff) == type) { + if (!*idx) { + *addr = component_base; break; + } else + (*idx)--; } } - } + entry_offset += 4; + } while (romentry > 0); - dap_ap_select(dap, 0); + if (!*addr) + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; return ERROR_OK; } -/** */ -struct dap_syssec_filter { - /** */ - uint32_t idcode; - /** */ - int (*dap_init)(struct adiv5_dap *dap); -}; - -/** */ -static struct dap_syssec_filter dap_syssec_filter_data[] = { - { 0x4BA00477, dap_syssec_kinetis_mdmap } -}; - -/** - * - */ -int dap_syssec(struct adiv5_dap *dap) +static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid) { - unsigned int i; - struct jtag_tap *tap; - - for (i = 0; i < sizeof(dap_syssec_filter_data); i++) { - tap = dap->jtag_info->tap; - - while (tap != NULL) { - if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) { - LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode); - dap_syssec_filter_data[i].dap_init(dap); - } - tap = tap->next_tap; - } - } - - return ERROR_OK; -} + assert((component_base & 0xFFF) == 0); + assert(ap != NULL && cid != NULL && pid != NULL); -/*--------------------------------------------------------------------------*/ - - -/* FIXME don't import ... just initialize as - * part of DAP transport setup -*/ -extern const struct dap_ops jtag_dp_ops; - -/*--------------------------------------------------------------------------*/ - -/** - * Initialize a DAP. This sets up the power domains, prepares the DP - * for further use, and arranges to use AP #0 for all AP operations - * until dap_ap-select() changes that policy. - * - * @param dap The DAP being initialized. - * - * @todo Rename this. We also need an initialization scheme which account - * for SWD transports not just JTAG; that will need to address differences - * in layering. (JTAG is useful without any debug target; but not SWD.) - * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP. - */ -int ahbap_debugport_init(struct adiv5_dap *dap) -{ - uint32_t ctrlstat; - int cnt = 0; + uint32_t cid0, cid1, cid2, cid3; + uint32_t pid0, pid1, pid2, pid3, pid4; int retval; - LOG_DEBUG(" "); - - /* JTAG-DP or SWJ-DP, in JTAG mode - * ... for SWD mode this is patched as part - * of link switchover - */ - if (!dap->ops) - dap->ops = &jtag_dp_ops; - - /* Default MEM-AP setup. - * - * REVISIT AP #0 may be an inappropriate default for this. - * Should we probe, or take a hint from the caller? - * Presumably we can ignore the possibility of multiple APs. - */ - dap->ap_current = !0; - dap_ap_select(dap, 0); - - /* DP initialization */ - - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + /* IDs are in last 4K section */ + retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0); if (retval != ERROR_OK) return retval; - - retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR); + retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1); if (retval != ERROR_OK) return retval; - - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2); if (retval != ERROR_OK) return retval; - - dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; - retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3); if (retval != ERROR_OK) return retval; - - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); + retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4); if (retval != ERROR_OK) return retval; - retval = dap_run(dap); + retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0); if (retval != ERROR_OK) return retval; - - /* Check that we have debug power domains activated */ - while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) { - LOG_DEBUG("DAP: wait CDBGPWRUPACK"); - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - return retval; - alive_sleep(10); - } - - while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) { - LOG_DEBUG("DAP: wait CSYSPWRUPACK"); - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - return retval; - alive_sleep(10); - } - - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1); if (retval != ERROR_OK) return retval; - /* With debug power on we can activate OVERRUN checking */ - dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; - retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat); + retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2); if (retval != ERROR_OK) return retval; - retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL); + retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3); if (retval != ERROR_OK) return retval; - dap_syssec(dap); + retval = dap_run(ap->dap); + if (retval != ERROR_OK) + return retval; + + *cid = (cid3 & 0xff) << 24 + | (cid2 & 0xff) << 16 + | (cid1 & 0xff) << 8 + | (cid0 & 0xff); + *pid = (uint64_t)(pid4 & 0xff) << 32 + | (pid3 & 0xff) << 24 + | (pid2 & 0xff) << 16 + | (pid1 & 0xff) << 8 + | (pid0 & 0xff); return ERROR_OK; } -/* CID interpretation -- see ARM IHI 0029B section 3 - * and ARM IHI 0031A table 13-3. +/* The designer identity code is encoded as: + * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1. + * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent + * a legacy ASCII Identity Code. + * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7. + * JEP106 is a standard available from jedec.org */ -static const char *class_description[16] = { - "Reserved", "ROM table", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block", - "Reserved", "OptimoDE DESS", - "Generic IP component", "PrimeCell or System component" -}; -static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0) -{ - return cid3 == 0xb1 && cid2 == 0x05 - && ((cid1 & 0x0f) == 0) && cid0 == 0x0d; -} +/* Part number interpretations are from Cortex + * core specs, the CoreSight components TRM + * (ARM DDI 0314H), CoreSight System Design + * Guide (ARM DGI 0012D) and ETM specs; also + * from chip observation (e.g. TI SDTI). + */ + +/* The legacy code only used the part number field to identify CoreSight peripherals. + * This meant that the same part number from two different manufacturers looked the same. + * It is desirable for all future additions to identify with both part number and JEP106. + * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries. + */ -int dap_get_debugbase(struct adiv5_dap *dap, int ap, - uint32_t *out_dbgbase, uint32_t *out_apid) +#define ANY_ID 0x1000 + +#define ARM_ID 0x4BB + +static const struct { + uint16_t designer_id; + uint16_t part_num; + const char *type; + const char *full; +} dap_partnums[] = { + { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", }, + { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", }, + { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", }, + { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", }, + { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", }, + { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", }, + { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", }, + { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", }, + { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", }, + { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", }, + { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", }, + { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", }, + { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", }, + { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", }, + { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", }, + { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", }, + { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", }, + { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", }, + { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", }, + { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", }, + { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", }, + { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", }, + { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", }, + { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", }, + { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", }, + { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", }, + { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", }, + { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", }, + { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", }, + { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", }, + { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", }, + { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", }, + { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", }, + { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", }, + { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", }, + { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", }, + { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", }, + { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", }, + { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", }, + { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", }, + { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", }, + { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", }, + { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", }, + { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", }, + { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", }, + { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", }, + { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", }, + { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", }, + { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" }, + { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" }, + { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" }, + { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" }, + { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" }, + { 0x0E5, 0x000, "SHARC+/Blackfin+", "", }, + { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", }, + { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", }, + { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", }, + { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", }, + { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", }, + { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", }, + /* legacy comment: 0x113: what? */ + { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */ + { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */ +}; + +static int dap_rom_display(struct command_context *cmd_ctx, + struct adiv5_ap *ap, uint32_t dbgbase, int depth) { - uint32_t ap_old; int retval; - uint32_t dbgbase, apid; + uint64_t pid; + uint32_t cid; + char tabs[16] = ""; - /* AP address is in bits 31:24 of DP_SELECT */ - if (ap >= 256) - return ERROR_COMMAND_SYNTAX_ERROR; + if (depth > 16) { + command_print(cmd_ctx, "\tTables too deep"); + return ERROR_FAIL; + } - ap_old = dap->ap_current; - dap_ap_select(dap, ap); + if (depth) + snprintf(tabs, sizeof(tabs), "[L%02d] ", depth); - retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase); - if (retval != ERROR_OK) - return retval; - retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - return retval; + uint32_t base_addr = dbgbase & 0xFFFFF000; + command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr); - /* Excavate the device ID code */ - struct jtag_tap *tap = dap->jtag_info->tap; - while (tap != NULL) { - if (tap->hasidcode) - break; - tap = tap->next_tap; + retval = dap_read_part_id(ap, base_addr, &cid, &pid); + if (retval != ERROR_OK) { + command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off"); + return ERROR_OK; /* Don't abort recursion */ } - if (tap == NULL || !tap->hasidcode) - return ERROR_OK; - dap_ap_select(dap, ap_old); + if (!is_dap_cid_ok(cid)) { + command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid); + return ERROR_OK; /* Don't abort recursion */ + } - /* The asignment happens only here to prevent modification of these - * values before they are certain. */ - *out_dbgbase = dbgbase; - *out_apid = apid; + /* component may take multiple 4K pages */ + uint32_t size = (pid >> 36) & 0xf; + if (size > 0) + command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size)); + + command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid); + + uint8_t class = (cid >> 12) & 0xf; + uint16_t part_num = pid & 0xfff; + uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff); + + if (designer_id & 0x80) { + /* JEP106 code */ + command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s", + designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f)); + } else { + /* Legacy ASCII ID, clear invalid bits */ + designer_id &= 0x7f; + command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s", + designer_id, designer_id == 0x41 ? "ARM" : ""); + } - return ERROR_OK; -} + /* default values to be overwritten upon finding a match */ + const char *type = "Unrecognized"; + const char *full = ""; -int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, - uint32_t dbgbase, uint8_t type, uint32_t *addr) -{ - uint32_t ap_old; - uint32_t romentry, entry_offset = 0, component_base, devtype; - int retval = ERROR_FAIL; + /* search dap_partnums[] array for a match */ + for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) { - if (ap >= 256) - return ERROR_COMMAND_SYNTAX_ERROR; + if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID)) + continue; - ap_old = dap->ap_current; - dap_ap_select(dap, ap); + if (dap_partnums[entry].part_num != part_num) + continue; - do { - retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | - entry_offset, &romentry); + type = dap_partnums[entry].type; + full = dap_partnums[entry].full; + break; + } + + command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full); + command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]); + + if (class == 1) { /* ROM Table */ + uint32_t memtype; + retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype); if (retval != ERROR_OK) return retval; - component_base = (dbgbase & 0xFFFFF000) - + (romentry & 0xFFFFF000); + if (memtype & 0x01) + command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus"); + else + command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus"); - if (romentry & 0x1) { - retval = mem_ap_read_atomic_u32(dap, - (component_base & 0xfffff000) | 0xfcc, - &devtype); - if ((devtype & 0xff) == type) { - *addr = component_base; - retval = ERROR_OK; + /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */ + for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) { + uint32_t romentry; + retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry); + if (retval != ERROR_OK) + return retval; + command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "", + tabs, entry_offset, romentry); + if (romentry & 0x01) { + /* Recurse */ + retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1); + if (retval != ERROR_OK) + return retval; + } else if (romentry != 0) { + command_print(cmd_ctx, "\t\tComponent not present"); + } else { + command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs); + break; + } + } + } else if (class == 9) { /* CoreSight component */ + const char *major = "Reserved", *subtype = "Reserved"; + + uint32_t devtype; + retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype); + if (retval != ERROR_OK) + return retval; + unsigned minor = (devtype >> 4) & 0x0f; + switch (devtype & 0x0f) { + case 0: + major = "Miscellaneous"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 4: + subtype = "Validation component"; + break; + } + break; + case 1: + major = "Trace Sink"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Port"; + break; + case 2: + subtype = "Buffer"; + break; + case 3: + subtype = "Router"; + break; + } + break; + case 2: + major = "Trace Link"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Funnel, router"; + break; + case 2: + subtype = "Filter"; + break; + case 3: + subtype = "FIFO, buffer"; + break; + } + break; + case 3: + major = "Trace Source"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + case 6: + subtype = "Software"; + break; + } + break; + case 4: + major = "Debug Control"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Trigger Matrix"; + break; + case 2: + subtype = "Debug Auth"; + break; + case 3: + subtype = "Power Requestor"; + break; + } + break; + case 5: + major = "Debug Logic"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + case 5: + subtype = "Memory"; + break; + } + break; + case 6: + major = "Perfomance Monitor"; + switch (minor) { + case 0: + subtype = "other"; + break; + case 1: + subtype = "Processor"; + break; + case 2: + subtype = "DSP"; + break; + case 3: + subtype = "Engine/Coprocessor"; + break; + case 4: + subtype = "Bus"; + break; + case 5: + subtype = "Memory"; break; } + break; } - entry_offset += 4; - } while (romentry > 0); - - dap_ap_select(dap, ap_old); + command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s", + (uint8_t)(devtype & 0xff), + major, subtype); + /* REVISIT also show 0xfc8 DevId */ + } - return retval; + return ERROR_OK; } -static int dap_info_command(struct command_context *cmd_ctx, - struct adiv5_dap *dap, int ap) +int dap_info_command(struct command_context *cmd_ctx, + struct adiv5_ap *ap) { int retval; - uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */ - int romtable_present = 0; + uint32_t dbgbase, apid; uint8_t mem_ap; - uint32_t ap_old; - retval = dap_get_debugbase(dap, ap, &dbgbase, &apid); + /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ + retval = dap_get_debugbase(ap, &dbgbase, &apid); if (retval != ERROR_OK) return retval; - ap_old = dap->ap_current; - dap_ap_select(dap, ap); - - /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0)); command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid); - if (apid) { - switch (apid&0x0F) { - case 0: - command_print(cmd_ctx, "\tType is JTAG-AP"); - break; - case 1: - command_print(cmd_ctx, "\tType is MEM-AP AHB"); - break; - case 2: - command_print(cmd_ctx, "\tType is MEM-AP APB"); - break; - default: - command_print(cmd_ctx, "\tUnknown AP type"); - break; - } + if (apid == 0) { + command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num); + return ERROR_FAIL; + } - /* NOTE: a MEM-AP may have a single CoreSight component that's - * not a ROM table ... or have no such components at all. - */ - if (mem_ap) - command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase); - } else - command_print(cmd_ctx, "No AP found at this ap 0x%x", ap); - - romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF)); - if (romtable_present) { - uint32_t cid0, cid1, cid2, cid3, memtype, romentry; - uint16_t entry_offset; - - /* bit 16 of apid indicates a memory access port */ - if (dbgbase & 0x02) - command_print(cmd_ctx, "\tValid ROM table present"); - else - command_print(cmd_ctx, "\tROM table in legacy format"); + switch (apid & (IDR_JEP106 | IDR_TYPE)) { + case IDR_JEP106_ARM | AP_TYPE_JTAG_AP: + command_print(cmd_ctx, "\tType is JTAG-AP"); + break; + case IDR_JEP106_ARM | AP_TYPE_AHB_AP: + command_print(cmd_ctx, "\tType is MEM-AP AHB"); + break; + case IDR_JEP106_ARM | AP_TYPE_APB_AP: + command_print(cmd_ctx, "\tType is MEM-AP APB"); + break; + case IDR_JEP106_ARM | AP_TYPE_AXI_AP: + command_print(cmd_ctx, "\tType is MEM-AP AXI"); + break; + default: + command_print(cmd_ctx, "\tUnknown AP type"); + break; + } - /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */ - retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - return retval; + /* NOTE: a MEM-AP may have a single CoreSight component that's + * not a ROM table ... or have no such components at all. + */ + mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP; + if (mem_ap) { + command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase); - if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) - command_print(cmd_ctx, "\tCID3 0x%2.2x" - ", CID2 0x%2.2x" - ", CID1 0x%2.2x" - ", CID0 0x%2.2x", - (unsigned) cid3, (unsigned)cid2, - (unsigned) cid1, (unsigned) cid0); - if (memtype & 0x01) - command_print(cmd_ctx, "\tMEMTYPE system memory present on bus"); - else - command_print(cmd_ctx, "\tMEMTYPE System memory not present. " - "Dedicated debug bus."); + if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) { + command_print(cmd_ctx, "\tNo ROM table present"); + } else { + if (dbgbase & 0x01) + command_print(cmd_ctx, "\tValid ROM table present"); + else + command_print(cmd_ctx, "\tROM table in legacy format"); - /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */ - entry_offset = 0; - do { - retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry); - if (retval != ERROR_OK) - return retval; - command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry); - if (romentry & 0x01) { - uint32_t c_cid0, c_cid1, c_cid2, c_cid3; - uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; - uint32_t component_base; - unsigned part_num; - char *type, *full; + dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0); + } + } - component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); + return ERROR_OK; +} - /* IDs are in last 4K section */ - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0); - if (retval != ERROR_OK) - return retval; - c_pid0 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1); - if (retval != ERROR_OK) - return retval; - c_pid1 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2); - if (retval != ERROR_OK) - return retval; - c_pid2 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3); - if (retval != ERROR_OK) - return retval; - c_pid3 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4); - if (retval != ERROR_OK) - return retval; - c_pid4 &= 0xff; +enum adiv5_cfg_param { + CFG_DAP, + CFG_AP_NUM +}; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0); - if (retval != ERROR_OK) - return retval; - c_cid0 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1); - if (retval != ERROR_OK) - return retval; - c_cid1 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2); - if (retval != ERROR_OK) - return retval; - c_cid2 &= 0xff; - retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3); - if (retval != ERROR_OK) - return retval; - c_cid3 &= 0xff; - - command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 "," - "start address 0x%" PRIx32, component_base, - /* component may take multiple 4K pages */ - component_base - 0x1000*(c_pid4 >> 4)); - command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s", - (int) (c_cid1 >> 4) & 0xf, - /* See ARM IHI 0029B Table 3-3 */ - class_description[(c_cid1 >> 4) & 0xf]); - - /* CoreSight component? */ - if (((c_cid1 >> 4) & 0x0f) == 9) { - uint32_t devtype; - unsigned minor; - char *major = "Reserved", *subtype = "Reserved"; - - retval = mem_ap_read_atomic_u32(dap, - (component_base & 0xfffff000) | 0xfcc, - &devtype); - if (retval != ERROR_OK) - return retval; - minor = (devtype >> 4) & 0x0f; - switch (devtype & 0x0f) { - case 0: - major = "Miscellaneous"; - switch (minor) { - case 0: - subtype = "other"; - break; - case 4: - subtype = "Validation component"; - break; - } - break; - case 1: - major = "Trace Sink"; - switch (minor) { - case 0: - subtype = "other"; - break; - case 1: - subtype = "Port"; - break; - case 2: - subtype = "Buffer"; - break; - } - break; - case 2: - major = "Trace Link"; - switch (minor) { - case 0: - subtype = "other"; - break; - case 1: - subtype = "Funnel, router"; - break; - case 2: - subtype = "Filter"; - break; - case 3: - subtype = "FIFO, buffer"; - break; - } - break; - case 3: - major = "Trace Source"; - switch (minor) { - case 0: - subtype = "other"; - break; - case 1: - subtype = "Processor"; - break; - case 2: - subtype = "DSP"; - break; - case 3: - subtype = "Engine/Coprocessor"; - break; - case 4: - subtype = "Bus"; - break; - } - break; - case 4: - major = "Debug Control"; - switch (minor) { - case 0: - subtype = "other"; - break; - case 1: - subtype = "Trigger Matrix"; - break; - case 2: - subtype = "Debug Auth"; - break; - } - break; - case 5: - major = "Debug Logic"; - switch (minor) { - case 0: - subtype = "other"; - break; - case 1: - subtype = "Processor"; - break; - case 2: - subtype = "DSP"; - break; - case 3: - subtype = "Engine/Coprocessor"; - break; - } - break; - } - command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s", - (unsigned) (devtype & 0xff), - major, subtype); - /* REVISIT also show 0xfc8 DevId */ +static const Jim_Nvp nvp_config_opts[] = { + { .name = "-dap", .value = CFG_DAP }, + { .name = "-ap-num", .value = CFG_AP_NUM }, + { .name = NULL, .value = -1 } +}; + +int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi) +{ + struct adiv5_private_config *pc; + int e; + + pc = (struct adiv5_private_config *)target->private_config; + if (pc == NULL) { + pc = calloc(1, sizeof(struct adiv5_private_config)); + pc->ap_num = DP_APSEL_INVALID; + target->private_config = pc; + } + + target->has_dap = true; + + if (goi->argc > 0) { + Jim_Nvp *n; + + Jim_SetEmptyResult(goi->interp); + + /* check first if topmost item is for us */ + e = Jim_Nvp_name2value_obj(goi->interp, nvp_config_opts, + goi->argv[0], &n); + if (e != JIM_OK) + return JIM_CONTINUE; + + e = Jim_GetOpt_Obj(goi, NULL); + if (e != JIM_OK) + return e; + + switch (n->value) { + case CFG_DAP: + if (goi->isconfigure) { + Jim_Obj *o_t; + struct adiv5_dap *dap; + e = Jim_GetOpt_Obj(goi, &o_t); + if (e != JIM_OK) + return e; + dap = dap_instance_by_jim_obj(goi->interp, o_t); + if (dap == NULL) { + Jim_SetResultString(goi->interp, "DAP name invalid!", -1); + return JIM_ERR; + } + if (pc->dap != NULL && pc->dap != dap) { + Jim_SetResultString(goi->interp, + "DAP assignment cannot be changed after target was created!", -1); + return JIM_ERR; + } + if (target->tap_configured) { + Jim_SetResultString(goi->interp, + "-chain-position and -dap configparams are mutually exclusive!", -1); + return JIM_ERR; + } + pc->dap = dap; + target->tap = dap->tap; + target->dap_configured = true; + } else { + if (goi->argc != 0) { + Jim_WrongNumArgs(goi->interp, + goi->argc, goi->argv, + "NO PARAMS"); + return JIM_ERR; } - if (!is_dap_cid_ok(cid3, cid2, cid1, cid0)) - command_print(cmd_ctx, - "\t\tCID3 0%2.2x" - ", CID2 0%2.2x" - ", CID1 0%2.2x" - ", CID0 0%2.2x", - (int) c_cid3, - (int) c_cid2, - (int)c_cid1, - (int)c_cid0); - command_print(cmd_ctx, - "\t\tPeripheral ID[4..0] = hex " - "%2.2x %2.2x %2.2x %2.2x %2.2x", - (int) c_pid4, (int) c_pid3, (int) c_pid2, - (int) c_pid1, (int) c_pid0); - - /* Part number interpretations are from Cortex - * core specs, the CoreSight components TRM - * (ARM DDI 0314H), CoreSight System Design - * Guide (ARM DGI 0012D) and ETM specs; also - * from chip observation (e.g. TI SDTI). - */ - part_num = (c_pid0 & 0xff); - part_num |= (c_pid1 & 0x0f) << 8; - switch (part_num) { - case 0x000: - type = "Cortex-M3 NVIC"; - full = "(Interrupt Controller)"; - break; - case 0x001: - type = "Cortex-M3 ITM"; - full = "(Instrumentation Trace Module)"; - break; - case 0x002: - type = "Cortex-M3 DWT"; - full = "(Data Watchpoint and Trace)"; - break; - case 0x003: - type = "Cortex-M3 FBP"; - full = "(Flash Patch and Breakpoint)"; - break; - case 0x00d: - type = "CoreSight ETM11"; - full = "(Embedded Trace)"; - break; - /* case 0x113: what? */ - case 0x120: /* from OMAP3 memmap */ - type = "TI SDTI"; - full = "(System Debug Trace Interface)"; - break; - case 0x343: /* from OMAP3 memmap */ - type = "TI DAPCTL"; - full = ""; - break; - case 0x906: - type = "Coresight CTI"; - full = "(Cross Trigger)"; - break; - case 0x907: - type = "Coresight ETB"; - full = "(Trace Buffer)"; - break; - case 0x908: - type = "Coresight CSTF"; - full = "(Trace Funnel)"; - break; - case 0x910: - type = "CoreSight ETM9"; - full = "(Embedded Trace)"; - break; - case 0x912: - type = "Coresight TPIU"; - full = "(Trace Port Interface Unit)"; - break; - case 0x921: - type = "Cortex-A8 ETM"; - full = "(Embedded Trace)"; - break; - case 0x922: - type = "Cortex-A8 CTI"; - full = "(Cross Trigger)"; - break; - case 0x923: - type = "Cortex-M3 TPIU"; - full = "(Trace Port Interface Unit)"; - break; - case 0x924: - type = "Cortex-M3 ETM"; - full = "(Embedded Trace)"; - break; - case 0x930: - type = "Cortex-R4 ETM"; - full = "(Embedded Trace)"; - break; - case 0xc08: - type = "Cortex-A8 Debug"; - full = "(Debug Unit)"; - break; - default: - type = "-*- unrecognized -*-"; - full = ""; - break; + if (pc->dap == NULL) { + Jim_SetResultString(goi->interp, "DAP not configured", -1); + return JIM_ERR; + } + Jim_SetResultString(goi->interp, adiv5_dap_name(pc->dap), -1); + } + break; + + case CFG_AP_NUM: + if (goi->isconfigure) { + jim_wide ap_num; + e = Jim_GetOpt_Wide(goi, &ap_num); + if (e != JIM_OK) + return e; + if (ap_num < 0 || ap_num > DP_APSEL_MAX) { + Jim_SetResultString(goi->interp, "Invalid AP number!", -1); + return JIM_ERR; } - command_print(cmd_ctx, "\t\tPart is %s %s", - type, full); + pc->ap_num = ap_num; } else { - if (romentry) - command_print(cmd_ctx, "\t\tComponent not present"); - else - command_print(cmd_ctx, "\t\tEnd of ROM table"); + if (goi->argc != 0) { + Jim_WrongNumArgs(goi->interp, + goi->argc, goi->argv, + "NO PARAMS"); + return JIM_ERR; + } + + if (pc->ap_num == DP_APSEL_INVALID) { + Jim_SetResultString(goi->interp, "AP number not configured", -1); + return JIM_ERR; + } + Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, pc->ap_num)); } - entry_offset += 4; - } while (romentry > 0); - } else - command_print(cmd_ctx, "\tNo ROM table present"); - dap_ap_select(dap, ap_old); + break; + } + } + + return JIM_OK; +} + +int adiv5_verify_config(struct adiv5_private_config *pc) +{ + if (pc == NULL) + return ERROR_FAIL; + + if (pc->dap == NULL) + return ERROR_FAIL; return ERROR_OK; } + COMMAND_HANDLER(handle_dap_info_command) { - struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target_to_arm(target); - struct adiv5_dap *dap = arm->dap; + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); uint32_t apsel; switch (CMD_ARGC) { @@ -1676,20 +1547,19 @@ COMMAND_HANDLER(handle_dap_info_command) break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + if (apsel > DP_APSEL_MAX) + return ERROR_COMMAND_SYNTAX_ERROR; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - return dap_info_command(CMD_CTX, dap, apsel); + return dap_info_command(CMD_CTX, &dap->ap[apsel]); } COMMAND_HANDLER(dap_baseaddr_command) { - struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target_to_arm(target); - struct adiv5_dap *dap = arm->dap; - + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); uint32_t apsel, baseaddr; int retval; @@ -1700,21 +1570,19 @@ COMMAND_HANDLER(dap_baseaddr_command) case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); /* AP address is in bits 31:24 of DP_SELECT */ - if (apsel >= 256) + if (apsel > DP_APSEL_MAX) return ERROR_COMMAND_SYNTAX_ERROR; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - dap_ap_select(dap, apsel); - /* NOTE: assumes we're talking to a MEM-AP, which * has a base address. There are other kinds of AP, * though they're not common for now. This should * use the ID register to verify it's a MEM-AP. */ - retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr); + retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr); if (retval != ERROR_OK) return retval; retval = dap_run(dap); @@ -1728,15 +1596,12 @@ COMMAND_HANDLER(dap_baseaddr_command) COMMAND_HANDLER(dap_memaccess_command) { - struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target_to_arm(target); - struct adiv5_dap *dap = arm->dap; - + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); uint32_t memaccess_tck; switch (CMD_ARGC) { case 0: - memaccess_tck = dap->memaccess_tck; + memaccess_tck = dap->ap[dap->apsel].memaccess_tck; break; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck); @@ -1744,31 +1609,27 @@ COMMAND_HANDLER(dap_memaccess_command) default: return ERROR_COMMAND_SYNTAX_ERROR; } - dap->memaccess_tck = memaccess_tck; + dap->ap[dap->apsel].memaccess_tck = memaccess_tck; command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck", - dap->memaccess_tck); + dap->ap[dap->apsel].memaccess_tck); return ERROR_OK; } COMMAND_HANDLER(dap_apsel_command) { - struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target_to_arm(target); - struct adiv5_dap *dap = arm->dap; - - uint32_t apsel, apid; - int retval; + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); + uint32_t apsel; switch (CMD_ARGC) { case 0: - apsel = 0; - break; + command_print(CMD_CTX, "%" PRIi32, dap->apsel); + return ERROR_OK; case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); /* AP address is in bits 31:24 of DP_SELECT */ - if (apsel >= 256) + if (apsel > DP_APSEL_MAX) return ERROR_COMMAND_SYNTAX_ERROR; break; default: @@ -1776,27 +1637,54 @@ COMMAND_HANDLER(dap_apsel_command) } dap->apsel = apsel; - dap_ap_select(dap, apsel); + return ERROR_OK; +} - retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); - if (retval != ERROR_OK) - return retval; - retval = dap_run(dap); - if (retval != ERROR_OK) - return retval; +COMMAND_HANDLER(dap_apcsw_command) +{ + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); + uint32_t apcsw = dap->ap[dap->apsel].csw_default; + uint32_t csw_val, csw_mask; - command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, - apsel, apid); + switch (CMD_ARGC) { + case 0: + command_print(CMD_CTX, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32, + dap->apsel, apcsw); + return ERROR_OK; + case 1: + if (strcmp(CMD_ARGV[0], "default") == 0) + csw_val = CSW_DEFAULT; + else + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val); - return retval; + if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) { + LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields"); + return ERROR_COMMAND_SYNTAX_ERROR; + } + apcsw = csw_val; + break; + case 2: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask); + if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) { + LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields"); + return ERROR_COMMAND_SYNTAX_ERROR; + } + apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + dap->ap[dap->apsel].csw_default = apcsw; + + return 0; } + + COMMAND_HANDLER(dap_apid_command) { - struct target *target = get_current_target(CMD_CTX); - struct arm *arm = target_to_arm(target); - struct adiv5_dap *dap = arm->dap; - + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); uint32_t apsel, apid; int retval; @@ -1807,16 +1695,14 @@ COMMAND_HANDLER(dap_apid_command) case 1: COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); /* AP address is in bits 31:24 of DP_SELECT */ - if (apsel >= 256) + if (apsel > DP_APSEL_MAX) return ERROR_COMMAND_SYNTAX_ERROR; break; default: return ERROR_COMMAND_SYNTAX_ERROR; } - dap_ap_select(dap, apsel); - - retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid); + retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid); if (retval != ERROR_OK) return retval; retval = dap_run(dap); @@ -1828,7 +1714,111 @@ COMMAND_HANDLER(dap_apid_command) return retval; } -static const struct command_registration dap_commands[] = { +COMMAND_HANDLER(dap_apreg_command) +{ + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); + uint32_t apsel, reg, value; + struct adiv5_ap *ap; + int retval; + + if (CMD_ARGC < 2 || CMD_ARGC > 3) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel); + /* AP address is in bits 31:24 of DP_SELECT */ + if (apsel > DP_APSEL_MAX) + return ERROR_COMMAND_SYNTAX_ERROR; + ap = dap_ap(dap, apsel); + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg); + if (reg >= 256 || (reg & 3)) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 3) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value); + switch (reg) { + case MEM_AP_REG_CSW: + ap->csw_default = 0; /* invalid, force write */ + retval = mem_ap_setup_csw(ap, value); + break; + case MEM_AP_REG_TAR: + ap->tar_valid = false; /* invalid, force write */ + retval = mem_ap_setup_tar(ap, value); + break; + default: + retval = dap_queue_ap_write(ap, reg, value); + break; + } + } else { + retval = dap_queue_ap_read(ap, reg, &value); + } + if (retval == ERROR_OK) + retval = dap_run(dap); + + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC == 2) + command_print(CMD_CTX, "0x%08" PRIx32, value); + + return retval; +} + +COMMAND_HANDLER(dap_dpreg_command) +{ + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); + uint32_t reg, value; + int retval; + + if (CMD_ARGC < 1 || CMD_ARGC > 2) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg); + if (reg >= 256 || (reg & 3)) + return ERROR_COMMAND_SYNTAX_ERROR; + + if (CMD_ARGC == 2) { + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value); + retval = dap_queue_dp_write(dap, reg, value); + } else { + retval = dap_queue_dp_read(dap, reg, &value); + } + if (retval == ERROR_OK) + retval = dap_run(dap); + + if (retval != ERROR_OK) + return retval; + + if (CMD_ARGC == 1) + command_print(CMD_CTX, "0x%08" PRIx32, value); + + return retval; +} + +COMMAND_HANDLER(dap_ti_be_32_quirks_command) +{ + struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA); + uint32_t enable = dap->ti_be_32_quirks; + + switch (CMD_ARGC) { + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable); + if (enable > 1) + return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; + } + dap->ti_be_32_quirks = enable; + command_print(CMD_CTX, "TI BE-32 quirks mode %s", + enable ? "enabled" : "disabled"); + + return 0; +} + +const struct command_registration dap_instance_commands[] = { { .name = "info", .handler = handle_dap_info_command, @@ -1840,11 +1830,19 @@ static const struct command_registration dap_commands[] = { { .name = "apsel", .handler = dap_apsel_command, - .mode = COMMAND_EXEC, + .mode = COMMAND_ANY, .help = "Set the currently selected AP (default 0) " "and display the result", .usage = "[ap_num]", }, + { + .name = "apcsw", + .handler = dap_apcsw_command, + .mode = COMMAND_ANY, + .help = "Set CSW default bits", + .usage = "[value [mask]]", + }, + { .name = "apid", .handler = dap_apid_command, @@ -1853,6 +1851,22 @@ static const struct command_registration dap_commands[] = { "(default currently selected AP)", .usage = "[ap_num]", }, + { + .name = "apreg", + .handler = dap_apreg_command, + .mode = COMMAND_EXEC, + .help = "read/write a register from AP " + "(reg is byte address of a word register, like 0 4 8...)", + .usage = "ap_num reg [value]", + }, + { + .name = "dpreg", + .handler = dap_dpreg_command, + .mode = COMMAND_EXEC, + .help = "read/write a register from DP " + "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)", + .usage = "reg [value]", + }, { .name = "baseaddr", .handler = dap_baseaddr_command, @@ -1869,16 +1883,12 @@ static const struct command_registration dap_commands[] = { "bus access [0-255]", .usage = "[cycles]", }, - COMMAND_REGISTRATION_DONE -}; - -const struct command_registration dap_command_handlers[] = { { - .name = "dap", - .mode = COMMAND_EXEC, - .help = "DAP command group", - .usage = "", - .chain = dap_commands, + .name = "ti_be_32_quirks", + .handler = dap_ti_be_32_quirks_command, + .mode = COMMAND_CONFIG, + .help = "set/get quirks mode for TI TMS450/TMS570 processors", + .usage = "[enable]", }, COMMAND_REGISTRATION_DONE };