X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=09b6b0d7401ae9d205c13e04f0da70e2c6e41cc0;hp=27a2f2f8a907b7e836f5b669b1d33f4d8ee21b16;hb=677b02b475870b7d9e5d86e9bf61dc28dae5a6e4;hpb=0649fb2f6c7e1bea138769ecc2ec8dc17ae98044 diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index 27a2f2f8a9..09b6b0d740 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -18,8 +18,9 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ + #ifndef ARM_ADI_V5_H #define ARM_ADI_V5_H @@ -46,18 +47,23 @@ #define DPAP_WRITE 0 #define DPAP_READ 1 +#define BANK_REG(bank, reg) (((bank) << 4) | (reg)) + /* A[3:0] for DP registers; A[1:0] are always zero. * - JTAG accesses all of these via JTAG_DP_DPACC, except for * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT). * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL */ -#define DP_IDCODE 0 /* SWD: read */ -#define DP_ABORT 0 /* SWD: write */ -#define DP_CTRL_STAT 0x4 /* r/w */ -#define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */ -#define DP_RESEND 0x8 /* SWD: read */ -#define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */ -#define DP_RDBUFF 0xC /* read-only */ +#define DP_IDCODE BANK_REG(0x0, 0x0) /* SWD: read */ +#define DP_ABORT BANK_REG(0x0, 0x0) /* SWD: write */ +#define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* r/w */ +#define DP_RESEND BANK_REG(0x0, 0x8) /* SWD: read */ +#define DP_SELECT BANK_REG(0x0, 0x8) /* JTAG: r/w; SWD: write */ +#define DP_RDBUFF BANK_REG(0x0, 0xC) /* read-only */ +#define DP_WCR BANK_REG(0x1, 0x4) /* SWD: r/w */ + +#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8))) /* 1..4 clocks */ +#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr)))) /* impl defined */ /* Fields of the DP's AP ABORT register */ #define DAPABORT (1 << 0) @@ -112,6 +118,7 @@ /* 30:24 - implementation-defined! */ #define CSW_HPROT (1 << 25) /* ? */ #define CSW_MASTER_DEBUG (1 << 29) /* ? */ +#define CSW_SPROT (1 << 30) #define CSW_DBGSWENABLE (1 << 31) /** @@ -130,21 +137,23 @@ * as part of setting up a debug session (if all the dual-role JTAG/SWD * signals are available). */ -struct adiv5_dap -{ +struct adiv5_dap { const struct dap_ops *ops; struct arm_jtag *jtag_info; /* Control config */ uint32_t dp_ctrl_stat; + uint32_t apcsw[256]; + uint32_t apsel; + /** * Cache for DP_SELECT bits identifying the current AP. A DAP may * connect to multiple APs, such as one MEM-AP for general access, * another reserved for accessing debug modules, and a JTAG-DP. * "-1" indicates no cached value. */ - uint32_t apsel; + uint32_t ap_current; /** * Cache for DP_SELECT bits identifying the current four-word AP @@ -154,6 +163,13 @@ struct adiv5_dap */ uint32_t ap_bank_value; + /** + * Cache for DP_SELECT bits identifying the current four-word DP + * register bank. This caches DP register addresss bits 7:4; JTAG + * and SWD access primitves pass address bits 3:2; bits 1:0 are zero. + */ + uint32_t dp_bank_value; + /** * Cache for (MEM-AP) AP_REG_CSW register value. This is written to * configure an access mode, such as autoincrementing AP_REG_TAR during @@ -171,13 +187,32 @@ struct adiv5_dap /* information about current pending SWjDP-AHBAP transaction */ uint8_t ack; + /** + * Holds the pointer to the destination word for the last queued read, + * for use with posted AP read sequence optimization. + */ + uint32_t *last_read; + /** * Configures how many extra tck clocks are added after starting a * MEM-AP access before we try to read its status (and/or result). */ uint32_t memaccess_tck; + /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */ uint32_t tar_autoincr_block; + + /* true if packed transfers are supported by the MEM-AP */ + bool packed_transfers; + + /* true if unaligned memory access is not supported by the MEM-AP */ + bool unaligned_access_bad; + + /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering + * despite lack of support in the ARMv7 architecture. Memory access through + * the AHB-AP has strange byte ordering these processors, and we need to + * swizzle appropriately. */ + bool ti_be_32_quirks; }; /** @@ -185,7 +220,7 @@ struct adiv5_dap * both JTAG and SWD transports. All submitted transactions are logically * queued, until the queue is executed by run(). Some implementations might * execute transactions as soon as they're submitted, but no status is made - * availablue until run(). + * available until run(). */ struct dap_ops { /** If the DAP transport isn't SWD, it must be JTAG. Upper level @@ -193,10 +228,6 @@ struct dap_ops { */ bool is_swd; - /** Reads the DAP's IDCODe register. */ - int (*queue_idcode_read)(struct adiv5_dap *dap, - uint8_t *ack, uint32_t *data); - /** DP register read. */ int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data); @@ -210,6 +241,7 @@ struct dap_ops { /** AP register write. */ int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data); + /** AP operation abort. */ int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack); @@ -217,23 +249,14 @@ struct dap_ops { int (*run)(struct adiv5_dap *dap); }; -/** - * Queue an IDCODE register read. This is primarily useful for SWD - * transports, where it is required as part of link initialization. - * (For JTAG, this register is read as part of scan chain setup.) - * - * @param dap The DAP used for reading. - * @param ack Pointer to where transaction status will be stored. - * @param data Pointer saying where to store the IDCODE value. - * - * @return ERROR_OK for success, else a fault code. +/* + * Access Port types */ -static inline int dap_queue_idcode_read(struct adiv5_dap *dap, - uint8_t *ack, uint32_t *data) -{ - assert(dap->ops != NULL); - return dap->ops->queue_idcode_read(dap, ack, data); -} +enum ap_type { + AP_TYPE_AHB_AP = 0x01, /* AHB Memory-AP */ + AP_TYPE_APB_AP = 0x02, /* APB Memory-AP */ + AP_TYPE_JTAG_AP = 0x10 /* JTAG-AP - JTAG master for controlling other JTAG devices */ +}; /** * Queue a DP register read. @@ -243,7 +266,7 @@ static inline int dap_queue_idcode_read(struct adiv5_dap *dap, * @param dap The DAP used for reading. * @param reg The two-bit number of the DP register being read. * @param data Pointer saying where to store the register's value - * (in host endianness). + * (in host endianness). * * @return ERROR_OK for success, else a fault code. */ @@ -278,7 +301,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap, * @param dap The DAP used for reading. * @param reg The number of the AP register being read. * @param data Pointer saying where to store the register's value - * (in host endianness). + * (in host endianness). * * @return ERROR_OK for success, else a fault code. */ @@ -338,14 +361,55 @@ static inline int dap_run(struct adiv5_dap *dap) return dap->ops->run(dap); } +static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg, + uint32_t *value) +{ + int retval; + + retval = dap_queue_dp_read(dap, reg, value); + if (retval != ERROR_OK) + return retval; + + return dap_run(dap); +} + +static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg, + uint32_t mask, uint32_t value, int timeout) +{ + assert(timeout > 0); + assert((value & mask) == value); + + int ret; + uint32_t regval; + LOG_DEBUG("DAP: poll %x, mask 0x08%" PRIx32 ", value 0x%08" PRIx32, + reg, mask, value); + do { + ret = dap_dp_read_atomic(dap, reg, ®val); + if (ret != ERROR_OK) + return ret; + + if ((regval & mask) == value) + break; + + alive_sleep(10); + } while (--timeout); + + if (!timeout) { + LOG_DEBUG("DAP: poll %x timeout", reg); + return ERROR_FAIL; + } else { + return ERROR_OK; + } +} + /** Accessor for currently selected DAP-AP number (0..255) */ static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp) { - return (uint8_t)(swjdp ->apsel >> 24); + return (uint8_t)(swjdp->ap_current >> 24); } /* AP selection applies to future AP transactions */ -void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel); +void dap_ap_select(struct adiv5_dap *dap, uint8_t ap); /* Queued AP transactions */ int dap_setup_accessport(struct adiv5_dap *swjdp, @@ -361,28 +425,53 @@ int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value); -/* MEM-AP memory mapped bus block transfers */ -int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, - uint8_t *buffer, int count, uint32_t address); -int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, - uint8_t *buffer, int count, uint32_t address); -int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, - uint8_t *buffer, int count, uint32_t address); - -int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, - uint8_t *buffer, int count, uint32_t address); -int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, - uint8_t *buffer, int count, uint32_t address); -int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, - uint8_t *buffer, int count, uint32_t address); +/* Queued MEM-AP memory mapped single word transfers with selection of ap */ +int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t *value); +int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t value); + +/* Synchronous MEM-AP memory mapped single word transfers with selection of ap */ +int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t *value); +int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap, + uint32_t address, uint32_t value); + +/* Synchronous MEM-AP memory mapped bus block transfers */ +int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, + uint32_t count, uint32_t address, bool addrinc); +int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, + uint32_t count, uint32_t address, bool addrinc); + +/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */ +int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); +int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); + +/* Synchronous, non-incrementing buffer functions for accessing fifos, with + * selection of ap */ +int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap, + uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); +int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap, + const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address); /* Initialisation of the debug system, power domains and registers */ int ahbap_debugport_init(struct adiv5_dap *swjdp); /* Probe the AP for ROM Table location */ -int dap_get_debugbase(struct adiv5_dap *dap, int apsel, +int dap_get_debugbase(struct adiv5_dap *dap, int ap, uint32_t *dbgbase, uint32_t *apid); +/* Probe Access Ports to find a particular type */ +int dap_find_ap(struct adiv5_dap *dap, + enum ap_type type_to_find, + uint8_t *ap_num_out); + +/* Lookup CoreSight component */ +int dap_lookup_cs_component(struct adiv5_dap *dap, int ap, + uint32_t dbgbase, uint8_t type, uint32_t *addr); + struct target; /* Put debug link into SWD mode */