X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_adi_v5.h;h=9f0dea9119186466e38f2f389c0f6f89290ba71e;hp=03a75f497d01ed9d0db9dcf51da24ad3ab67ff48;hb=d007764fe88958aa556f060054d55841e1d9306d;hpb=fa93174a56c0aca1201bebf88795d6fe31c18aa1

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 03a75f497d..9f0dea9119 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -18,8 +18,9 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
+
 #ifndef ARM_ADI_V5_H
 #define ARM_ADI_V5_H
 
@@ -59,8 +60,8 @@
 #define DP_SELECT		0x8		/* JTAG: r/w; SWD: write */
 #define DP_RDBUFF		0xC		/* read-only */
 
-#define WCR_TO_TRN(wcr) (1 + (3 & ((wcr)) >> 8))	/* 1..4 clocks */
-#define WCR_TO_PRESCALE(wcr) (7 & ((wcr)))		/* impl defined */
+#define WCR_TO_TRN(wcr) ((uint32_t)(1 + (3 & ((wcr)) >> 8)))	/* 1..4 clocks */
+#define WCR_TO_PRESCALE(wcr) ((uint32_t)(7 & ((wcr))))		/* impl defined */
 
 /* Fields of the DP's AP ABORT register */
 #define DAPABORT		(1 << 0)
@@ -115,6 +116,7 @@
 /* 30:24 - implementation-defined! */
 #define CSW_HPROT			(1 << 25)		/* ? */
 #define CSW_MASTER_DEBUG	(1 << 29)		/* ? */
+#define CSW_SPROT (1 << 30)
 #define CSW_DBGSWENABLE		(1 << 31)
 
 /**
@@ -133,15 +135,14 @@
  * as part of setting up a debug session (if all the dual-role JTAG/SWD
  * signals are available).
  */
-struct adiv5_dap
-{
+struct adiv5_dap {
 	const struct dap_ops *ops;
 
 	struct arm_jtag *jtag_info;
 	/* Control config */
 	uint32_t dp_ctrl_stat;
 
-
+	uint32_t apcsw[256];
 	uint32_t apsel;
 
 	/**
@@ -182,8 +183,21 @@ struct adiv5_dap
 	 * MEM-AP access before we try to read its status (and/or result).
 	 */
 	uint32_t	memaccess_tck;
+
 	/* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
 	uint32_t tar_autoincr_block;
+
+	/* true if packed transfers are supported by the MEM-AP */
+	bool packed_transfers;
+
+	/* true if unaligned memory access is not supported by the MEM-AP */
+	bool unaligned_access_bad;
+
+	/* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
+	 * despite lack of support in the ARMv7 architecture. Memory access through
+	 * the AHB-AP has strange byte ordering these processors, and we need to
+	 * swizzle appropriately. */
+	bool ti_be_32_quirks;
 };
 
 /**
@@ -216,6 +230,10 @@ struct dap_ops {
 	/** AP register write. */
 	int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
 			uint32_t data);
+	/** AP read block. */
+	int (*queue_ap_read_block)(struct adiv5_dap *dap, unsigned reg,
+			uint32_t blocksize, uint8_t *buffer);
+
 	/** AP operation abort. */
 	int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
 
@@ -223,6 +241,15 @@ struct dap_ops {
 	int (*run)(struct adiv5_dap *dap);
 };
 
+/*
+ * Access Port types
+ */
+enum ap_type {
+	AP_TYPE_AHB_AP  = 0x01,  /* AHB Memory-AP */
+	AP_TYPE_APB_AP  = 0x02,  /* APB Memory-AP */
+	AP_TYPE_JTAG_AP = 0x10   /* JTAG-AP - JTAG master for controlling other JTAG devices */
+};
+
 /**
  * Queue an IDCODE register read.  This is primarily useful for SWD
  * transports, where it is required as part of link initialization.
@@ -249,7 +276,7 @@ static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
  * @param dap The DAP used for reading.
  * @param reg The two-bit number of the DP register being read.
  * @param data Pointer saying where to store the register's value
- * 	(in host endianness).
+ * (in host endianness).
  *
  * @return ERROR_OK for success, else a fault code.
  */
@@ -284,7 +311,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap,
  * @param dap The DAP used for reading.
  * @param reg The number of the AP register being read.
  * @param data Pointer saying where to store the register's value
- * 	(in host endianness).
+ * (in host endianness).
  *
  * @return ERROR_OK for success, else a fault code.
  */
@@ -311,6 +338,24 @@ static inline int dap_queue_ap_write(struct adiv5_dap *dap,
 	return dap->ops->queue_ap_write(dap, reg, data);
 }
 
+/**
+ * Queue an AP block read.
+ *
+ * @param dap The DAP used for reading.
+ * @param reg The number of the AP register being read.
+ * @param blocksize The number of the AP register being read.
+ * @param buffer Pointer saying where to store the data
+ * (in host endianness).
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_ap_read_block(struct adiv5_dap *dap,
+		unsigned reg, unsigned blocksize, uint8_t *buffer)
+{
+	assert(dap->ops != NULL);
+	return dap->ops->queue_ap_read_block(dap, reg, blocksize, buffer);
+}
+
 /**
  * Queue an AP abort operation.  The current AP transaction is aborted,
  * including any update of the transaction counter.  The AP is left in
@@ -344,14 +389,26 @@ static inline int dap_run(struct adiv5_dap *dap)
 	return dap->ops->run(dap);
 }
 
+static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
+				     uint32_t *value)
+{
+	int retval;
+
+	retval = dap_queue_dp_read(dap, reg, value);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return dap_run(dap);
+}
+
 /** Accessor for currently selected DAP-AP number (0..255) */
 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
 {
-	return (uint8_t)(swjdp ->ap_current >> 24);
+	return (uint8_t)(swjdp->ap_current >> 24);
 }
 
 /* AP selection applies to future AP transactions */
-void dap_ap_select(struct adiv5_dap *dap,uint8_t ap);
+void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
 
 /* Queued AP transactions */
 int dap_setup_accessport(struct adiv5_dap *swjdp,
@@ -367,23 +424,6 @@ int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
 		uint32_t address, uint32_t value);
 
-/* MEM-AP memory mapped bus block transfers */
-int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address);
-
-int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address);
-
-
-
 /* Queued MEM-AP memory mapped single word transfers with selection of ap */
 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 		uint32_t address, uint32_t *value);
@@ -396,22 +436,24 @@ int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 		uint32_t address, uint32_t value);
 
-/* MEM-AP memory mapped bus block transfers with selection of ap */
-int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
-		uint8_t *buffer, int count, uint32_t address);
-
-int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
-		uint8_t *buffer, int count, uint32_t address);
-int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
-		uint8_t *buffer, int count, uint32_t address);
-
-
+/* Synchronous MEM-AP memory mapped bus block transfers */
+int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size,
+		uint32_t count, uint32_t address, bool addrinc);
+int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size,
+		uint32_t count, uint32_t address, bool addrinc);
+
+/* Synchronous MEM-AP memory mapped bus block transfers with selection of ap */
+int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
+		uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
+		const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+
+/* Synchronous, non-incrementing buffer functions for accessing fifos, with
+ * selection of ap */
+int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+		uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
+int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
+		const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
 
 /* Initialisation of the debug system, power domains and registers */
 int ahbap_debugport_init(struct adiv5_dap *swjdp);
@@ -420,6 +462,11 @@ int ahbap_debugport_init(struct adiv5_dap *swjdp);
 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 			uint32_t *dbgbase, uint32_t *apid);
 
+/* Probe Access Ports to find a particular type */
+int dap_find_ap(struct adiv5_dap *dap,
+			enum ap_type type_to_find,
+			uint8_t *ap_num_out);
+
 /* Lookup CoreSight component */
 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 			uint32_t dbgbase, uint8_t type, uint32_t *addr);