X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_disassembler.c;h=65086c2fdd4752d8dd5c2080b5043c0c3a29cc2a;hp=abeb08e9bfa223424a44757a54a997a076a049f0;hb=ebe9b7a6611210d185be88697457819f01df43ab;hpb=f97a1594119f90f63526e1fa8a95dbcba0acd192

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index abeb08e9bf..65086c2fdd 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -17,7 +17,7 @@
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, write to the                         *
  *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -1403,17 +1403,46 @@ static int evaluate_misc_instr(uint32_t opcode,
 				Rn);
 	}
 
-	/* Software breakpoints */
+	/* exception return */
+	if ((opcode & 0x0000000f0) == 0x00000060) {
+		if (((opcode & 0x600000) >> 21) == 3)
+			instruction->type = ARM_ERET;
+		snprintf(instruction->text,
+				128,
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tERET",
+				address,
+				opcode);
+	}
+
+	/* exception generate instructions */
 	if ((opcode & 0x0000000f0) == 0x00000070) {
-		uint32_t immediate;
-		instruction->type = ARM_BKPT;
-		immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
+		uint32_t immediate = 0;
+		char *mnemonic = NULL;
+
+		switch ((opcode & 0x600000) >> 21) {
+			case 0x1:
+				instruction->type = ARM_BKPT;
+				mnemonic = "BRKT";
+				immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
+				break;
+			case 0x2:
+				instruction->type = ARM_HVC;
+				mnemonic = "HVC";
+				immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
+				break;
+			case 0x3:
+				instruction->type = ARM_SMC;
+				mnemonic = "SMC";
+				immediate = (opcode & 0xf);
+				break;
+		}
 
 		snprintf(instruction->text,
 				128,
-				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
 				address,
 				opcode,
+				mnemonic,
 				immediate);
 	}