X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_dpm.h;h=66b2b1dfe85accdcafcb6ec76821c3fdb6ed7e68;hp=e180807fe68a0a8299206310c6f0bf00de8b5d04;hb=374127301ec1d72033b9d573b72c7abdfd61990d;hpb=50e79d60ce148f86bc93cc3248c3f6f0f81b3c3e

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index e180807fe6..66b2b1dfe8 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -126,13 +126,16 @@ struct arm_dpm {
 	/** Recent value of DSCR. */
 	uint32_t dscr;
 
-	// FIXME -- read/write DCSR methods and symbols
+	/* FIXME -- read/write DCSR methods and symbols */
 };
 
 int arm_dpm_setup(struct arm_dpm *dpm);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
 int arm_dpm_read_current_registers(struct arm_dpm *);
+int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
+
+
 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 
 void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
@@ -143,14 +146,20 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 #define DSCR_CORE_HALTED	(1 << 0)
 #define DSCR_CORE_RESTARTED	(1 << 1)
 #define DSCR_INT_DIS		(1 << 11)
-#define DSCR_ITR_EN		(1 << 13)
+#define DSCR_ITR_EN			(1 << 13)
 #define DSCR_HALT_DBG_MODE	(1 << 14)
 #define DSCR_MON_DBG_MODE	(1 << 15)
 #define DSCR_INSTR_COMP		(1 << 24)
 #define DSCR_DTR_TX_FULL	(1 << 29)
 #define DSCR_DTR_RX_FULL	(1 << 30)
 
-#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+#define DSCR_ENTRY(dscr) 	(((dscr) >> 2) & 0xf)
+#define DSCR_RUN_MODE(dscr)	((dscr) & (DSCR_CORE_HALTED | DSCR_CORE_RESTARTED))
+
+/* DRCR (debug run control register) bits */
+#define DRCR_HALT				(1 << 0)
+#define DRCR_RESTART			(1 << 1)
+#define DRCR_CLEAR_EXCEPTIONS	(1 << 2)
 
 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);