X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farm_opcodes.h;h=12a9ca8d5ebebb9383c415c55c83c67d3ba73a2c;hp=b77721e6f9314d3258c1c47236889006466630ec;hb=9b3224e8875493d2fd9f299f14e139d06554bf9c;hpb=29a8cdc3b066df0a6038775621154ba525389321

diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index b77721e6f9..12a9ca8d5e 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -86,6 +86,12 @@
 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
 	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 
+/* Load Register Word Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRW_IP(Rd, Rn)	(0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
+
 /* Load Register Halfword Immediate Post-Index
  * Rd: register to load
  * Rn: base register
@@ -98,6 +104,12 @@
  */
 #define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 
+/* Store register Word Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRW_IP(Rd, Rn)	(0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
+
 /* Store register Halfword Immediate Post-Index
  * Rd: register to store
  * Rn: base register