X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=0d890b80be9532609f18e9d941ebddfadc9f646c;hp=b88cdc8c638c0c305cb034e61d0d4afeb875a7dd;hb=9a98e83b49fe3541cb0d79924b13c2d86484aee2;hpb=53d605e12c3765aeedabf2bfe0c5cc338dc95d5a diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index b88cdc8c63..0d890b80be 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -28,26 +28,14 @@ #endif #include "armv4_5.h" +#include "arm_jtag.h" +#include "breakpoints.h" #include "arm_disassembler.h" #include "binarybuffer.h" +#include "algorithm.h" +#include "register.h" -bitfield_desc_t armv4_5_psr_bitfield_desc[] = -{ - {"M[4:0]", 5}, - {"T", 1}, - {"F", 1}, - {"I", 1}, - {"reserved", 16}, - {"J", 1}, - {"reserved", 2}, - {"Q", 1}, - {"V", 1}, - {"C", 1}, - {"Z", 1}, - {"N", 1}, -}; - char* armv4_5_core_reg_list[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc", @@ -71,7 +59,7 @@ char * armv4_5_mode_strings_list[] = }; /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */ -char** armv4_5_mode_strings = armv4_5_mode_strings_list+1; +char** armv4_5_mode_strings = armv4_5_mode_strings_list + 1; char* armv4_5_state_strings[] = { @@ -80,7 +68,7 @@ char* armv4_5_state_strings[] = int armv4_5_core_reg_arch_type = -1; -armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] = +struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] = { {0, ARMV4_5_MODE_ANY, NULL, NULL}, {1, ARMV4_5_MODE_ANY, NULL, NULL}, @@ -155,23 +143,35 @@ int armv4_5_core_reg_map[7][17] = uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -reg_t armv4_5_gdb_dummy_fp_reg = +struct reg armv4_5_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point register", + .value = armv4_5_gdb_dummy_fp_value, + .dirty = 0, + .valid = 1, + .size = 96, + .arch_info = NULL, + .arch_type = 0, }; uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0}; -reg_t armv4_5_gdb_dummy_fps_reg = +struct reg armv4_5_gdb_dummy_fps_reg = { - "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point status register", + .value = armv4_5_gdb_dummy_fps_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, + .arch_type = 0, }; -int armv4_5_get_core_reg(reg_t *reg) +int armv4_5_get_core_reg(struct reg *reg) { int retval; - armv4_5_core_reg_t *armv4_5 = reg->arch_info; - target_t *target = armv4_5->target; + struct armv4_5_core_reg *armv4_5 = reg->arch_info; + struct target *target = armv4_5->target; if (target->state != TARGET_HALTED) { @@ -185,11 +185,11 @@ int armv4_5_get_core_reg(reg_t *reg) return retval; } -int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf) +int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { - armv4_5_core_reg_t *armv4_5 = reg->arch_info; - target_t *target = armv4_5->target; - armv4_5_common_t *armv4_5_target = target->arch_info; + struct armv4_5_core_reg *armv4_5 = reg->arch_info; + struct target *target = armv4_5->target; + struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target); uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -235,9 +235,9 @@ int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf) return ERROR_OK; } -int armv4_5_invalidate_core_regs(target_t *target) +int armv4_5_invalidate_core_regs(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); int i; for (i = 0; i < 37; i++) @@ -249,12 +249,12 @@ int armv4_5_invalidate_core_regs(target_t *target) return ERROR_OK; } -reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common) +struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common) { int num_regs = 37; - reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = malloc(sizeof(struct reg) * num_regs); + struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs); int i; cache->name = "arm v4/5 registers"; @@ -278,8 +278,6 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].arch_type = armv4_5_core_reg_arch_type; reg_list[i].arch_info = &arch_info[i]; } @@ -287,9 +285,9 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 return cache; } -int armv4_5_arch_state(struct target_s *target) +int armv4_5_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -299,7 +297,7 @@ int armv4_5_arch_state(struct target_s *target) LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name, + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); @@ -307,13 +305,13 @@ int armv4_5_arch_state(struct target_s *target) return ERROR_OK; } -int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_reg_command) { char output[128]; int output_len; int mode, num; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(cmd_ctx); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -339,9 +337,9 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha { armv4_5->full_context(target); } - output_len += snprintf(output + output_len, - 128 - output_len, - "%8s: %8.8" PRIx32 " ", + output_len += snprintf(output + output_len, + 128 - output_len, + "%8s: %8.8" PRIx32 " ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name, buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32)); } @@ -359,10 +357,10 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha return ERROR_OK; } -int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_core_state_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(cmd_ctx); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -387,15 +385,15 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } -int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_disassemble_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(cmd_ctx); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); uint32_t address; - int count; + int count = 1; int i; - arm_instruction_t cur_instruction; + struct arm_instruction cur_instruction; uint32_t opcode; uint16_t thumb_opcode; int thumb = 0; @@ -406,19 +404,32 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } - if (argc < 2) - { - command_print(cmd_ctx, "usage: armv4_5 disassemble
['thumb']"); + switch (argc) { + case 3: + if (strcmp(args[2], "thumb") != 0) + goto usage; + thumb = 1; + /* FALL THROUGH */ + case 2: + COMMAND_PARSE_NUMBER(int, args[1], count); + /* FALL THROUGH */ + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], address); + if (address & 0x01) { + if (!thumb) { + command_print(cmd_ctx, "Disassemble as Thumb"); + thumb = 1; + } + address &= ~1; + } + break; + default: +usage: + command_print(cmd_ctx, + "usage: armv4_5 disassemble
[ ['thumb']]"); return ERROR_OK; } - address = strtoul(args[0], NULL, 0); - count = strtoul(args[1], NULL, 0); - - if (argc >= 3) - if (strcmp(args[2], "thumb") == 0) - thumb = 1; - for (i = 0; i < count; i++) { if (thumb) @@ -449,29 +460,37 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } -int armv4_5_register_commands(struct command_context_s *cmd_ctx) +int armv4_5_register_commands(struct command_context *cmd_ctx) { - command_t *armv4_5_cmd; + struct command *armv4_5_cmd; + + armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", + NULL, COMMAND_ANY, + "armv4/5 specific commands"); + + register_command(cmd_ctx, armv4_5_cmd, "reg", + handle_armv4_5_reg_command, COMMAND_EXEC, + "display ARM core registers"); + register_command(cmd_ctx, armv4_5_cmd, "core_state", + handle_armv4_5_core_state_command, COMMAND_EXEC, + "display/change ARM core state "); + register_command(cmd_ctx, armv4_5_cmd, "disassemble", + handle_armv4_5_disassemble_command, COMMAND_EXEC, + "disassemble instructions
[ ['thumb']]"); - armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands"); - - register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers"); - register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state "); - - register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions
['thumb']"); return ERROR_OK; } -int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) +int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); int i; if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; *reg_list_size = 26; - *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); for (i = 0; i < 16; i++) { @@ -490,10 +509,10 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list } /* wait for execution to complete and check exit point */ -static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) +static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) { @@ -501,15 +520,18 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex } if (target->state != TARGET_HALTED) { - if ((retval=target_halt(target)) != ERROR_OK) + if ((retval = target_halt(target)) != ERROR_OK) return retval; - if ((retval=target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) + if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK) { return retval; } return ERROR_TARGET_TIMEOUT; } - if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point) + + /* fast exit: ARMv5+ code can use BKPT */ + if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value, + 0, 32) != exit_point) { LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); @@ -519,10 +541,10 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex return ERROR_OK; } -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)) +int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)) { - armv4_5_common_t *armv4_5 = target->arch_info; - armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; enum armv4_5_state core_state = armv4_5->core_state; enum armv4_5_mode core_mode = armv4_5->core_mode; uint32_t context[17]; @@ -547,6 +569,13 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; + /* armv5 and later can terminate with BKPT instruction; less overhead */ + if (!exit_point && armv4_5->is_armv4) + { + LOG_ERROR("ARMv4 target needs HW breakpoint location"); + return ERROR_FAIL; + } + for (i = 0; i <= 16; i++) { if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid) @@ -565,7 +594,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem for (i = 0; i < num_reg_params; i++) { - reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -603,9 +632,11 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; } - if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) + /* terminate using a hardware or (ARMv5+) software breakpoint */ + if (exit_point && (retval = breakpoint_add(target, exit_point, + exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) { - LOG_ERROR("can't add breakpoint to finish algorithm execution"); + LOG_ERROR("can't add HW breakpoint to terminate algorithm"); return ERROR_TARGET_FAILURE; } @@ -614,9 +645,10 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem return retval; } int retvaltemp; - retval=run_it(target, exit_point, timeout_ms, arch_info); + retval = run_it(target, exit_point, timeout_ms, arch_info); - breakpoint_remove(target, exit_point); + if (exit_point) + breakpoint_remove(target, exit_point); if (retval != ERROR_OK) return retval; @@ -635,7 +667,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem if (reg_params[i].direction != PARAM_OUT) { - reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -674,12 +706,182 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem return retval; } -int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) +int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) { return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion); } -int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5) +/** + * Runs ARM code in the target to calculate a CRC32 checksum. + * + * \todo On ARMv5+, rely on BKPT termination for reduced overhead. + */ +int arm_checksum_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t *checksum) +{ + struct working_area *crc_algorithm; + struct armv4_5_algorithm armv4_5_info; + struct reg_param reg_params[2]; + int retval; + uint32_t i; + + static const uint32_t arm_crc_code[] = { + 0xE1A02000, /* mov r2, r0 */ + 0xE3E00000, /* mov r0, #0xffffffff */ + 0xE1A03001, /* mov r3, r1 */ + 0xE3A04000, /* mov r4, #0 */ + 0xEA00000B, /* b ncomp */ + /* nbyte: */ + 0xE7D21004, /* ldrb r1, [r2, r4] */ + 0xE59F7030, /* ldr r7, CRC32XOR */ + 0xE0200C01, /* eor r0, r0, r1, asl 24 */ + 0xE3A05000, /* mov r5, #0 */ + /* loop: */ + 0xE3500000, /* cmp r0, #0 */ + 0xE1A06080, /* mov r6, r0, asl #1 */ + 0xE2855001, /* add r5, r5, #1 */ + 0xE1A00006, /* mov r0, r6 */ + 0xB0260007, /* eorlt r0, r6, r7 */ + 0xE3550008, /* cmp r5, #8 */ + 0x1AFFFFF8, /* bne loop */ + 0xE2844001, /* add r4, r4, #1 */ + /* ncomp: */ + 0xE1540003, /* cmp r4, r3 */ + 0x1AFFFFF1, /* bne nbyte */ + /* end: */ + 0xEAFFFFFE, /* b end */ + /* CRC32XOR: */ + 0x04C11DB7 /* .word 0x04C11DB7 */ + }; + + retval = target_alloc_working_area(target, + sizeof(arm_crc_code), &crc_algorithm); + if (retval != ERROR_OK) + return retval; + + /* convert code into a buffer in target endianness */ + for (i = 0; i < ARRAY_SIZE(arm_crc_code); i++) { + retval = target_write_u32(target, + crc_algorithm->address + i * sizeof(uint32_t), + arm_crc_code[i]); + if (retval != ERROR_OK) + return retval; + } + + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; + + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + + buf_set_u32(reg_params[0].value, 0, 32, address); + buf_set_u32(reg_params[1].value, 0, 32, count); + + /* 20 second timeout/megabyte */ + int timeout = 20000 * (1 + (count / (1024 * 1024))); + + retval = target_run_algorithm(target, 0, NULL, 2, reg_params, + crc_algorithm->address, + crc_algorithm->address + sizeof(arm_crc_code) - 8, + timeout, &armv4_5_info); + if (retval != ERROR_OK) { + LOG_ERROR("error executing ARM crc algorithm"); + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + target_free_working_area(target, crc_algorithm); + return retval; + } + + *checksum = buf_get_u32(reg_params[0].value, 0, 32); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + + target_free_working_area(target, crc_algorithm); + + return ERROR_OK; +} + +/** + * Runs ARM code in the target to check whether a memory block holds + * all ones. NOR flash which has been erased, and thus may be written, + * holds all ones. + * + * \todo On ARMv5+, rely on BKPT termination for reduced overhead. + */ +int arm_blank_check_memory(struct target *target, + uint32_t address, uint32_t count, uint32_t *blank) +{ + struct working_area *check_algorithm; + struct reg_param reg_params[3]; + struct armv4_5_algorithm armv4_5_info; + int retval; + uint32_t i; + + static const uint32_t check_code[] = { + /* loop: */ + 0xe4d03001, /* ldrb r3, [r0], #1 */ + 0xe0022003, /* and r2, r2, r3 */ + 0xe2511001, /* subs r1, r1, #1 */ + 0x1afffffb, /* bne loop */ + /* end: */ + 0xeafffffe /* b end */ + }; + + /* make sure we have a working area */ + retval = target_alloc_working_area(target, + sizeof(check_code), &check_algorithm); + if (retval != ERROR_OK) + return retval; + + /* convert code into a buffer in target endianness */ + for (i = 0; i < ARRAY_SIZE(check_code); i++) { + retval = target_write_u32(target, + check_algorithm->address + + i * sizeof(uint32_t), + check_code[i]); + if (retval != ERROR_OK) + return retval; + } + + armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC; + armv4_5_info.core_mode = ARMV4_5_MODE_SVC; + armv4_5_info.core_state = ARMV4_5_STATE_ARM; + + init_reg_param(®_params[0], "r0", 32, PARAM_OUT); + buf_set_u32(reg_params[0].value, 0, 32, address); + + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); + buf_set_u32(reg_params[1].value, 0, 32, count); + + init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT); + buf_set_u32(reg_params[2].value, 0, 32, 0xff); + + retval = target_run_algorithm(target, 0, NULL, 3, reg_params, + check_algorithm->address, + check_algorithm->address + sizeof(check_code) - 4, + 10000, &armv4_5_info); + if (retval != ERROR_OK) { + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + target_free_working_area(target, check_algorithm); + return retval; + } + + *blank = buf_get_u32(reg_params[2].value, 0, 32); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + + target_free_working_area(target, check_algorithm); + + return ERROR_OK; +} + +int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5) { target->arch_info = armv4_5;