X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Ftarget%2Farmv4_5.c;h=aa05e83158c64a3813b3bd495dbbd643faf2eb76;hp=e1b137f968fb307a581d4ad31641b575d624a3c1;hb=04b514707f221ba00ae789e69f6f8047af96125d;hpb=f90d8fa45f2d4c9d4b7990f198b232ee55cbb4e1 diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index e1b137f968..aa05e83158 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -32,22 +32,6 @@ #include "binarybuffer.h" -bitfield_desc_t armv4_5_psr_bitfield_desc[] = -{ - {"M[4:0]", 5}, - {"T", 1}, - {"F", 1}, - {"I", 1}, - {"reserved", 16}, - {"J", 1}, - {"reserved", 2}, - {"Q", 1}, - {"V", 1}, - {"C", 1}, - {"Z", 1}, - {"N", 1}, -}; - char* armv4_5_core_reg_list[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc", @@ -80,7 +64,7 @@ char* armv4_5_state_strings[] = int armv4_5_core_reg_arch_type = -1; -armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] = +struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] = { {0, ARMV4_5_MODE_ANY, NULL, NULL}, {1, ARMV4_5_MODE_ANY, NULL, NULL}, @@ -155,23 +139,35 @@ int armv4_5_core_reg_map[7][17] = uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -reg_t armv4_5_gdb_dummy_fp_reg = +struct reg armv4_5_gdb_dummy_fp_reg = { - "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point register", + .value = armv4_5_gdb_dummy_fp_value, + .dirty = 0, + .valid = 1, + .size = 96, + .arch_info = NULL, + .arch_type = 0, }; uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0}; -reg_t armv4_5_gdb_dummy_fps_reg = +struct reg armv4_5_gdb_dummy_fps_reg = { - "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0 + .name = "GDB dummy floating-point status register", + .value = armv4_5_gdb_dummy_fps_value, + .dirty = 0, + .valid = 1, + .size = 32, + .arch_info = NULL, + .arch_type = 0, }; -int armv4_5_get_core_reg(reg_t *reg) +int armv4_5_get_core_reg(struct reg *reg) { int retval; - armv4_5_core_reg_t *armv4_5 = reg->arch_info; - target_t *target = armv4_5->target; + struct armv4_5_core_reg *armv4_5 = reg->arch_info; + struct target *target = armv4_5->target; if (target->state != TARGET_HALTED) { @@ -185,11 +181,11 @@ int armv4_5_get_core_reg(reg_t *reg) return retval; } -int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf) +int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { - armv4_5_core_reg_t *armv4_5 = reg->arch_info; - target_t *target = armv4_5->target; - armv4_5_common_t *armv4_5_target = target->arch_info; + struct armv4_5_core_reg *armv4_5 = reg->arch_info; + struct target *target = armv4_5->target; + struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target); uint32_t value = buf_get_u32(buf, 0, 32); if (target->state != TARGET_HALTED) @@ -235,9 +231,9 @@ int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf) return ERROR_OK; } -int armv4_5_invalidate_core_regs(target_t *target) +int armv4_5_invalidate_core_regs(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); int i; for (i = 0; i < 37; i++) @@ -249,12 +245,12 @@ int armv4_5_invalidate_core_regs(target_t *target) return ERROR_OK; } -reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common) +struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common) { int num_regs = 37; - reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = malloc(sizeof(struct reg) * num_regs); + struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs); int i; cache->name = "arm v4/5 registers"; @@ -278,8 +274,6 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; reg_list[i].valid = 0; - reg_list[i].bitfield_desc = NULL; - reg_list[i].num_bitfields = 0; reg_list[i].arch_type = armv4_5_core_reg_arch_type; reg_list[i].arch_info = &arch_info[i]; } @@ -287,9 +281,9 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5 return cache; } -int armv4_5_arch_state(struct target_s *target) +int armv4_5_arch_state(struct target *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -299,7 +293,7 @@ int armv4_5_arch_state(struct target_s *target) LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", armv4_5_state_strings[armv4_5->core_state], - Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name, + Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name, armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)], buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); @@ -307,13 +301,13 @@ int armv4_5_arch_state(struct target_s *target) return ERROR_OK; } -int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_reg_command) { char output[128]; int output_len; int mode, num; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(cmd_ctx); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -339,9 +333,9 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha { armv4_5->full_context(target); } - output_len += snprintf(output + output_len, - 128 - output_len, - "%8s: %8.8" PRIx32 " ", + output_len += snprintf(output + output_len, + 128 - output_len, + "%8s: %8.8" PRIx32 " ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name, buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32)); } @@ -359,10 +353,10 @@ int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, cha return ERROR_OK; } -int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_core_state_command) { - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(cmd_ctx); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { @@ -387,15 +381,15 @@ int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *c return ERROR_OK; } -int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +COMMAND_HANDLER(handle_armv4_5_disassemble_command) { int retval = ERROR_OK; - target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5 = target->arch_info; + struct target *target = get_current_target(cmd_ctx); + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); uint32_t address; - int count; + int count = 1; int i; - arm_instruction_t cur_instruction; + struct arm_instruction cur_instruction; uint32_t opcode; uint16_t thumb_opcode; int thumb = 0; @@ -406,19 +400,32 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } - if (argc < 2) - { - command_print(cmd_ctx, "usage: armv4_5 disassemble
['thumb']"); + switch (argc) { + case 3: + if (strcmp(args[2], "thumb") != 0) + goto usage; + thumb = 1; + /* FALL THROUGH */ + case 2: + COMMAND_PARSE_NUMBER(int, args[1], count); + /* FALL THROUGH */ + case 1: + COMMAND_PARSE_NUMBER(u32, args[0], address); + if (address & 0x01) { + if (!thumb) { + command_print(cmd_ctx, "Disassemble as Thumb"); + thumb = 1; + } + address &= ~1; + } + break; + default: +usage: + command_print(cmd_ctx, + "usage: armv4_5 disassemble
[ ['thumb']]"); return ERROR_OK; } - address = strtoul(args[0], NULL, 0); - count = strtoul(args[1], NULL, 0); - - if (argc >= 3) - if (strcmp(args[2], "thumb") == 0) - thumb = 1; - for (i = 0; i < count; i++) { if (thumb) @@ -449,29 +456,37 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char * return ERROR_OK; } -int armv4_5_register_commands(struct command_context_s *cmd_ctx) +int armv4_5_register_commands(struct command_context *cmd_ctx) { - command_t *armv4_5_cmd; + struct command *armv4_5_cmd; + + armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", + NULL, COMMAND_ANY, + "armv4/5 specific commands"); + + register_command(cmd_ctx, armv4_5_cmd, "reg", + handle_armv4_5_reg_command, COMMAND_EXEC, + "display ARM core registers"); + register_command(cmd_ctx, armv4_5_cmd, "core_state", + handle_armv4_5_core_state_command, COMMAND_EXEC, + "display/change ARM core state "); + register_command(cmd_ctx, armv4_5_cmd, "disassemble", + handle_armv4_5_disassemble_command, COMMAND_EXEC, + "disassemble instructions
[ ['thumb']]"); - armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands"); - - register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers"); - register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state "); - - register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions
['thumb']"); return ERROR_OK; } -int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size) +int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); int i; if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; *reg_list_size = 26; - *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); + *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); for (i = 0; i < 16; i++) { @@ -490,10 +505,10 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list } /* wait for execution to complete and check exit point */ -static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info) +static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) { @@ -509,7 +524,10 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex } return ERROR_TARGET_TIMEOUT; } - if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point) + + /* fast exit: ARMv5+ code can use BKPT */ + if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value, + 0, 32) != exit_point) { LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32)); @@ -519,10 +537,10 @@ static int armv4_5_run_algorithm_completion(struct target_s *target, uint32_t ex return ERROR_OK; } -int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info)) +int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)) { - armv4_5_common_t *armv4_5 = target->arch_info; - armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info; + struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target); + struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info; enum armv4_5_state core_state = armv4_5->core_state; enum armv4_5_mode core_mode = armv4_5->core_mode; uint32_t context[17]; @@ -547,6 +565,13 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; + /* armv5 and later can terminate with BKPT instruction; less overhead */ + if (!exit_point && armv4_5->is_armv4) + { + LOG_ERROR("ARMv4 target needs HW breakpoint location"); + return ERROR_FAIL; + } + for (i = 0; i <= 16; i++) { if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid) @@ -565,7 +590,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem for (i = 0; i < num_reg_params; i++) { - reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -603,9 +628,11 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; } - if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) + /* terminate using a hardware or (ARMv5+) software breakpoint */ + if (exit_point && (retval = breakpoint_add(target, exit_point, + exit_breakpoint_size, BKPT_HARD)) != ERROR_OK) { - LOG_ERROR("can't add breakpoint to finish algorithm execution"); + LOG_ERROR("can't add HW breakpoint to terminate algorithm"); return ERROR_TARGET_FAILURE; } @@ -616,7 +643,8 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem int retvaltemp; retval = run_it(target, exit_point, timeout_ms, arch_info); - breakpoint_remove(target, exit_point); + if (exit_point) + breakpoint_remove(target, exit_point); if (retval != ERROR_OK) return retval; @@ -635,7 +663,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem if (reg_params[i].direction != PARAM_OUT) { - reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -674,12 +702,12 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem return retval; } -int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) +int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info) { return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion); } -int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5) +int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5) { target->arch_info = armv4_5;